Re: [PATCH 2/6] iio: adc: versal-sysmon: validate temperature hysteresis

[Andy Shevchenko <andriy.shevchenko@intel.com>]

On Fri, Nov 06, 2026 at 11:35:00AM +0000, Mahapatra, Amit Kumar wrote:
> > -----Original Message-----
> > From: Andy Shevchenko <andriy.shevchenko@intel.com>
> > Sent: Tuesday, November 3, 2026 3:39 PM
> > On Mon, Nov 02, 2026 at 05:51:08PM +0530, Amit Kumar Mahapatra wrote:

...

> > >     sysmon_q8p7_to_millicelsius(upper_reg, &upper_mc);
> > >     sysmon_q8p7_to_millicelsius(lower_reg, &lower_mc);
> > > -   *hysteresis = upper_mc - lower_mc;
> > > +   *hysteresis = max(upper_mc - lower_mc, 0);
> >
> > But you can use abs_diff() and let it make the problem of the supplier.
> 
> I went with max() because an inverted pair (lower above upper) doesn't
> really describe a hysteresis, so treating it as zero seemed the safest
> reading. With abs_diff(), an inverted 80/90 pair would be read as
> 10 degrees, and the next threshold write would then set the lower
> threshold to 70.

Bu where did it come from? HW or DT? If the latter, we may just reject
the wrong values at probe time, no?

-- 
With Best Regards,
Andy Shevchenko