From: Richard Cheng <icheng@nvidia.com>
To: Fenghua Yu <fenghuay@nvidia.com>
Cc: Reinette Chatre <reinette.chatre@intel.com>,
Tony Luck <tony.luck@intel.com>, Ben Horgan <ben.horgan@arm.com>,
James Morse <james.morse@arm.com>, Will Deacon <will@kernel.org>,
Dave Martin <Dave.Martin@arm.com>,
Catalin Marinas <catalin.marinas@arm.com>,
Shaopeng Tan <tan.shaopeng@fujitsu.com>,
Chen Yu <yu.c.chen@intel.com>, Babu Moger <babu.moger@amd.com>,
Drew Fustini <fustini@kernel.org>,
Vikram Sethi <vsethi@nvidia.com>,
Shanker Donthineni <sdonthineni@nvidia.com>,
Newton Liu <newtonl@nvidia.com>,
linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH RFC v1 2/6] arm_mpam: resctrl: probe MPAMF_MBW_IDR MAX_LIM and hardlim_rw
Date: Wed, 11 Nov 2026 16:59:28 +0800 [thread overview]
Message-ID: <avQmqLUWT6VoYmnq@MWDK4CY14F> (raw)
In-Reply-To: <20261109212937.1409570-3-fenghuay@nvidia.com>
On Mon, Nov 09, 2026 at 01:29:33PM +0800, Fenghua Yu wrote:
> Before resctrl can expose MB_MAXHLM, the driver must discover
> whether the platform supports HARDLIM read/write and what
> MPAMF_MBW_IDR.MAX_LIM reports. MSCs on the same system may differ;
> inconsistent merge would expose controls on hardware that cannot honour
> them.
>
> Read mbw_max_lim from MPAMF_MBW_IDR when MBW_MAX is present, derive
> mpam_feat_mbw_max_hardlim_rw when soft and hard limiting are both
> supported, merge capability across MSCs, and keep the merged view in
> sync via mpam_props_sync_mbw_max_hardlim_rw().
>
> Signed-off-by: Fenghua Yu <fenghuay@nvidia.com>
> ---
> drivers/resctrl/mpam_devices.c | 40 ++++++++++++++++++++++++++++++++-
> drivers/resctrl/mpam_internal.h | 7 ++++++
> 2 files changed, 46 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/resctrl/mpam_devices.c b/drivers/resctrl/mpam_devices.c
> index cb6096e9d2cf..1e56e8f3858e 100644
> --- a/drivers/resctrl/mpam_devices.c
> +++ b/drivers/resctrl/mpam_devices.c
> @@ -830,6 +830,19 @@ static bool mpam_ris_hw_probe_csu_nrdy(struct mpam_msc_ris *ris)
> return (!can_set || !can_clear);
> }
>
> +/* Align mpam_feat_mbw_max_hardlim_rw with MPAMF_MBW_IDR.MAX_LIM and mbw_max. */
> +static void mpam_props_sync_mbw_max_hardlim_rw(struct mpam_props *props)
> +{
> + if (!mpam_has_feature(mpam_feat_mbw_max, props)) {
> + mpam_clear_feature(mpam_feat_mbw_max_hardlim_rw, props);
> + return;
> + }
> + if (props->mbw_max_lim == 0)
> + mpam_set_feature(mpam_feat_mbw_max_hardlim_rw, props);
> + else
> + mpam_clear_feature(mpam_feat_mbw_max_hardlim_rw, props);
> +}
> +
> static void mpam_ris_hw_probe(struct mpam_msc_ris *ris)
> {
> int err;
> @@ -877,6 +890,8 @@ static void mpam_ris_hw_probe(struct mpam_msc_ris *ris)
> if (FIELD_GET(MPAMF_IDR_HAS_MBW_PART, ris->idr)) {
> u32 mbw_features = mpam_read_partsel_reg(msc, MBW_IDR);
>
> + props->mbw_max_lim = 0;
> +
> /* portion bitmap resolution */
> props->mbw_pbm_bits = FIELD_GET(MPAMF_MBW_IDR_BWPBM_WD, mbw_features);
> if (props->mbw_pbm_bits &&
> @@ -891,14 +906,18 @@ static void mpam_ris_hw_probe(struct mpam_msc_ris *ris)
> */
> props->bwa_wd = min(props->bwa_wd, 16);
>
> - if (props->bwa_wd && FIELD_GET(MPAMF_MBW_IDR_HAS_MAX, mbw_features))
> + if (props->bwa_wd && FIELD_GET(MPAMF_MBW_IDR_HAS_MAX, mbw_features)) {
> mpam_set_feature(mpam_feat_mbw_max, props);
> + props->mbw_max_lim = FIELD_GET(MPAMF_MBW_IDR_MAX_LIM, mbw_features);
> + }
>
> if (props->bwa_wd && FIELD_GET(MPAMF_MBW_IDR_HAS_MIN, mbw_features))
> mpam_set_feature(mpam_feat_mbw_min, props);
>
> if (props->bwa_wd && FIELD_GET(MPAMF_MBW_IDR_HAS_PROP, mbw_features))
> mpam_set_feature(mpam_feat_mbw_prop, props);
> +
> + mpam_props_sync_mbw_max_hardlim_rw(props);
> }
>
> /* Priority partitioning */
> @@ -2252,12 +2271,31 @@ static void __props_mismatch(struct mpam_props *parent,
> if (alias && !mpam_has_bwa_wd_feature(parent) &&
> mpam_has_bwa_wd_feature(child)) {
> parent->bwa_wd = child->bwa_wd;
> + parent->mbw_max_lim = child->mbw_max_lim;
> + if (mpam_has_feature(mpam_feat_mbw_max_hardlim_rw, child))
> + mpam_set_feature(mpam_feat_mbw_max_hardlim_rw, parent);
> + else
> + mpam_clear_feature(mpam_feat_mbw_max_hardlim_rw, parent);
> } else if (MISMATCHED_HELPER(parent, child, mpam_has_bwa_wd_feature,
> bwa_wd, alias)) {
> pr_debug("took the min bwa_wd\n");
> parent->bwa_wd = min(parent->bwa_wd, child->bwa_wd);
> }
>
> + if (CAN_MERGE_FEAT(parent, child, mpam_feat_mbw_max, alias)) {
> + parent->mbw_max_lim = child->mbw_max_lim;
> + if (mpam_has_feature(mpam_feat_mbw_max_hardlim_rw, child))
> + mpam_set_feature(mpam_feat_mbw_max_hardlim_rw, parent);
> + else
> + mpam_clear_feature(mpam_feat_mbw_max_hardlim_rw, parent);
> + } else if (MISMATCHED_FEAT(parent, child, mpam_feat_mbw_max,
> + mbw_max_lim, alias)) {
> + pr_debug("%s mbw_max_lim mismatch, clearing mbw_max\n", __func__);
> + mpam_clear_feature(mpam_feat_mbw_max, parent);
> + parent->mbw_max_lim = 0;
> + mpam_props_sync_mbw_max_hardlim_rw(parent);
Hi Fenghua,
For alias=True, the existing bitmap_or() at the end of __props_mismatch() appears
to undo this rejection by copying the child's feature bits back into parent.
With both inputs advertising MBW_MAX and having matching bwa_wd, a small harness
using the actual merge functions produced:
parent.MAX_LIM child.MAX_LIM resulting mbw_max hardlim_rw
0 1 1 0
1 0 1 1
The resulting mbw_max_lim is 0 in both cases, thus the same pair of capabilities produces
different writable-HARDLIM support depending on merge order, and MBW_MAX remains enabled
despite the mismatch.
Rerunning mpam_props_sync_mbw_max_hardlim_rw() after the OR would not preserve the
rejection, mbw_max has been restored and mbw_max_lim was reset to 0, which means soft+hard
support.
Best regards,
Richard Cheng.
> + }
> +
> if (alias && !mpam_has_cmax_wd_feature(parent) && mpam_has_cmax_wd_feature(child)) {
> parent->cmax_wd = child->cmax_wd;
> } else if (MISMATCHED_HELPER(parent, child, mpam_has_cmax_wd_feature,
> diff --git a/drivers/resctrl/mpam_internal.h b/drivers/resctrl/mpam_internal.h
> index 1c9e0e8b78a9..6be32b2cb0ab 100644
> --- a/drivers/resctrl/mpam_internal.h
> +++ b/drivers/resctrl/mpam_internal.h
> @@ -172,6 +172,7 @@ enum mpam_device_features {
> mpam_feat_mbw_part,
> mpam_feat_mbw_min,
> mpam_feat_mbw_max,
> + mpam_feat_mbw_max_hardlim_rw,
> mpam_feat_mbw_prop,
> mpam_feat_intpri_part,
> mpam_feat_intpri_part_0_low,
> @@ -203,6 +204,11 @@ struct mpam_props {
> u16 dspri_wd;
> u16 num_csu_mon;
> u16 num_mbwu_mon;
> + /*
> + * MPAMF_MBW_IDR.MAX_LIM [1:0] when mpam_feat_mbw_max; else 0.
> + * 0 = soft+hard, 1 = soft only, 2 = hard only, 3 = reserved.
> + */
> + u8 mbw_max_lim;
>
> /*
> * Kunit tests use memset() to set up feature combinations that should be
> @@ -585,6 +591,7 @@ static inline void mpam_resctrl_teardown_class(struct mpam_class *class) { }
>
> /* MPAMF_MBW_IDR - MPAM features memory bandwidth partitioning ID register */
> #define MPAMF_MBW_IDR_BWA_WD GENMASK(5, 0)
> +#define MPAMF_MBW_IDR_MAX_LIM GENMASK(9, 8)
> #define MPAMF_MBW_IDR_HAS_MIN BIT(10)
> #define MPAMF_MBW_IDR_HAS_MAX BIT(11)
> #define MPAMF_MBW_IDR_HAS_PBM BIT(12)
> --
> 2.53.0
>
next prev parent reply other threads:[~2026-11-11 8:59 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-11-09 21:29 [PATCH RFC v1 0/6] arm_mpam,resctrl: expose MPAM MBW_MAX hard limit Fenghua Yu
2026-11-09 21:29 ` [PATCH RFC v1 1/6] resctrl: wire MB_MAXHLM schemata parsing and group setup Fenghua Yu
2026-11-09 21:29 ` [PATCH RFC v1 2/6] arm_mpam: resctrl: probe MPAMF_MBW_IDR MAX_LIM and hardlim_rw Fenghua Yu
2026-11-11 8:59 ` Richard Cheng [this message]
2026-11-09 21:29 ` [PATCH RFC v1 3/6] arm_mpam: resctrl: track MBW max hard-limit in config Fenghua Yu
2026-11-09 21:29 ` [PATCH RFC v1 4/6] arm_mpam: resctrl: add MAXHLM control on the MBA resource Fenghua Yu
2026-11-09 21:29 ` [PATCH RFC v1 5/6] arm_mpam: Add MB_MAXHLM_NODE and Node scope Fenghua Yu
2026-11-09 21:29 ` [PATCH RFC v1 6/6] Documentation: resctrl: document MB_MAXHLM for MPAM MBA Fenghua Yu
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