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From: Artem Bityutskiy <dedekind1@gmail.com>
To: Binbin Wu <binbin.wu@linux.intel.com>,
	"Edgecombe, Rick P"	 <rick.p.edgecombe@intel.com>,
	"kvm@vger.kernel.org" <kvm@vger.kernel.org>,
	 "linux-kernel@vger.kernel.org"	 <linux-kernel@vger.kernel.org>
Cc: "Gao, Chao" <chao.gao@intel.com>,
	"seanjc@google.com" <seanjc@google.com>,
	 "dave.hansen@linux.intel.com"	 <dave.hansen@linux.intel.com>,
	"kas@kernel.org" <kas@kernel.org>,
	"Li, Xiaoyao"	 <xiaoyao.li@intel.com>,
	"pbonzini@redhat.com" <pbonzini@redhat.com>,
	 "andrew.cooper3@citrix.com"	 <andrew.cooper3@citrix.com>,
	"nik.borisov@suse.com" <nik.borisov@suse.com>
Subject: Re: [PATCH v3 0/4] KVM: TDX: Validate directly configurable CPUID bits
Date: Wed, 09 Sep 2026 14:20:21 +0300	[thread overview]
Message-ID: <b227e4b40c45b090eee627e6a4d8f314297996ff.camel@gmail.com> (raw)
In-Reply-To: <473c5507-045f-454c-b6d1-76d2a390f413@linux.intel.com>

On Wed, 2026-09-09 at 16:48 +0800, Binbin Wu wrote:
> > VMX:
> >   VM entry = load guest state from guest-state area
> >   VM exit  = save guest state into guest-state area,
> >              load host state from host-state area
> > 
> > TDX:
> >   SEAMCALL = save host state into SEAM VMCS guest-state area,
> >              load module state from SEAM VMCS host-state area
> >   SEAMRET  = restore host state from SEAM VMCS guest-state area
> > 
> > I may be reading the SDM wrong, let me know.
> 
> That's my understanding too.

Good, thanks for confirming.

> > 
> > So there are differences, and I was hoping to:
> > - Be corrected if I misinterpret the SDM and how things work.
> > - Get comments on whether the proposal took this into account.
> > - Get comments on how this affects, or does not affect, the proposal.
> 
> For host state clobbering behavior, we cares about the values of the host (VMX
> root mode) after SEAMRET.
> 
> When there is a control/field for "load host state from host-state area", I
> think there are two cases: 
> - If there is the corresponding control/field for "load guest state from
>   guest-state area", the TDX module could leverage it.
> - If there is no such corresponding control/field for "load guest state from
>   guest-state area", the TDX module could do it in software way to mimic it.
> 
> So from the view of the VMM, it can have the aligned behavior on host state
> clobbering behavior.

Now I see what you mean: make msr_preservation.pdf follow the same rule
as the VMX host-state restore, and let the TDX module help where HW behaves
differently (call this SW restore vs HW restore via VMCS).

That sounds good to me.

My only doubt is whether it can be guaranteed in every case. A HW restore
happens after a SW restore.

E.g., IA32_DEBUGCTL - HW clears it on VM exit (SDM 30.5.1), so whatever
TDX module puts there on the exit path, will be overwritten. Not that this
is an issue today, just using this as an example.

But I'd guess there would be only few problematic cases (if any).

Then you wrote this:

<cite>
FRED is a useful concrete example.  Under VMX, the FRED host state in
IA32_FRED_CONFIG, IA32_FRED_STKLVLS, IA32_FRED_RSP1-3 and
IA32_FRED_SSP1-3 is covered by the VMCS host-state area, so the TDX module
is expected to restore these MSRs on TDH.VP.ENTER return.  IA32_FRED_RSP0
and IA32_PL0_SSP (a.k.a. IA32_FRED_SSP0) are handled by software, so the
TDX module is expected to clobber them on TDH.VP.ENTER return.
</cite>

That one reads as obviously right to me. If VMX and TDX differed in how
IA32_FRED_RSP0 and IA32_PL0_SSP are handled, that would be a red flag.

Did you go through all the MSRs and check that the VMX and TDX behavior
matches today?

Thanks!

  reply	other threads:[~2026-09-09 11:20 UTC|newest]

Thread overview: 64+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-08-27  3:18 Binbin Wu
2026-08-27  3:18 ` [PATCH v3 1/4] KVM: TDX: Track configurable CPUID bits allowed by KVM Binbin Wu
2026-09-01  6:29   ` Tony Lindgren
2026-09-01  8:23     ` Binbin Wu
2026-09-01  8:27       ` Tony Lindgren
2026-09-01 14:35   ` Xiaoyao Li
2026-09-02  0:33     ` Binbin Wu
2026-09-02 15:09       ` Xiaoyao Li
2026-09-02 16:19         ` Binbin Wu
2026-09-02 16:22           ` Edgecombe, Rick P
2026-09-02 16:25             ` Binbin Wu
2026-09-03  7:28           ` Xiaoyao Li
2026-09-03  8:57             ` Binbin Wu
2026-09-08 21:13             ` Edgecombe, Rick P
2026-09-09 16:39               ` Xiaoyao Li
2026-09-09 22:29                 ` Sean Christopherson
2026-09-09 23:18                   ` Edgecombe, Rick P
2026-09-10  2:39                     ` Binbin Wu
2026-09-10 21:29                       ` Edgecombe, Rick P
2026-09-11  0:55                         ` Binbin Wu
2026-09-11  1:30                           ` Edgecombe, Rick P
2026-09-10  2:53                     ` Xiaoyao Li
2026-09-08 21:15         ` Edgecombe, Rick P
2026-08-27  3:18 ` [PATCH v3 2/4] KVM: TDX: Report CORE_CAPABILITIES as configurable Binbin Wu
2026-09-01  6:45   ` Tony Lindgren
2026-09-02 17:43   ` Kishen Maloor
2026-09-03  2:22     ` Binbin Wu
2026-09-03  6:10       ` Kishen Maloor
2026-09-03  8:12         ` Binbin Wu
2026-08-27  3:18 ` [PATCH v3 3/4] KVM: TDX: Filter configurable CPUID bits Binbin Wu
2026-09-01  6:44   ` Tony Lindgren
2026-09-01  8:42     ` Binbin Wu
2026-09-01  9:09       ` Tony Lindgren
2026-09-03  8:04   ` Xiaoyao Li
2026-09-03  8:23     ` Binbin Wu
2026-08-27  3:18 ` [PATCH v3 4/4] KVM: TDX: Validate userspace CPUID input for KVM_TDX_INIT_VM Binbin Wu
2026-09-01  6:47   ` Tony Lindgren
2026-08-27 19:33 ` [PATCH v3 0/4] KVM: TDX: Validate directly configurable CPUID bits Edgecombe, Rick P
2026-08-28  3:19   ` Binbin Wu
2026-08-28 16:58     ` Edgecombe, Rick P
2026-08-31  5:01       ` Binbin Wu
2026-09-01  9:42         ` Xiaoyao Li
2026-09-01 10:21           ` Xiaoyao Li
2026-09-02 16:09           ` Edgecombe, Rick P
2026-09-02 16:21             ` Binbin Wu
2026-09-09  1:46             ` Binbin Wu
2026-09-01  9:38     ` Xiaoyao Li
2026-09-01 17:41       ` Edgecombe, Rick P
2026-09-02 10:29         ` Xiaoyao Li
2026-09-02 13:13           ` Edgecombe, Rick P
2026-09-02 13:39             ` Xiaoyao Li
2026-09-02 13:53               ` Edgecombe, Rick P
2026-09-02 14:21                 ` Xiaoyao Li
2026-09-02 16:26             ` Binbin Wu
2026-09-08  9:42 ` Artem Bityutskiy
2026-09-09  0:04   ` Binbin Wu
2026-09-08 20:30 ` Artem Bityutskiy
2026-09-08 22:31   ` Edgecombe, Rick P
2026-09-09  6:52     ` Artem Bityutskiy
2026-09-09  8:48       ` Binbin Wu
2026-09-09 11:20         ` Artem Bityutskiy [this message]
2026-09-10  2:54           ` Binbin Wu
2026-09-08 23:54   ` Binbin Wu
2026-09-09  5:37     ` Binbin Wu

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