* [PATCH 1/4] arm64: dts: qcom: hamoa: Add CoreSight nodes for APSS debug block
2026-09-22 10:35 [PATCH 0/4] Add ETM devices for multiple QCOM platforms Jie Gan
@ 2026-09-22 10:35 ` Jie Gan
2026-10-13 12:46 ` Konrad Dybcio
2026-09-22 10:35 ` [PATCH 2/4] arm64: dts: qcom: sm8750: " Jie Gan
` (2 subsequent siblings)
3 siblings, 1 reply; 9+ messages in thread
From: Jie Gan @ 2026-09-22 10:35 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Abel Vesa, Rob Herring,
Krzysztof Kozlowski, Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel, Jie Gan
The APSS debug block is built with CoreSight devices like ETM,
replicator, funnel and TMC ETF. Add dt nodes for these devices to enable
ETM trace.
The replicator, funnel and TMC ETF nodes in this block are physically
powered by the CPU cluster power rail rather than by a dedicated always-on
rail. Add a power-domains property referencing the corresponding
cluster_pdN domain to each of these nodes, so their power state is
tied to the CPU cluster domain and the runtime PM core can power the
domain on before the devices are accessed and let it be powered off
otherwise.
Signed-off-by: Jie Gan <jie.gan@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/hamoa.dtsi | 884 ++++++++++++++++++++++++++++++++++++
arch/arm64/boot/dts/qcom/purwa.dtsi | 12 +
2 files changed, 896 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/hamoa.dtsi b/arch/arm64/boot/dts/qcom/hamoa.dtsi
index 4e35254cdd11..370b6bba2594 100644
--- a/arch/arm64/boot/dts/qcom/hamoa.dtsi
+++ b/arch/arm64/boot/dts/qcom/hamoa.dtsi
@@ -326,6 +326,210 @@ eud_in: endpoint {
};
};
+ etm-0 {
+ compatible = "arm,coresight-etm4x-sysreg";
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+ cpu = <&cpu0>;
+ qcom,skip-power-up;
+
+ out-ports {
+ port {
+ etm0_out: endpoint {
+ remote-endpoint = <&ncc0_0_rep_in>;
+ };
+ };
+ };
+ };
+
+ etm-1 {
+ compatible = "arm,coresight-etm4x-sysreg";
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+ cpu = <&cpu1>;
+ qcom,skip-power-up;
+
+ out-ports {
+ port {
+ etm1_out: endpoint {
+ remote-endpoint = <&ncc0_1_rep_in>;
+ };
+ };
+ };
+ };
+
+ etm-2 {
+ compatible = "arm,coresight-etm4x-sysreg";
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+ cpu = <&cpu2>;
+ qcom,skip-power-up;
+
+ out-ports {
+ port {
+ etm2_out: endpoint {
+ remote-endpoint = <&ncc0_2_rep_in>;
+ };
+ };
+ };
+ };
+
+ etm-3 {
+ compatible = "arm,coresight-etm4x-sysreg";
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+ cpu = <&cpu3>;
+ qcom,skip-power-up;
+
+ out-ports {
+ port {
+ etm3_out: endpoint {
+ remote-endpoint = <&ncc0_3_rep_in>;
+ };
+ };
+ };
+ };
+
+ etm-4 {
+ compatible = "arm,coresight-etm4x-sysreg";
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+ cpu = <&cpu4>;
+ qcom,skip-power-up;
+
+ out-ports {
+ port {
+ etm4_out: endpoint {
+ remote-endpoint = <&ncc1_0_rep_in>;
+ };
+ };
+ };
+ };
+
+ etm-5 {
+ compatible = "arm,coresight-etm4x-sysreg";
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+ cpu = <&cpu5>;
+ qcom,skip-power-up;
+
+ out-ports {
+ port {
+ etm5_out: endpoint {
+ remote-endpoint = <&ncc1_1_rep_in>;
+ };
+ };
+ };
+ };
+
+ etm-6 {
+ compatible = "arm,coresight-etm4x-sysreg";
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+ cpu = <&cpu6>;
+ qcom,skip-power-up;
+
+ out-ports {
+ port {
+ etm6_out: endpoint {
+ remote-endpoint = <&ncc1_2_rep_in>;
+ };
+ };
+ };
+ };
+
+ etm-7 {
+ compatible = "arm,coresight-etm4x-sysreg";
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+ cpu = <&cpu7>;
+ qcom,skip-power-up;
+
+ out-ports {
+ port {
+ etm7_out: endpoint {
+ remote-endpoint = <&ncc1_3_rep_in>;
+ };
+ };
+ };
+ };
+
+ etm8: etm-8 {
+ compatible = "arm,coresight-etm4x-sysreg";
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+ cpu = <&cpu8>;
+ qcom,skip-power-up;
+
+ out-ports {
+ port {
+ etm8_out: endpoint {
+ remote-endpoint = <&ncc2_0_rep_in>;
+ };
+ };
+ };
+ };
+
+ etm9: etm-9 {
+ compatible = "arm,coresight-etm4x-sysreg";
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+ cpu = <&cpu9>;
+ qcom,skip-power-up;
+
+ out-ports {
+ port {
+ etm9_out: endpoint {
+ remote-endpoint = <&ncc2_1_rep_in>;
+ };
+ };
+ };
+ };
+
+ etm10: etm-10 {
+ compatible = "arm,coresight-etm4x-sysreg";
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+ cpu = <&cpu10>;
+ qcom,skip-power-up;
+
+ out-ports {
+ port {
+ etm10_out: endpoint {
+ remote-endpoint = <&ncc2_2_rep_in>;
+ };
+ };
+ };
+ };
+
+ etm11: etm-11 {
+ compatible = "arm,coresight-etm4x-sysreg";
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+ cpu = <&cpu11>;
+ qcom,skip-power-up;
+
+ out-ports {
+ port {
+ etm11_out: endpoint {
+ remote-endpoint = <&ncc2_3_rep_in>;
+ };
+ };
+ };
+ };
+
firmware {
scm: scm {
compatible = "qcom,scm-x1e80100", "qcom,scm";
@@ -6986,6 +7190,14 @@ funnel1_in2: endpoint {
};
};
+ port@4 {
+ reg = <4>;
+
+ funnel1_in4: endpoint {
+ remote-endpoint = <&apss_funnel_out>;
+ };
+ };
+
port@5 {
reg = <5>;
@@ -8433,6 +8645,678 @@ ddr_funnel1_out: endpoint {
};
};
+ funnel@12080000 {
+ compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
+ reg = <0x0 0x12080000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ in-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ apss_funnel_in0: endpoint {
+ remote-endpoint = <&ncc0_etf_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ apss_funnel_in1: endpoint {
+ remote-endpoint = <&ncc1_etf_out>;
+ };
+ };
+
+ port@2 {
+ reg = <2>;
+
+ apss_funnel_in2: endpoint {
+ remote-endpoint = <&ncc2_etf_out>;
+ };
+ };
+ };
+
+ out-ports {
+ port {
+ apss_funnel_out: endpoint {
+ remote-endpoint = <&funnel1_in4>;
+ };
+ };
+ };
+ };
+
+ funnel@13401000 {
+ compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
+ reg = <0x0 0x13401000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+ power-domains = <&cluster_pd0>;
+
+ in-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@2 {
+ reg = <2>;
+
+ ncc0_2_funnel_in2: endpoint {
+ remote-endpoint = <&ncc0_1_funnel_out>;
+ };
+ };
+ };
+
+ out-ports {
+ port {
+ ncc0_2_funnel_out: endpoint {
+ remote-endpoint = <&ncc0_etf_in>;
+ };
+ };
+ };
+ };
+
+ tmc@13409000 {
+ compatible = "arm,coresight-tmc", "arm,primecell";
+ reg = <0x0 0x13409000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+ power-domains = <&cluster_pd0>;
+
+ in-ports {
+ port {
+ ncc0_etf_in: endpoint {
+ remote-endpoint = <&ncc0_2_funnel_out>;
+ };
+ };
+ };
+
+ out-ports {
+ port {
+ ncc0_etf_out: endpoint {
+ remote-endpoint = <&apss_funnel_in0>;
+ };
+ };
+ };
+ };
+
+ replicator@13490000 {
+ compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
+ reg = <0x0 0x13490000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+ power-domains = <&cluster_pd0>;
+
+ in-ports {
+ port {
+ ncc0_0_rep_in: endpoint {
+ remote-endpoint = <&etm0_out>;
+ };
+ };
+ };
+
+ out-ports {
+ port {
+ ncc0_0_rep_out: endpoint {
+ remote-endpoint = <&ncc0_1_funnel_in0>;
+ };
+ };
+ };
+ };
+
+ replicator@134a0000 {
+ compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
+ reg = <0x0 0x134a0000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+ power-domains = <&cluster_pd0>;
+
+ in-ports {
+ port {
+ ncc0_1_rep_in: endpoint {
+ remote-endpoint = <&etm1_out>;
+ };
+ };
+ };
+
+ out-ports {
+ port {
+ ncc0_1_rep_out: endpoint {
+ remote-endpoint = <&ncc0_1_funnel_in1>;
+ };
+ };
+ };
+ };
+
+ replicator@134b0000 {
+ compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
+ reg = <0x0 0x134b0000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+ power-domains = <&cluster_pd0>;
+
+ in-ports {
+ port {
+ ncc0_2_rep_in: endpoint {
+ remote-endpoint = <&etm2_out>;
+ };
+ };
+ };
+
+ out-ports {
+ port {
+ ncc0_2_rep_out: endpoint {
+ remote-endpoint = <&ncc0_1_funnel_in2>;
+ };
+ };
+ };
+ };
+
+ replicator@134c0000 {
+ compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
+ reg = <0x0 0x134c0000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+ power-domains = <&cluster_pd0>;
+
+ in-ports {
+ port {
+ ncc0_3_rep_in: endpoint {
+ remote-endpoint = <&etm3_out>;
+ };
+ };
+ };
+
+ out-ports {
+ port {
+ ncc0_3_rep_out: endpoint {
+ remote-endpoint = <&ncc0_1_funnel_in3>;
+ };
+ };
+ };
+ };
+
+ funnel@134d0000 {
+ compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
+ reg = <0x0 0x134d0000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+ power-domains = <&cluster_pd0>;
+
+ in-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ ncc0_1_funnel_in0: endpoint {
+ remote-endpoint = <&ncc0_0_rep_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ ncc0_1_funnel_in1: endpoint {
+ remote-endpoint = <&ncc0_1_rep_out>;
+ };
+ };
+
+ port@2 {
+ reg = <2>;
+
+ ncc0_1_funnel_in2: endpoint {
+ remote-endpoint = <&ncc0_2_rep_out>;
+ };
+ };
+
+ port@3 {
+ reg = <3>;
+
+ ncc0_1_funnel_in3: endpoint {
+ remote-endpoint = <&ncc0_3_rep_out>;
+ };
+ };
+ };
+
+ out-ports {
+ port {
+ ncc0_1_funnel_out: endpoint {
+ remote-endpoint = <&ncc0_2_funnel_in2>;
+ };
+ };
+ };
+ };
+
+ funnel@13901000 {
+ compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
+ reg = <0x0 0x13901000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+ power-domains = <&cluster_pd1>;
+
+ in-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@2 {
+ reg = <2>;
+
+ ncc1_2_funnel_in2: endpoint {
+ remote-endpoint = <&ncc1_1_funnel_out>;
+ };
+ };
+ };
+
+ out-ports {
+ port {
+ ncc1_2_funnel_out: endpoint {
+ remote-endpoint = <&ncc1_etf_in>;
+ };
+ };
+ };
+ };
+
+ tmc@13909000 {
+ compatible = "arm,coresight-tmc", "arm,primecell";
+ reg = <0x0 0x13909000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+ power-domains = <&cluster_pd1>;
+
+ in-ports {
+ port {
+ ncc1_etf_in: endpoint {
+ remote-endpoint = <&ncc1_2_funnel_out>;
+ };
+ };
+ };
+
+ out-ports {
+ port {
+ ncc1_etf_out: endpoint {
+ remote-endpoint = <&apss_funnel_in1>;
+ };
+ };
+ };
+ };
+
+ replicator@13990000 {
+ compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
+ reg = <0x0 0x13990000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+ power-domains = <&cluster_pd1>;
+
+ in-ports {
+ port {
+ ncc1_0_rep_in: endpoint {
+ remote-endpoint = <&etm4_out>;
+ };
+ };
+ };
+
+ out-ports {
+ port {
+ ncc1_0_rep_out: endpoint {
+ remote-endpoint = <&ncc1_1_funnel_in0>;
+ };
+ };
+ };
+ };
+
+ replicator@139a0000 {
+ compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
+ reg = <0x0 0x139a0000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+ power-domains = <&cluster_pd1>;
+
+ in-ports {
+ port {
+ ncc1_1_rep_in: endpoint {
+ remote-endpoint = <&etm5_out>;
+ };
+ };
+ };
+
+ out-ports {
+ port {
+ ncc1_1_rep_out: endpoint {
+ remote-endpoint = <&ncc1_1_funnel_in1>;
+ };
+ };
+ };
+ };
+
+ replicator@139b0000 {
+ compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
+ reg = <0x0 0x139b0000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+ power-domains = <&cluster_pd1>;
+
+ in-ports {
+ port {
+ ncc1_2_rep_in: endpoint {
+ remote-endpoint = <&etm6_out>;
+ };
+ };
+ };
+
+ out-ports {
+ port {
+ ncc1_2_rep_out: endpoint {
+ remote-endpoint = <&ncc1_1_funnel_in2>;
+ };
+ };
+ };
+ };
+
+ replicator@139c0000 {
+ compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
+ reg = <0x0 0x139c0000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+ power-domains = <&cluster_pd1>;
+
+ in-ports {
+ port {
+ ncc1_3_rep_in: endpoint {
+ remote-endpoint = <&etm7_out>;
+ };
+ };
+ };
+
+ out-ports {
+ port {
+ ncc1_3_rep_out: endpoint {
+ remote-endpoint = <&ncc1_1_funnel_in3>;
+ };
+ };
+ };
+ };
+
+ funnel@139d0000 {
+ compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
+ reg = <0x0 0x139d0000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+ power-domains = <&cluster_pd1>;
+
+ in-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ ncc1_1_funnel_in0: endpoint {
+ remote-endpoint = <&ncc1_0_rep_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ ncc1_1_funnel_in1: endpoint {
+ remote-endpoint = <&ncc1_1_rep_out>;
+ };
+ };
+
+ port@2 {
+ reg = <2>;
+
+ ncc1_1_funnel_in2: endpoint {
+ remote-endpoint = <&ncc1_2_rep_out>;
+ };
+ };
+
+ port@3 {
+ reg = <3>;
+
+ ncc1_1_funnel_in3: endpoint {
+ remote-endpoint = <&ncc1_3_rep_out>;
+ };
+ };
+ };
+
+ out-ports {
+ port {
+ ncc1_1_funnel_out: endpoint {
+ remote-endpoint = <&ncc1_2_funnel_in2>;
+ };
+ };
+ };
+ };
+
+ cluster2_funnel_l2: funnel@13e01000 {
+ compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
+ reg = <0x0 0x13e01000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+ power-domains = <&cluster_pd2>;
+
+ in-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@2 {
+ reg = <2>;
+
+ ncc2_2_funnel_in2: endpoint {
+ remote-endpoint = <&ncc2_1_funnel_out>;
+ };
+ };
+ };
+
+ out-ports {
+ port {
+ ncc2_2_funnel_out: endpoint {
+ remote-endpoint = <&ncc2_etf_in>;
+ };
+ };
+ };
+ };
+
+ cluster2_etf: tmc@13e09000 {
+ compatible = "arm,coresight-tmc", "arm,primecell";
+ reg = <0x0 0x13e09000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+ power-domains = <&cluster_pd2>;
+
+ in-ports {
+ port {
+ ncc2_etf_in: endpoint {
+ remote-endpoint = <&ncc2_2_funnel_out>;
+ };
+ };
+ };
+
+ out-ports {
+ port {
+ ncc2_etf_out: endpoint {
+ remote-endpoint = <&apss_funnel_in2>;
+ };
+ };
+ };
+ };
+
+ cluster2_rep_2_0: replicator@13e90000 {
+ compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
+ reg = <0x0 0x13e90000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+ power-domains = <&cluster_pd2>;
+
+ in-ports {
+ port {
+ ncc2_0_rep_in: endpoint {
+ remote-endpoint = <&etm8_out>;
+ };
+ };
+ };
+
+ out-ports {
+ port {
+ ncc2_0_rep_out: endpoint {
+ remote-endpoint = <&ncc2_1_funnel_in0>;
+ };
+ };
+ };
+ };
+
+ cluster2_rep_2_1: replicator@13ea0000 {
+ compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
+ reg = <0x0 0x13ea0000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+ power-domains = <&cluster_pd2>;
+
+ in-ports {
+ port {
+ ncc2_1_rep_in: endpoint {
+ remote-endpoint = <&etm9_out>;
+ };
+ };
+ };
+
+ out-ports {
+ port {
+ ncc2_1_rep_out: endpoint {
+ remote-endpoint = <&ncc2_1_funnel_in1>;
+ };
+ };
+ };
+ };
+
+ cluster2_rep_2_2: replicator@13eb0000 {
+ compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
+ reg = <0x0 0x13eb0000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+ power-domains = <&cluster_pd2>;
+
+ in-ports {
+ port {
+ ncc2_2_rep_in: endpoint {
+ remote-endpoint = <&etm10_out>;
+ };
+ };
+ };
+
+ out-ports {
+ port {
+ ncc2_2_rep_out: endpoint {
+ remote-endpoint = <&ncc2_1_funnel_in2>;
+ };
+ };
+ };
+ };
+
+ cluster2_rep_2_3: replicator@13ec0000 {
+ compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
+ reg = <0x0 0x13ec0000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+ power-domains = <&cluster_pd2>;
+
+ in-ports {
+ port {
+ ncc2_3_rep_in: endpoint {
+ remote-endpoint = <&etm11_out>;
+ };
+ };
+ };
+
+ out-ports {
+ port {
+ ncc2_3_rep_out: endpoint {
+ remote-endpoint = <&ncc2_1_funnel_in3>;
+ };
+ };
+ };
+ };
+
+ cluster2_funnel_l1: funnel@13ed0000 {
+ compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
+ reg = <0x0 0x13ed0000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+ power-domains = <&cluster_pd2>;
+
+ in-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ ncc2_1_funnel_in0: endpoint {
+ remote-endpoint = <&ncc2_0_rep_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ ncc2_1_funnel_in1: endpoint {
+ remote-endpoint = <&ncc2_1_rep_out>;
+ };
+ };
+
+ port@2 {
+ reg = <2>;
+
+ ncc2_1_funnel_in2: endpoint {
+ remote-endpoint = <&ncc2_2_rep_out>;
+ };
+ };
+
+ port@3 {
+ reg = <3>;
+
+ ncc2_1_funnel_in3: endpoint {
+ remote-endpoint = <&ncc2_3_rep_out>;
+ };
+ };
+ };
+
+ out-ports {
+ port {
+ ncc2_1_funnel_out: endpoint {
+ remote-endpoint = <&ncc2_2_funnel_in2>;
+ };
+ };
+ };
+ };
+
apps_smmu: iommu@15000000 {
compatible = "qcom,x1e80100-smmu-500", "qcom,smmu-500", "arm,mmu-500";
reg = <0 0x15000000 0 0x100000>;
diff --git a/arch/arm64/boot/dts/qcom/purwa.dtsi b/arch/arm64/boot/dts/qcom/purwa.dtsi
index 4348dd3d1dc5..90069c8e1d40 100644
--- a/arch/arm64/boot/dts/qcom/purwa.dtsi
+++ b/arch/arm64/boot/dts/qcom/purwa.dtsi
@@ -8,7 +8,15 @@
#include <dt-bindings/clock/qcom,x1p42100-videocc.h>
+/delete-node/ &apss_funnel_in2;
/delete-node/ &bwmon_cluster0;
+/delete-node/ &cluster2_etf;
+/delete-node/ &cluster2_funnel_l1;
+/delete-node/ &cluster2_funnel_l2;
+/delete-node/ &cluster2_rep_2_0;
+/delete-node/ &cluster2_rep_2_1;
+/delete-node/ &cluster2_rep_2_2;
+/delete-node/ &cluster2_rep_2_3;
/delete-node/ &cluster_pd2;
/delete-node/ &cpu_map_cluster2;
/delete-node/ &cpu8;
@@ -19,6 +27,10 @@
/delete-node/ &cpu_pd9;
/delete-node/ &cpu_pd10;
/delete-node/ &cpu_pd11;
+/delete-node/ &etm8;
+/delete-node/ &etm9;
+/delete-node/ &etm10;
+/delete-node/ &etm11;
/delete-node/ &gpu_opp_table;
/delete-node/ &gpu_speed_bin;
/delete-node/ &iris_opp_table;
--
2.34.1
^ permalink raw reply [flat|nested] 9+ messages in thread* Re: [PATCH 1/4] arm64: dts: qcom: hamoa: Add CoreSight nodes for APSS debug block
2026-09-22 10:35 ` [PATCH 1/4] arm64: dts: qcom: hamoa: Add CoreSight nodes for APSS debug block Jie Gan
@ 2026-10-13 12:46 ` Konrad Dybcio
2026-10-14 1:13 ` Jie Gan
0 siblings, 1 reply; 9+ messages in thread
From: Konrad Dybcio @ 2026-10-13 12:46 UTC (permalink / raw)
To: Jie Gan, Bjorn Andersson, Konrad Dybcio, Abel Vesa, Rob Herring,
Krzysztof Kozlowski, Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel
On 9/22/26 12:35 PM, Jie Gan wrote:
> The APSS debug block is built with CoreSight devices like ETM,
> replicator, funnel and TMC ETF. Add dt nodes for these devices to enable
> ETM trace.
>
> The replicator, funnel and TMC ETF nodes in this block are physically
> powered by the CPU cluster power rail rather than by a dedicated always-on
> rail. Add a power-domains property referencing the corresponding
> cluster_pdN domain to each of these nodes, so their power state is
> tied to the CPU cluster domain and the runtime PM core can power the
> domain on before the devices are accessed and let it be powered off
> otherwise.
>
> Signed-off-by: Jie Gan <jie.gan@oss.qualcomm.com>
> ---
[...]
> + funnel@12080000 {
> + compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
> + reg = <0x0 0x12080000 0x0 0x1000>;
> +
> + clocks = <&aoss_qmp>;
> + clock-names = "apb_pclk";
> +
> + in-ports {
No need for power-domains here? (also same question for the other
platforms)
Konrad
^ permalink raw reply [flat|nested] 9+ messages in thread* Re: [PATCH 1/4] arm64: dts: qcom: hamoa: Add CoreSight nodes for APSS debug block
2026-10-13 12:46 ` Konrad Dybcio
@ 2026-10-14 1:13 ` Jie Gan
0 siblings, 0 replies; 9+ messages in thread
From: Jie Gan @ 2026-10-14 1:13 UTC (permalink / raw)
To: Konrad Dybcio, Bjorn Andersson, Konrad Dybcio, Abel Vesa,
Rob Herring, Krzysztof Kozlowski, Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel
On 10/13/2026 8:46 PM, Konrad Dybcio wrote:
> On 9/22/26 12:35 PM, Jie Gan wrote:
>> The APSS debug block is built with CoreSight devices like ETM,
>> replicator, funnel and TMC ETF. Add dt nodes for these devices to enable
>> ETM trace.
>>
>> The replicator, funnel and TMC ETF nodes in this block are physically
>> powered by the CPU cluster power rail rather than by a dedicated always-on
>> rail. Add a power-domains property referencing the corresponding
>> cluster_pdN domain to each of these nodes, so their power state is
>> tied to the CPU cluster domain and the runtime PM core can power the
>> domain on before the devices are accessed and let it be powered off
>> otherwise.
>>
>> Signed-off-by: Jie Gan <jie.gan@oss.qualcomm.com>
>> ---
>
> [...]
>
>> + funnel@12080000 {
>> + compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
>> + reg = <0x0 0x12080000 0x0 0x1000>;
>> +
>> + clocks = <&aoss_qmp>;
>> + clock-names = "apb_pclk";
>> +
>> + in-ports {
>
> No need for power-domains here? (also same question for the other
> platforms)
The power-domain only adds to the devices within the cluster. This
funnel device doesnt sit in the CPU clusters.
Thanks,
Jie
>
> Konrad
^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH 2/4] arm64: dts: qcom: sm8750: Add CoreSight nodes for APSS debug block
2026-09-22 10:35 [PATCH 0/4] Add ETM devices for multiple QCOM platforms Jie Gan
2026-09-22 10:35 ` [PATCH 1/4] arm64: dts: qcom: hamoa: Add CoreSight nodes for APSS debug block Jie Gan
@ 2026-09-22 10:35 ` Jie Gan
2026-09-22 10:35 ` [PATCH 3/4] arm64: dts: qcom: kaanapali: " Jie Gan
2026-09-22 10:35 ` [PATCH 4/4] arm64: dts: qcom: glymur: " Jie Gan
3 siblings, 0 replies; 9+ messages in thread
From: Jie Gan @ 2026-09-22 10:35 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Abel Vesa, Rob Herring,
Krzysztof Kozlowski, Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel, Jie Gan
The APSS debug block is built with CoreSight devices like ETM,
replicator, funnel and TMC ETF. Add dt nodes for these devices to enable
ETM trace.
The replicator, funnel and TMC ETF nodes in this block are physically
powered by the CPU cluster power rail rather than by a dedicated always-on
rail. Add a power-domains property referencing the corresponding
cluster0_pd/cluster1_pd domain to each of these nodes, so their power
state is tied to the CPU cluster domain and the runtime PM core can
power the domain on before the devices are accessed and let it be
powered off otherwise.
Signed-off-by: Jie Gan <jie.gan@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/sm8750.dtsi | 599 +++++++++++++++++++++++++++++++++++
1 file changed, 599 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sm8750.dtsi b/arch/arm64/boot/dts/qcom/sm8750.dtsi
index 28cf22da854d..c8059c275606 100644
--- a/arch/arm64/boot/dts/qcom/sm8750.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8750.dtsi
@@ -216,6 +216,142 @@ domain_ss3: domain-sleep-0 {
};
};
+ etm-0 {
+ compatible = "arm,coresight-etm4x-sysreg";
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+ cpu = <&cpu0>;
+ qcom,skip-power-up;
+
+ out-ports {
+ port {
+ etm0_out: endpoint {
+ remote-endpoint = <&ncc0_0_rep_in>;
+ };
+ };
+ };
+ };
+
+ etm-1 {
+ compatible = "arm,coresight-etm4x-sysreg";
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+ cpu = <&cpu1>;
+ qcom,skip-power-up;
+
+ out-ports {
+ port {
+ etm1_out: endpoint {
+ remote-endpoint = <&ncc0_1_rep_in>;
+ };
+ };
+ };
+ };
+
+ etm-2 {
+ compatible = "arm,coresight-etm4x-sysreg";
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+ cpu = <&cpu2>;
+ qcom,skip-power-up;
+
+ out-ports {
+ port {
+ etm2_out: endpoint {
+ remote-endpoint = <&ncc0_2_rep_in>;
+ };
+ };
+ };
+ };
+
+ etm-3 {
+ compatible = "arm,coresight-etm4x-sysreg";
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+ cpu = <&cpu3>;
+ qcom,skip-power-up;
+
+ out-ports {
+ port {
+ etm3_out: endpoint {
+ remote-endpoint = <&ncc0_3_rep_in>;
+ };
+ };
+ };
+ };
+
+ etm-4 {
+ compatible = "arm,coresight-etm4x-sysreg";
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+ cpu = <&cpu4>;
+ qcom,skip-power-up;
+
+ out-ports {
+ port {
+ etm4_out: endpoint {
+ remote-endpoint = <&ncc0_4_rep_in>;
+ };
+ };
+ };
+ };
+
+ etm-5 {
+ compatible = "arm,coresight-etm4x-sysreg";
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+ cpu = <&cpu5>;
+ qcom,skip-power-up;
+
+ out-ports {
+ port {
+ etm5_out: endpoint {
+ remote-endpoint = <&ncc0_5_rep_in>;
+ };
+ };
+ };
+ };
+
+ etm-6 {
+ compatible = "arm,coresight-etm4x-sysreg";
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+ cpu = <&cpu6>;
+ qcom,skip-power-up;
+
+ out-ports {
+ port {
+ etm6_out: endpoint {
+ remote-endpoint = <&ncc1_0_rep_in>;
+ };
+ };
+ };
+ };
+
+ etm-7 {
+ compatible = "arm,coresight-etm4x-sysreg";
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+ cpu = <&cpu7>;
+ qcom,skip-power-up;
+
+ out-ports {
+ port {
+ etm7_out: endpoint {
+ remote-endpoint = <&ncc1_1_rep_in>;
+ };
+ };
+ };
+ };
+
firmware {
scm: scm {
compatible = "qcom,scm-sm8750", "qcom,scm";
@@ -5072,6 +5208,14 @@ tn_ag_in32: endpoint {
remote-endpoint = <&tpdm_rdpm_cmb2_out>;
};
};
+
+ port@21 {
+ reg = <0x21>;
+
+ tn_ag_in33: endpoint {
+ remote-endpoint = <&apss_funnel_out>;
+ };
+ };
};
out-ports {
@@ -5349,6 +5493,461 @@ tpdm_swao_out: endpoint {
};
};
+ funnel@12080000 {
+ compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
+ reg = <0x0 0x12080000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ in-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ apss_funnel_in0: endpoint {
+ remote-endpoint = <&ncc0_etf_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ apss_funnel_in1: endpoint {
+ remote-endpoint = <&ncc1_etf_out>;
+ };
+ };
+ };
+
+ out-ports {
+ port {
+ apss_funnel_out: endpoint {
+ remote-endpoint = <&tn_ag_in33>;
+ };
+ };
+ };
+ };
+
+ funnel@13401000 {
+ compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
+ reg = <0x0 0x13401000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+ power-domains = <&cluster0_pd>;
+
+ in-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@2 {
+ reg = <2>;
+
+ ncc0_2_funnel_in2: endpoint {
+ remote-endpoint = <&ncc0_1_funnel_out>;
+ };
+ };
+ };
+
+ out-ports {
+ port {
+ ncc0_2_funnel_out: endpoint {
+ remote-endpoint = <&ncc0_etf_in>;
+ };
+ };
+ };
+ };
+
+ tmc@13409000 {
+ compatible = "arm,coresight-tmc", "arm,primecell";
+ reg = <0x0 0x13409000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+ power-domains = <&cluster0_pd>;
+
+ in-ports {
+ port {
+ ncc0_etf_in: endpoint {
+ remote-endpoint = <&ncc0_2_funnel_out>;
+ };
+ };
+ };
+
+ out-ports {
+ port {
+ ncc0_etf_out: endpoint {
+ remote-endpoint = <&apss_funnel_in0>;
+ };
+ };
+ };
+ };
+
+ funnel@13481000 {
+ compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
+ reg = <0x0 0x13481000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+ power-domains = <&cluster0_pd>;
+
+ in-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ ncc0_1_funnel_in0: endpoint {
+ remote-endpoint = <&ncc0_0_rep_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ ncc0_1_funnel_in1: endpoint {
+ remote-endpoint = <&ncc0_1_rep_out>;
+ };
+ };
+
+ port@2 {
+ reg = <2>;
+
+ ncc0_1_funnel_in2: endpoint {
+ remote-endpoint = <&ncc0_2_rep_out>;
+ };
+ };
+
+ port@3 {
+ reg = <3>;
+
+ ncc0_1_funnel_in3: endpoint {
+ remote-endpoint = <&ncc0_3_rep_out>;
+ };
+ };
+
+ port@4 {
+ reg = <4>;
+
+ ncc0_1_funnel_in4: endpoint {
+ remote-endpoint = <&ncc0_4_rep_out>;
+ };
+ };
+
+ port@5 {
+ reg = <5>;
+
+ ncc0_1_funnel_in5: endpoint {
+ remote-endpoint = <&ncc0_5_rep_out>;
+ };
+ };
+ };
+
+ out-ports {
+ port {
+ ncc0_1_funnel_out: endpoint {
+ remote-endpoint = <&ncc0_2_funnel_in2>;
+ };
+ };
+ };
+ };
+
+ replicator@13490000 {
+ compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
+ reg = <0x0 0x13490000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+ power-domains = <&cluster0_pd>;
+
+ in-ports {
+ port {
+ ncc0_0_rep_in: endpoint {
+ remote-endpoint = <&etm0_out>;
+ };
+ };
+ };
+
+ out-ports {
+ port {
+ ncc0_0_rep_out: endpoint {
+ remote-endpoint = <&ncc0_1_funnel_in0>;
+ };
+ };
+ };
+ };
+
+ replicator@134a0000 {
+ compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
+ reg = <0x0 0x134a0000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+ power-domains = <&cluster0_pd>;
+
+ in-ports {
+ port {
+ ncc0_1_rep_in: endpoint {
+ remote-endpoint = <&etm1_out>;
+ };
+ };
+ };
+
+ out-ports {
+ port {
+ ncc0_1_rep_out: endpoint {
+ remote-endpoint = <&ncc0_1_funnel_in1>;
+ };
+ };
+ };
+ };
+
+ replicator@134b0000 {
+ compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
+ reg = <0x0 0x134b0000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+ power-domains = <&cluster0_pd>;
+
+ in-ports {
+ port {
+ ncc0_2_rep_in: endpoint {
+ remote-endpoint = <&etm2_out>;
+ };
+ };
+ };
+
+ out-ports {
+ port {
+ ncc0_2_rep_out: endpoint {
+ remote-endpoint = <&ncc0_1_funnel_in2>;
+ };
+ };
+ };
+ };
+
+ replicator@134c0000 {
+ compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
+ reg = <0x0 0x134c0000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+ power-domains = <&cluster0_pd>;
+
+ in-ports {
+ port {
+ ncc0_3_rep_in: endpoint {
+ remote-endpoint = <&etm3_out>;
+ };
+ };
+ };
+
+ out-ports {
+ port {
+ ncc0_3_rep_out: endpoint {
+ remote-endpoint = <&ncc0_1_funnel_in3>;
+ };
+ };
+ };
+ };
+
+ replicator@134d0000 {
+ compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
+ reg = <0x0 0x134d0000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+ power-domains = <&cluster0_pd>;
+
+ in-ports {
+ port {
+ ncc0_4_rep_in: endpoint {
+ remote-endpoint = <&etm4_out>;
+ };
+ };
+ };
+
+ out-ports {
+ port {
+ ncc0_4_rep_out: endpoint {
+ remote-endpoint = <&ncc0_1_funnel_in4>;
+ };
+ };
+ };
+ };
+
+ replicator@134e0000 {
+ compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
+ reg = <0x0 0x134e0000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+ power-domains = <&cluster0_pd>;
+
+ in-ports {
+ port {
+ ncc0_5_rep_in: endpoint {
+ remote-endpoint = <&etm5_out>;
+ };
+ };
+ };
+
+ out-ports {
+ port {
+ ncc0_5_rep_out: endpoint {
+ remote-endpoint = <&ncc0_1_funnel_in5>;
+ };
+ };
+ };
+ };
+
+ funnel@13d01000 {
+ compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
+ reg = <0x0 0x13d01000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+ power-domains = <&cluster1_pd>;
+
+ in-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@2 {
+ reg = <2>;
+
+ ncc1_2_funnel_in2: endpoint {
+ remote-endpoint = <&ncc1_1_funnel_out>;
+ };
+ };
+ };
+
+ out-ports {
+ port {
+ ncc1_2_funnel_out: endpoint {
+ remote-endpoint = <&ncc1_etf_in>;
+ };
+ };
+ };
+ };
+
+ tmc@13d09000 {
+ compatible = "arm,coresight-tmc", "arm,primecell";
+ reg = <0x0 0x13d09000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+ power-domains = <&cluster1_pd>;
+
+ in-ports {
+ port {
+ ncc1_etf_in: endpoint {
+ remote-endpoint = <&ncc1_2_funnel_out>;
+ };
+ };
+ };
+
+ out-ports {
+ port {
+ ncc1_etf_out: endpoint {
+ remote-endpoint = <&apss_funnel_in1>;
+ };
+ };
+ };
+ };
+
+ funnel@13d81000 {
+ compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
+ reg = <0x0 0x13d81000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+ power-domains = <&cluster1_pd>;
+
+ in-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ ncc1_1_funnel_in0: endpoint {
+ remote-endpoint = <&ncc1_0_rep_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ ncc1_1_funnel_in1: endpoint {
+ remote-endpoint = <&ncc1_1_rep_out>;
+ };
+ };
+ };
+
+ out-ports {
+ port {
+ ncc1_1_funnel_out: endpoint {
+ remote-endpoint = <&ncc1_2_funnel_in2>;
+ };
+ };
+ };
+ };
+
+ replicator@13d90000 {
+ compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
+ reg = <0x0 0x13d90000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+ power-domains = <&cluster1_pd>;
+
+ in-ports {
+ port {
+ ncc1_0_rep_in: endpoint {
+ remote-endpoint = <&etm6_out>;
+ };
+ };
+ };
+
+ out-ports {
+ port {
+ ncc1_0_rep_out: endpoint {
+ remote-endpoint = <&ncc1_1_funnel_in0>;
+ };
+ };
+ };
+ };
+
+ replicator@13da0000 {
+ compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
+ reg = <0x0 0x13da0000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+ power-domains = <&cluster1_pd>;
+
+ in-ports {
+ port {
+ ncc1_1_rep_in: endpoint {
+ remote-endpoint = <&etm7_out>;
+ };
+ };
+ };
+
+ out-ports {
+ port {
+ ncc1_1_rep_out: endpoint {
+ remote-endpoint = <&ncc1_1_funnel_in1>;
+ };
+ };
+ };
+ };
+
apps_smmu: iommu@15000000 {
compatible = "qcom,sm8750-smmu-500", "qcom,smmu-500", "arm,mmu-500";
reg = <0x0 0x15000000 0x0 0x100000>;
--
2.34.1
^ permalink raw reply [flat|nested] 9+ messages in thread* [PATCH 3/4] arm64: dts: qcom: kaanapali: Add CoreSight nodes for APSS debug block
2026-09-22 10:35 [PATCH 0/4] Add ETM devices for multiple QCOM platforms Jie Gan
2026-09-22 10:35 ` [PATCH 1/4] arm64: dts: qcom: hamoa: Add CoreSight nodes for APSS debug block Jie Gan
2026-09-22 10:35 ` [PATCH 2/4] arm64: dts: qcom: sm8750: " Jie Gan
@ 2026-09-22 10:35 ` Jie Gan
2026-10-13 12:49 ` Konrad Dybcio
2026-09-22 10:35 ` [PATCH 4/4] arm64: dts: qcom: glymur: " Jie Gan
3 siblings, 1 reply; 9+ messages in thread
From: Jie Gan @ 2026-09-22 10:35 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Abel Vesa, Rob Herring,
Krzysztof Kozlowski, Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel, Jie Gan
The APSS debug block is built with CoreSight devices like ETE,
replicator, funnel and TMC ETF. Add dt nodes for these devices to enable
ETM trace.
The replicator, funnel and TMC ETF nodes in this block are physically
powered by the CPU cluster power rail rather than by a dedicated always-on
rail. Add a power-domains property referencing the cluster_pd domain to
each of these nodes, so their power state is tied to the CPU cluster
domain and the runtime PM core can power the domain on before the
devices are accessed and let it be powered off otherwise.
Signed-off-by: Jie Gan <jie.gan@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/kaanapali.dtsi | 567 ++++++++++++++++++++++++++++++++
1 file changed, 567 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/kaanapali.dtsi b/arch/arm64/boot/dts/qcom/kaanapali.dtsi
index 131fd2a16c54..d9313de53ee5 100644
--- a/arch/arm64/boot/dts/qcom/kaanapali.dtsi
+++ b/arch/arm64/boot/dts/qcom/kaanapali.dtsi
@@ -218,6 +218,110 @@ domain_ss3: domain-sleep-0 {
};
};
+ ete-0 {
+ compatible = "arm,embedded-trace-extension";
+ cpu = <&cpu0>;
+
+ out-ports {
+ port {
+ etm0_out: endpoint {
+ remote-endpoint = <&ncc0_0_rep_in>;
+ };
+ };
+ };
+ };
+
+ ete-1 {
+ compatible = "arm,embedded-trace-extension";
+ cpu = <&cpu1>;
+
+ out-ports {
+ port {
+ etm1_out: endpoint {
+ remote-endpoint = <&ncc0_1_rep_in>;
+ };
+ };
+ };
+ };
+
+ ete-2 {
+ compatible = "arm,embedded-trace-extension";
+ cpu = <&cpu2>;
+
+ out-ports {
+ port {
+ etm2_out: endpoint {
+ remote-endpoint = <&ncc0_2_rep_in>;
+ };
+ };
+ };
+ };
+
+ ete-3 {
+ compatible = "arm,embedded-trace-extension";
+ cpu = <&cpu3>;
+
+ out-ports {
+ port {
+ etm3_out: endpoint {
+ remote-endpoint = <&ncc0_3_rep_in>;
+ };
+ };
+ };
+ };
+
+ ete-4 {
+ compatible = "arm,embedded-trace-extension";
+ cpu = <&cpu4>;
+
+ out-ports {
+ port {
+ etm4_out: endpoint {
+ remote-endpoint = <&ncc0_4_rep_in>;
+ };
+ };
+ };
+ };
+
+ ete-5 {
+ compatible = "arm,embedded-trace-extension";
+ cpu = <&cpu5>;
+
+ out-ports {
+ port {
+ etm5_out: endpoint {
+ remote-endpoint = <&ncc0_5_rep_in>;
+ };
+ };
+ };
+ };
+
+ ete-6 {
+ compatible = "arm,embedded-trace-extension";
+ cpu = <&cpu6>;
+
+ out-ports {
+ port {
+ etm6_out: endpoint {
+ remote-endpoint = <&ncc1_0_rep_in>;
+ };
+ };
+ };
+ };
+
+ ete-7 {
+ compatible = "arm,embedded-trace-extension";
+ cpu = <&cpu7>;
+
+ out-ports {
+ port {
+ etm7_out: endpoint {
+ remote-endpoint = <&ncc1_1_rep_in>;
+ };
+ };
+ };
+ };
+
firmware {
scm: scm {
compatible = "qcom,scm-kaanapali", "qcom,scm";
@@ -5292,6 +5396,14 @@ tn_ag_in37: endpoint {
remote-endpoint = <&tpdm_ipcc_cmb3_out>;
};
};
+
+ port@36 {
+ reg = <0x36>;
+
+ tn_ag_in54: endpoint {
+ remote-endpoint = <&apss_funnel_out>;
+ };
+ };
};
out-ports {
@@ -5577,6 +5689,43 @@ tpdm_ipa_out: endpoint {
};
};
+ funnel@12080000 {
+ compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
+ reg = <0x0 0x12080000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ in-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ apss_funnel_in0: endpoint {
+ remote-endpoint = <&ncc0_etf_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ apss_funnel_in1: endpoint {
+ remote-endpoint = <&ncc1_etf_out>;
+ };
+ };
+ };
+
+ out-ports {
+ port {
+ apss_funnel_out: endpoint {
+ remote-endpoint = <&tn_ag_in54>;
+ };
+ };
+ };
+ };
+
sram@14680000 {
compatible = "qcom,kaanapali-imem", "mmio-sram";
reg = <0x0 0x14680000 0x0 0x1000>;
@@ -5970,6 +6119,424 @@ rpmhpd_opp_super_turbo_no_cpr: opp-480 {
};
};
+ funnel@1d021000 {
+ compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
+ reg = <0x0 0x1d021000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+ power-domains = <&cluster_pd>;
+
+ in-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@2 {
+ reg = <2>;
+
+ ncc0_2_funnel_in2: endpoint {
+ remote-endpoint = <&ncc0_1_funnel_out>;
+ };
+ };
+ };
+
+ out-ports {
+ port {
+ ncc0_2_funnel_out: endpoint {
+ remote-endpoint = <&ncc0_etf_in>;
+ };
+ };
+ };
+ };
+
+ tmc@1d029000 {
+ compatible = "arm,coresight-tmc", "arm,primecell";
+ reg = <0x0 0x1d029000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+ power-domains = <&cluster_pd>;
+
+ in-ports {
+ port {
+ ncc0_etf_in: endpoint {
+ remote-endpoint = <&ncc0_2_funnel_out>;
+ };
+ };
+ };
+
+ out-ports {
+ port {
+ ncc0_etf_out: endpoint {
+ remote-endpoint = <&apss_funnel_in0>;
+ };
+ };
+ };
+ };
+
+ funnel@1d081000 {
+ compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
+ reg = <0x0 0x1d081000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+ power-domains = <&cluster_pd>;
+
+ in-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ ncc0_1_funnel_in0: endpoint {
+ remote-endpoint = <&ncc0_0_rep_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ ncc0_1_funnel_in1: endpoint {
+ remote-endpoint = <&ncc0_1_rep_out>;
+ };
+ };
+
+ port@2 {
+ reg = <2>;
+
+ ncc0_1_funnel_in2: endpoint {
+ remote-endpoint = <&ncc0_2_rep_out>;
+ };
+ };
+
+ port@3 {
+ reg = <3>;
+
+ ncc0_1_funnel_in3: endpoint {
+ remote-endpoint = <&ncc0_3_rep_out>;
+ };
+ };
+
+ port@4 {
+ reg = <4>;
+
+ ncc0_1_funnel_in4: endpoint {
+ remote-endpoint = <&ncc0_4_rep_out>;
+ };
+ };
+
+ port@5 {
+ reg = <5>;
+
+ ncc0_1_funnel_in5: endpoint {
+ remote-endpoint = <&ncc0_5_rep_out>;
+ };
+ };
+ };
+
+ out-ports {
+ port {
+ ncc0_1_funnel_out: endpoint {
+ remote-endpoint = <&ncc0_2_funnel_in2>;
+ };
+ };
+ };
+ };
+
+ replicator@1d090000 {
+ compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
+ reg = <0x0 0x1d090000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+ power-domains = <&cluster_pd>;
+
+ in-ports {
+ port {
+ ncc0_0_rep_in: endpoint {
+ remote-endpoint = <&etm0_out>;
+ };
+ };
+ };
+
+ out-ports {
+ port {
+ ncc0_0_rep_out: endpoint {
+ remote-endpoint = <&ncc0_1_funnel_in0>;
+ };
+ };
+ };
+ };
+
+ replicator@1d0a0000 {
+ compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
+ reg = <0x0 0x1d0a0000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+ power-domains = <&cluster_pd>;
+
+ in-ports {
+ port {
+ ncc0_1_rep_in: endpoint {
+ remote-endpoint = <&etm1_out>;
+ };
+ };
+ };
+
+ out-ports {
+ port {
+ ncc0_1_rep_out: endpoint {
+ remote-endpoint = <&ncc0_1_funnel_in1>;
+ };
+ };
+ };
+ };
+
+ replicator@1d0b0000 {
+ compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
+ reg = <0x0 0x1d0b0000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+ power-domains = <&cluster_pd>;
+
+ in-ports {
+ port {
+ ncc0_2_rep_in: endpoint {
+ remote-endpoint = <&etm2_out>;
+ };
+ };
+ };
+
+ out-ports {
+ port {
+ ncc0_2_rep_out: endpoint {
+ remote-endpoint = <&ncc0_1_funnel_in2>;
+ };
+ };
+ };
+ };
+
+ replicator@1d0c0000 {
+ compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
+ reg = <0x0 0x1d0c0000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+ power-domains = <&cluster_pd>;
+
+ in-ports {
+ port {
+ ncc0_3_rep_in: endpoint {
+ remote-endpoint = <&etm3_out>;
+ };
+ };
+ };
+
+ out-ports {
+ port {
+ ncc0_3_rep_out: endpoint {
+ remote-endpoint = <&ncc0_1_funnel_in3>;
+ };
+ };
+ };
+ };
+
+ replicator@1d0d0000 {
+ compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
+ reg = <0x0 0x1d0d0000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+ power-domains = <&cluster_pd>;
+
+ in-ports {
+ port {
+ ncc0_4_rep_in: endpoint {
+ remote-endpoint = <&etm4_out>;
+ };
+ };
+ };
+
+ out-ports {
+ port {
+ ncc0_4_rep_out: endpoint {
+ remote-endpoint = <&ncc0_1_funnel_in4>;
+ };
+ };
+ };
+ };
+
+ replicator@1d0e0000 {
+ compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
+ reg = <0x0 0x1d0e0000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+ power-domains = <&cluster_pd>;
+
+ in-ports {
+ port {
+ ncc0_5_rep_in: endpoint {
+ remote-endpoint = <&etm5_out>;
+ };
+ };
+ };
+
+ out-ports {
+ port {
+ ncc0_5_rep_out: endpoint {
+ remote-endpoint = <&ncc0_1_funnel_in5>;
+ };
+ };
+ };
+ };
+
+ funnel@1d121000 {
+ compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
+ reg = <0x0 0x1d121000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+ power-domains = <&cluster_pd>;
+
+ in-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@2 {
+ reg = <2>;
+
+ ncc1_2_funnel_in2: endpoint {
+ remote-endpoint = <&ncc1_1_funnel_out>;
+ };
+ };
+ };
+
+ out-ports {
+ port {
+ ncc1_2_funnel_out: endpoint {
+ remote-endpoint = <&ncc1_etf_in>;
+ };
+ };
+ };
+ };
+
+ tmc@1d129000 {
+ compatible = "arm,coresight-tmc", "arm,primecell";
+ reg = <0x0 0x1d129000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+ power-domains = <&cluster_pd>;
+
+ in-ports {
+ port {
+ ncc1_etf_in: endpoint {
+ remote-endpoint = <&ncc1_2_funnel_out>;
+ };
+ };
+ };
+
+ out-ports {
+ port {
+ ncc1_etf_out: endpoint {
+ remote-endpoint = <&apss_funnel_in1>;
+ };
+ };
+ };
+ };
+
+ funnel@1d181000 {
+ compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
+ reg = <0x0 0x1d181000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+ power-domains = <&cluster_pd>;
+
+ in-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ ncc1_1_funnel_in0: endpoint {
+ remote-endpoint = <&ncc1_0_rep_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ ncc1_1_funnel_in1: endpoint {
+ remote-endpoint = <&ncc1_1_rep_out>;
+ };
+ };
+ };
+
+ out-ports {
+ port {
+ ncc1_1_funnel_out: endpoint {
+ remote-endpoint = <&ncc1_2_funnel_in2>;
+ };
+ };
+ };
+ };
+
+ replicator@1d190000 {
+ compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
+ reg = <0x0 0x1d190000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+ power-domains = <&cluster_pd>;
+
+ in-ports {
+ port {
+ ncc1_0_rep_in: endpoint {
+ remote-endpoint = <&etm6_out>;
+ };
+ };
+ };
+
+ out-ports {
+ port {
+ ncc1_0_rep_out: endpoint {
+ remote-endpoint = <&ncc1_1_funnel_in0>;
+ };
+ };
+ };
+ };
+
+ replicator@1d1a0000 {
+ compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
+ reg = <0x0 0x1d1a0000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+ power-domains = <&cluster_pd>;
+
+ in-ports {
+ port {
+ ncc1_1_rep_in: endpoint {
+ remote-endpoint = <&etm7_out>;
+ };
+ };
+ };
+
+ out-ports {
+ port {
+ ncc1_1_rep_out: endpoint {
+ remote-endpoint = <&ncc1_1_funnel_in1>;
+ };
+ };
+ };
+ };
+
nsp_noc: interconnect@260c0000 {
compatible = "qcom,kaanapali-nsp-noc";
reg = <0x0 0x260c0000 0x0 0x21280>;
--
2.34.1
^ permalink raw reply [flat|nested] 9+ messages in thread* Re: [PATCH 3/4] arm64: dts: qcom: kaanapali: Add CoreSight nodes for APSS debug block
2026-09-22 10:35 ` [PATCH 3/4] arm64: dts: qcom: kaanapali: " Jie Gan
@ 2026-10-13 12:49 ` Konrad Dybcio
2026-10-14 1:23 ` Jie Gan
0 siblings, 1 reply; 9+ messages in thread
From: Konrad Dybcio @ 2026-10-13 12:49 UTC (permalink / raw)
To: Jie Gan, Bjorn Andersson, Konrad Dybcio, Abel Vesa, Rob Herring,
Krzysztof Kozlowski, Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel
On 9/22/26 12:35 PM, Jie Gan wrote:
> The APSS debug block is built with CoreSight devices like ETE,
> replicator, funnel and TMC ETF. Add dt nodes for these devices to enable
> ETM trace.
>
> The replicator, funnel and TMC ETF nodes in this block are physically
> powered by the CPU cluster power rail rather than by a dedicated always-on
> rail. Add a power-domains property referencing the cluster_pd domain to
> each of these nodes, so their power state is tied to the CPU cluster
> domain and the runtime PM core can power the domain on before the
> devices are accessed and let it be powered off otherwise.
>
> Signed-off-by: Jie Gan <jie.gan@oss.qualcomm.com>
> ---
> arch/arm64/boot/dts/qcom/kaanapali.dtsi | 567 ++++++++++++++++++++++++++++++++
> 1 file changed, 567 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/kaanapali.dtsi b/arch/arm64/boot/dts/qcom/kaanapali.dtsi
> index 131fd2a16c54..d9313de53ee5 100644
> --- a/arch/arm64/boot/dts/qcom/kaanapali.dtsi
> +++ b/arch/arm64/boot/dts/qcom/kaanapali.dtsi
> @@ -218,6 +218,110 @@ domain_ss3: domain-sleep-0 {
> };
> };
>
> + ete-0 {
> + compatible = "arm,embedded-trace-extension";
No power-domains for these too?
[...]
> + tmc@1d029000 {
> + compatible = "arm,coresight-tmc", "arm,primecell";
> + reg = <0x0 0x1d029000 0x0 0x1000>;
> +
> + clocks = <&aoss_qmp>;
> + clock-names = "apb_pclk";
> + power-domains = <&cluster_pd>;
Is there only being a single cluster_pd a mistake on kaanapali?
The CPUs have a different Aff1 value in the MPIDR register, so one
would think there's 2 (also according to the cpu-map)
Konrad
^ permalink raw reply [flat|nested] 9+ messages in thread* Re: [PATCH 3/4] arm64: dts: qcom: kaanapali: Add CoreSight nodes for APSS debug block
2026-10-13 12:49 ` Konrad Dybcio
@ 2026-10-14 1:23 ` Jie Gan
0 siblings, 0 replies; 9+ messages in thread
From: Jie Gan @ 2026-10-14 1:23 UTC (permalink / raw)
To: Konrad Dybcio, Bjorn Andersson, Konrad Dybcio, Abel Vesa,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Jingyi Wang
Cc: linux-arm-msm, devicetree, linux-kernel
On 10/13/2026 8:49 PM, Konrad Dybcio wrote:
> On 9/22/26 12:35 PM, Jie Gan wrote:
>> The APSS debug block is built with CoreSight devices like ETE,
>> replicator, funnel and TMC ETF. Add dt nodes for these devices to enable
>> ETM trace.
>>
>> The replicator, funnel and TMC ETF nodes in this block are physically
>> powered by the CPU cluster power rail rather than by a dedicated always-on
>> rail. Add a power-domains property referencing the cluster_pd domain to
>> each of these nodes, so their power state is tied to the CPU cluster
>> domain and the runtime PM core can power the domain on before the
>> devices are accessed and let it be powered off otherwise.
>>
>> Signed-off-by: Jie Gan <jie.gan@oss.qualcomm.com>
>> ---
>> arch/arm64/boot/dts/qcom/kaanapali.dtsi | 567 ++++++++++++++++++++++++++++++++
>> 1 file changed, 567 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/kaanapali.dtsi b/arch/arm64/boot/dts/qcom/kaanapali.dtsi
>> index 131fd2a16c54..d9313de53ee5 100644
>> --- a/arch/arm64/boot/dts/qcom/kaanapali.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/kaanapali.dtsi
>> @@ -218,6 +218,110 @@ domain_ss3: domain-sleep-0 {
>> };
>> };
>>
>> + ete-0 {
>> + compatible = "arm,embedded-trace-extension";
>
> No power-domains for these too?
ETM/ETE device is the debug device of the CPU, no power-domain property
attached to the device and the power management operations relies on the
CPU itself.
I missed qcom,skip-power-up; for those nodes, ETE device should not
check the power state of the device.
Will send new version to address it.
>
> [...]
>
>> + tmc@1d029000 {
>> + compatible = "arm,coresight-tmc", "arm,primecell";
>> + reg = <0x0 0x1d029000 0x0 0x1000>;
>> +
>> + clocks = <&aoss_qmp>;
>> + clock-names = "apb_pclk";
>> + power-domains = <&cluster_pd>;
>
> Is there only being a single cluster_pd a mistake on kaanapali?
>
From psci map, KNP only has one cluster_pd shared among all CPUs.
Hi Jingyi,
Can you please help to comment this part?
Thanks,
Jie
> The CPUs have a different Aff1 value in the MPIDR register, so one
> would think there's 2 (also according to the cpu-map)
>
> Konrad
^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH 4/4] arm64: dts: qcom: glymur: Add CoreSight nodes for APSS debug block
2026-09-22 10:35 [PATCH 0/4] Add ETM devices for multiple QCOM platforms Jie Gan
` (2 preceding siblings ...)
2026-09-22 10:35 ` [PATCH 3/4] arm64: dts: qcom: kaanapali: " Jie Gan
@ 2026-09-22 10:35 ` Jie Gan
3 siblings, 0 replies; 9+ messages in thread
From: Jie Gan @ 2026-09-22 10:35 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Abel Vesa, Rob Herring,
Krzysztof Kozlowski, Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel, Jie Gan
The APSS debug block is built with CoreSight devices like ETM,
replicator, funnel and TMC ETF. Add dt nodes for these devices to
enable ETM trace.
The replicator, funnel and TMC ETF nodes in this block are physically
powered by the CPU cluster power rail rather than by a dedicated
always-on rail. Add a power-domains property referencing the
corresponding cluster_pdN domain to each of these nodes, so their
power state is tied to the CPU cluster domain and the runtime PM core
can power the domain on before the devices are accessed and let it be
powered off otherwise.
Mahua is based on glymur but only has 12 CPUs across two clusters
instead of 18 across three, so delete the ETM and cluster2 CoreSight
nodes that have no corresponding CPUs on that platform.
Signed-off-by: Jie Gan <jie.gan@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/glymur.dtsi | 1184 ++++++++++++++++++++++++++++++++++
arch/arm64/boot/dts/qcom/mahua.dtsi | 16 +
2 files changed, 1200 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/glymur.dtsi b/arch/arm64/boot/dts/qcom/glymur.dtsi
index de7c395d9c35..049bebbb80f9 100644
--- a/arch/arm64/boot/dts/qcom/glymur.dtsi
+++ b/arch/arm64/boot/dts/qcom/glymur.dtsi
@@ -397,6 +397,312 @@ eud_in: endpoint {
};
};
+ etm-0 {
+ compatible = "arm,coresight-etm4x-sysreg";
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+ cpu = <&cpu0>;
+ qcom,skip-power-up;
+
+ out-ports {
+ port {
+ etm0_out: endpoint {
+ remote-endpoint = <&ncc0_0_rep_in>;
+ };
+ };
+ };
+ };
+
+ etm-1 {
+ compatible = "arm,coresight-etm4x-sysreg";
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+ cpu = <&cpu1>;
+ qcom,skip-power-up;
+
+ out-ports {
+ port {
+ etm1_out: endpoint {
+ remote-endpoint = <&ncc0_1_rep_in>;
+ };
+ };
+ };
+ };
+
+ etm-2 {
+ compatible = "arm,coresight-etm4x-sysreg";
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+ cpu = <&cpu2>;
+ qcom,skip-power-up;
+
+ out-ports {
+ port {
+ etm2_out: endpoint {
+ remote-endpoint = <&ncc0_2_rep_in>;
+ };
+ };
+ };
+ };
+
+ etm-3 {
+ compatible = "arm,coresight-etm4x-sysreg";
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+ cpu = <&cpu3>;
+ qcom,skip-power-up;
+
+ out-ports {
+ port {
+ etm3_out: endpoint {
+ remote-endpoint = <&ncc0_3_rep_in>;
+ };
+ };
+ };
+ };
+
+ etm-4 {
+ compatible = "arm,coresight-etm4x-sysreg";
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+ cpu = <&cpu4>;
+ qcom,skip-power-up;
+
+ out-ports {
+ port {
+ etm4_out: endpoint {
+ remote-endpoint = <&ncc0_4_rep_in>;
+ };
+ };
+ };
+ };
+
+ etm-5 {
+ compatible = "arm,coresight-etm4x-sysreg";
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+ cpu = <&cpu5>;
+ qcom,skip-power-up;
+
+ out-ports {
+ port {
+ etm5_out: endpoint {
+ remote-endpoint = <&ncc0_5_rep_in>;
+ };
+ };
+ };
+ };
+
+ etm-6 {
+ compatible = "arm,coresight-etm4x-sysreg";
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+ cpu = <&cpu6>;
+ qcom,skip-power-up;
+
+ out-ports {
+ port {
+ etm6_out: endpoint {
+ remote-endpoint = <&ncc1_0_rep_in>;
+ };
+ };
+ };
+ };
+
+ etm-7 {
+ compatible = "arm,coresight-etm4x-sysreg";
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+ cpu = <&cpu7>;
+ qcom,skip-power-up;
+
+ out-ports {
+ port {
+ etm7_out: endpoint {
+ remote-endpoint = <&ncc1_1_rep_in>;
+ };
+ };
+ };
+ };
+
+ etm-8 {
+ compatible = "arm,coresight-etm4x-sysreg";
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+ cpu = <&cpu8>;
+ qcom,skip-power-up;
+
+ out-ports {
+ port {
+ etm8_out: endpoint {
+ remote-endpoint = <&ncc1_2_rep_in>;
+ };
+ };
+ };
+ };
+
+ etm-9 {
+ compatible = "arm,coresight-etm4x-sysreg";
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+ cpu = <&cpu9>;
+ qcom,skip-power-up;
+
+ out-ports {
+ port {
+ etm9_out: endpoint {
+ remote-endpoint = <&ncc1_3_rep_in>;
+ };
+ };
+ };
+ };
+
+ etm-10 {
+ compatible = "arm,coresight-etm4x-sysreg";
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+ cpu = <&cpu10>;
+ qcom,skip-power-up;
+
+ out-ports {
+ port {
+ etm10_out: endpoint {
+ remote-endpoint = <&ncc1_4_rep_in>;
+ };
+ };
+ };
+ };
+
+ etm-11 {
+ compatible = "arm,coresight-etm4x-sysreg";
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+ cpu = <&cpu11>;
+ qcom,skip-power-up;
+
+ out-ports {
+ port {
+ etm11_out: endpoint {
+ remote-endpoint = <&ncc1_5_rep_in>;
+ };
+ };
+ };
+ };
+
+ etm12: etm-12 {
+ compatible = "arm,coresight-etm4x-sysreg";
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+ cpu = <&cpu12>;
+ qcom,skip-power-up;
+
+ out-ports {
+ port {
+ etm12_out: endpoint {
+ remote-endpoint = <&ncc2_0_rep_in>;
+ };
+ };
+ };
+ };
+
+ etm13: etm-13 {
+ compatible = "arm,coresight-etm4x-sysreg";
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+ cpu = <&cpu13>;
+ qcom,skip-power-up;
+
+ out-ports {
+ port {
+ etm13_out: endpoint {
+ remote-endpoint = <&ncc2_1_rep_in>;
+ };
+ };
+ };
+ };
+
+ etm14: etm-14 {
+ compatible = "arm,coresight-etm4x-sysreg";
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+ cpu = <&cpu14>;
+ qcom,skip-power-up;
+
+ out-ports {
+ port {
+ etm14_out: endpoint {
+ remote-endpoint = <&ncc2_2_rep_in>;
+ };
+ };
+ };
+ };
+
+ etm15: etm-15 {
+ compatible = "arm,coresight-etm4x-sysreg";
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+ cpu = <&cpu15>;
+ qcom,skip-power-up;
+
+ out-ports {
+ port {
+ etm15_out: endpoint {
+ remote-endpoint = <&ncc2_3_rep_in>;
+ };
+ };
+ };
+ };
+
+ etm16: etm-16 {
+ compatible = "arm,coresight-etm4x-sysreg";
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+ cpu = <&cpu16>;
+ qcom,skip-power-up;
+
+ out-ports {
+ port {
+ etm16_out: endpoint {
+ remote-endpoint = <&ncc2_4_rep_in>;
+ };
+ };
+ };
+ };
+
+ etm17: etm-17 {
+ compatible = "arm,coresight-etm4x-sysreg";
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+ cpu = <&cpu17>;
+ qcom,skip-power-up;
+
+ out-ports {
+ port {
+ etm17_out: endpoint {
+ remote-endpoint = <&ncc2_5_rep_in>;
+ };
+ };
+ };
+ };
+
firmware {
scm: scm {
compatible = "qcom,scm-glymur", "qcom,scm";
@@ -7244,6 +7550,14 @@ tn_ag_in53: endpoint {
};
};
+ port@36 {
+ reg = <0x36>;
+
+ tn_ag_in54: endpoint {
+ remote-endpoint = <&apss_funnel_out>;
+ };
+ };
+
port@3f {
reg = <0x3f>;
@@ -7625,6 +7939,51 @@ pcie_rscc_tpda_out: endpoint {
};
};
+ funnel@12080000 {
+ compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
+ reg = <0x0 0x12080000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ in-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ apss_funnel_in0: endpoint {
+ remote-endpoint = <&ncc0_etf_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ apss_funnel_in1: endpoint {
+ remote-endpoint = <&ncc1_etf_out>;
+ };
+ };
+
+ port@2 {
+ reg = <2>;
+
+ apss_funnel_in2: endpoint {
+ remote-endpoint = <&ncc2_etf_out>;
+ };
+ };
+ };
+
+ out-ports {
+ port {
+ apss_funnel_out: endpoint {
+ remote-endpoint = <&tn_ag_in54>;
+ };
+ };
+ };
+ };
+
tpdm@11c03000 {
compatible = "qcom,coresight-tpdm", "arm,primecell";
reg = <0x0 0x11c03000 0x0 0x1000>;
@@ -8286,6 +8645,831 @@ rpmhpd_opp_turbo_l1: opp-416 {
};
};
+ funnel@1d021000 {
+ compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
+ reg = <0x0 0x1d021000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+ power-domains = <&cluster0_pd>;
+
+ in-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@2 {
+ reg = <2>;
+
+ ncc0_2_funnel_in2: endpoint {
+ remote-endpoint = <&ncc0_1_funnel_out>;
+ };
+ };
+ };
+
+ out-ports {
+ port {
+ ncc0_2_funnel_out: endpoint {
+ remote-endpoint = <&ncc0_etf_in>;
+ };
+ };
+ };
+ };
+
+ tmc@1d029000 {
+ compatible = "arm,coresight-tmc", "arm,primecell";
+ reg = <0x0 0x1d029000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+ power-domains = <&cluster0_pd>;
+
+ in-ports {
+ port {
+ ncc0_etf_in: endpoint {
+ remote-endpoint = <&ncc0_2_funnel_out>;
+ };
+ };
+ };
+
+ out-ports {
+ port {
+ ncc0_etf_out: endpoint {
+ remote-endpoint = <&apss_funnel_in0>;
+ };
+ };
+ };
+ };
+
+ funnel@1d081000 {
+ compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
+ reg = <0x0 0x1d081000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+ power-domains = <&cluster0_pd>;
+
+ in-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ ncc0_1_funnel_in0: endpoint {
+ remote-endpoint = <&ncc0_0_rep_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ ncc0_1_funnel_in1: endpoint {
+ remote-endpoint = <&ncc0_1_rep_out>;
+ };
+ };
+
+ port@2 {
+ reg = <2>;
+
+ ncc0_1_funnel_in2: endpoint {
+ remote-endpoint = <&ncc0_2_rep_out>;
+ };
+ };
+
+ port@3 {
+ reg = <3>;
+
+ ncc0_1_funnel_in3: endpoint {
+ remote-endpoint = <&ncc0_3_rep_out>;
+ };
+ };
+
+ port@4 {
+ reg = <4>;
+
+ ncc0_1_funnel_in4: endpoint {
+ remote-endpoint = <&ncc0_4_rep_out>;
+ };
+ };
+
+ port@5 {
+ reg = <5>;
+
+ ncc0_1_funnel_in5: endpoint {
+ remote-endpoint = <&ncc0_5_rep_out>;
+ };
+ };
+ };
+
+ out-ports {
+ port {
+ ncc0_1_funnel_out: endpoint {
+ remote-endpoint = <&ncc0_2_funnel_in2>;
+ };
+ };
+ };
+ };
+
+ replicator@1d090000 {
+ compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
+ reg = <0x0 0x1d090000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+ power-domains = <&cluster0_pd>;
+
+ in-ports {
+ port {
+ ncc0_0_rep_in: endpoint {
+ remote-endpoint = <&etm0_out>;
+ };
+ };
+ };
+
+ out-ports {
+ port {
+ ncc0_0_rep_out: endpoint {
+ remote-endpoint = <&ncc0_1_funnel_in0>;
+ };
+ };
+ };
+ };
+
+ replicator@1d0a0000 {
+ compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
+ reg = <0x0 0x1d0a0000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+ power-domains = <&cluster0_pd>;
+
+ in-ports {
+ port {
+ ncc0_1_rep_in: endpoint {
+ remote-endpoint = <&etm1_out>;
+ };
+ };
+ };
+
+ out-ports {
+ port {
+ ncc0_1_rep_out: endpoint {
+ remote-endpoint = <&ncc0_1_funnel_in1>;
+ };
+ };
+ };
+ };
+
+ replicator@1d0b0000 {
+ compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
+ reg = <0x0 0x1d0b0000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+ power-domains = <&cluster0_pd>;
+
+ in-ports {
+ port {
+ ncc0_2_rep_in: endpoint {
+ remote-endpoint = <&etm2_out>;
+ };
+ };
+ };
+
+ out-ports {
+ port {
+ ncc0_2_rep_out: endpoint {
+ remote-endpoint = <&ncc0_1_funnel_in2>;
+ };
+ };
+ };
+ };
+
+ replicator@1d0c0000 {
+ compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
+ reg = <0x0 0x1d0c0000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+ power-domains = <&cluster0_pd>;
+
+ in-ports {
+ port {
+ ncc0_3_rep_in: endpoint {
+ remote-endpoint = <&etm3_out>;
+ };
+ };
+ };
+
+ out-ports {
+ port {
+ ncc0_3_rep_out: endpoint {
+ remote-endpoint = <&ncc0_1_funnel_in3>;
+ };
+ };
+ };
+ };
+
+ replicator@1d0d0000 {
+ compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
+ reg = <0x0 0x1d0d0000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+ power-domains = <&cluster0_pd>;
+
+ in-ports {
+ port {
+ ncc0_4_rep_in: endpoint {
+ remote-endpoint = <&etm4_out>;
+ };
+ };
+ };
+
+ out-ports {
+ port {
+ ncc0_4_rep_out: endpoint {
+ remote-endpoint = <&ncc0_1_funnel_in4>;
+ };
+ };
+ };
+ };
+
+ replicator@1d0e0000 {
+ compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
+ reg = <0x0 0x1d0e0000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+ power-domains = <&cluster0_pd>;
+
+ in-ports {
+ port {
+ ncc0_5_rep_in: endpoint {
+ remote-endpoint = <&etm5_out>;
+ };
+ };
+ };
+
+ out-ports {
+ port {
+ ncc0_5_rep_out: endpoint {
+ remote-endpoint = <&ncc0_1_funnel_in5>;
+ };
+ };
+ };
+ };
+
+ funnel@1d121000 {
+ compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
+ reg = <0x0 0x1d121000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+ power-domains = <&cluster1_pd>;
+
+ in-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@2 {
+ reg = <2>;
+
+ ncc1_2_funnel_in2: endpoint {
+ remote-endpoint = <&ncc1_1_funnel_out>;
+ };
+ };
+ };
+
+ out-ports {
+ port {
+ ncc1_2_funnel_out: endpoint {
+ remote-endpoint = <&ncc1_etf_in>;
+ };
+ };
+ };
+ };
+
+ tmc@1d129000 {
+ compatible = "arm,coresight-tmc", "arm,primecell";
+ reg = <0x0 0x1d129000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+ power-domains = <&cluster1_pd>;
+
+ in-ports {
+ port {
+ ncc1_etf_in: endpoint {
+ remote-endpoint = <&ncc1_2_funnel_out>;
+ };
+ };
+ };
+
+ out-ports {
+ port {
+ ncc1_etf_out: endpoint {
+ remote-endpoint = <&apss_funnel_in1>;
+ };
+ };
+ };
+ };
+
+ funnel@1d181000 {
+ compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
+ reg = <0x0 0x1d181000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+ power-domains = <&cluster1_pd>;
+
+ in-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ ncc1_1_funnel_in0: endpoint {
+ remote-endpoint = <&ncc1_0_rep_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ ncc1_1_funnel_in1: endpoint {
+ remote-endpoint = <&ncc1_1_rep_out>;
+ };
+ };
+
+ port@2 {
+ reg = <2>;
+
+ ncc1_1_funnel_in2: endpoint {
+ remote-endpoint = <&ncc1_2_rep_out>;
+ };
+ };
+
+ port@3 {
+ reg = <3>;
+
+ ncc1_1_funnel_in3: endpoint {
+ remote-endpoint = <&ncc1_3_rep_out>;
+ };
+ };
+
+ port@4 {
+ reg = <4>;
+
+ ncc1_1_funnel_in4: endpoint {
+ remote-endpoint = <&ncc1_4_rep_out>;
+ };
+ };
+
+ port@5 {
+ reg = <5>;
+
+ ncc1_1_funnel_in5: endpoint {
+ remote-endpoint = <&ncc1_5_rep_out>;
+ };
+ };
+ };
+
+ out-ports {
+ port {
+ ncc1_1_funnel_out: endpoint {
+ remote-endpoint = <&ncc1_2_funnel_in2>;
+ };
+ };
+ };
+ };
+
+ replicator@1d190000 {
+ compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
+ reg = <0x0 0x1d190000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+ power-domains = <&cluster1_pd>;
+
+ in-ports {
+ port {
+ ncc1_0_rep_in: endpoint {
+ remote-endpoint = <&etm6_out>;
+ };
+ };
+ };
+
+ out-ports {
+ port {
+ ncc1_0_rep_out: endpoint {
+ remote-endpoint = <&ncc1_1_funnel_in0>;
+ };
+ };
+ };
+ };
+
+ replicator@1d1a0000 {
+ compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
+ reg = <0x0 0x1d1a0000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+ power-domains = <&cluster1_pd>;
+
+ in-ports {
+ port {
+ ncc1_1_rep_in: endpoint {
+ remote-endpoint = <&etm7_out>;
+ };
+ };
+ };
+
+ out-ports {
+ port {
+ ncc1_1_rep_out: endpoint {
+ remote-endpoint = <&ncc1_1_funnel_in1>;
+ };
+ };
+ };
+ };
+
+ replicator@1d1b0000 {
+ compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
+ reg = <0x0 0x1d1b0000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+ power-domains = <&cluster1_pd>;
+
+ in-ports {
+ port {
+ ncc1_2_rep_in: endpoint {
+ remote-endpoint = <&etm8_out>;
+ };
+ };
+ };
+
+ out-ports {
+ port {
+ ncc1_2_rep_out: endpoint {
+ remote-endpoint = <&ncc1_1_funnel_in2>;
+ };
+ };
+ };
+ };
+
+ replicator@1d1c0000 {
+ compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
+ reg = <0x0 0x1d1c0000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+ power-domains = <&cluster1_pd>;
+
+ in-ports {
+ port {
+ ncc1_3_rep_in: endpoint {
+ remote-endpoint = <&etm9_out>;
+ };
+ };
+ };
+
+ out-ports {
+ port {
+ ncc1_3_rep_out: endpoint {
+ remote-endpoint = <&ncc1_1_funnel_in3>;
+ };
+ };
+ };
+ };
+
+ replicator@1d1d0000 {
+ compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
+ reg = <0x0 0x1d1d0000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+ power-domains = <&cluster1_pd>;
+
+ in-ports {
+ port {
+ ncc1_4_rep_in: endpoint {
+ remote-endpoint = <&etm10_out>;
+ };
+ };
+ };
+
+ out-ports {
+ port {
+ ncc1_4_rep_out: endpoint {
+ remote-endpoint = <&ncc1_1_funnel_in4>;
+ };
+ };
+ };
+ };
+
+ replicator@1d1e0000 {
+ compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
+ reg = <0x0 0x1d1e0000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+ power-domains = <&cluster1_pd>;
+
+ in-ports {
+ port {
+ ncc1_5_rep_in: endpoint {
+ remote-endpoint = <&etm11_out>;
+ };
+ };
+ };
+
+ out-ports {
+ port {
+ ncc1_5_rep_out: endpoint {
+ remote-endpoint = <&ncc1_1_funnel_in5>;
+ };
+ };
+ };
+ };
+
+ cluster2_funnel_l2: funnel@1d221000 {
+ compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
+ reg = <0x0 0x1d221000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+ power-domains = <&cluster2_pd>;
+
+ in-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@2 {
+ reg = <2>;
+
+ ncc2_2_funnel_in2: endpoint {
+ remote-endpoint = <&ncc2_1_funnel_out>;
+ };
+ };
+ };
+
+ out-ports {
+ port {
+ ncc2_2_funnel_out: endpoint {
+ remote-endpoint = <&ncc2_etf_in>;
+ };
+ };
+ };
+ };
+
+ cluster2_etf: tmc@1d229000 {
+ compatible = "arm,coresight-tmc", "arm,primecell";
+ reg = <0x0 0x1d229000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+ power-domains = <&cluster2_pd>;
+
+ in-ports {
+ port {
+ ncc2_etf_in: endpoint {
+ remote-endpoint = <&ncc2_2_funnel_out>;
+ };
+ };
+ };
+
+ out-ports {
+ port {
+ ncc2_etf_out: endpoint {
+ remote-endpoint = <&apss_funnel_in2>;
+ };
+ };
+ };
+ };
+
+ cluster2_funnel_l1: funnel@1d281000 {
+ compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
+ reg = <0x0 0x1d281000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+ power-domains = <&cluster2_pd>;
+
+ in-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ ncc2_1_funnel_in0: endpoint {
+ remote-endpoint = <&ncc2_0_rep_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ ncc2_1_funnel_in1: endpoint {
+ remote-endpoint = <&ncc2_1_rep_out>;
+ };
+ };
+
+ port@2 {
+ reg = <2>;
+
+ ncc2_1_funnel_in2: endpoint {
+ remote-endpoint = <&ncc2_2_rep_out>;
+ };
+ };
+
+ port@3 {
+ reg = <3>;
+
+ ncc2_1_funnel_in3: endpoint {
+ remote-endpoint = <&ncc2_3_rep_out>;
+ };
+ };
+
+ port@4 {
+ reg = <4>;
+
+ ncc2_1_funnel_in4: endpoint {
+ remote-endpoint = <&ncc2_4_rep_out>;
+ };
+ };
+
+ port@5 {
+ reg = <5>;
+
+ ncc2_1_funnel_in5: endpoint {
+ remote-endpoint = <&ncc2_5_rep_out>;
+ };
+ };
+ };
+
+ out-ports {
+ port {
+ ncc2_1_funnel_out: endpoint {
+ remote-endpoint = <&ncc2_2_funnel_in2>;
+ };
+ };
+ };
+ };
+
+ cluster2_rep_2_0: replicator@1d290000 {
+ compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
+ reg = <0x0 0x1d290000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+ power-domains = <&cluster2_pd>;
+
+ in-ports {
+ port {
+ ncc2_0_rep_in: endpoint {
+ remote-endpoint = <&etm12_out>;
+ };
+ };
+ };
+
+ out-ports {
+ port {
+ ncc2_0_rep_out: endpoint {
+ remote-endpoint = <&ncc2_1_funnel_in0>;
+ };
+ };
+ };
+ };
+
+ cluster2_rep_2_1: replicator@1d2a0000 {
+ compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
+ reg = <0x0 0x1d2a0000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+ power-domains = <&cluster2_pd>;
+
+ in-ports {
+ port {
+ ncc2_1_rep_in: endpoint {
+ remote-endpoint = <&etm13_out>;
+ };
+ };
+ };
+
+ out-ports {
+ port {
+ ncc2_1_rep_out: endpoint {
+ remote-endpoint = <&ncc2_1_funnel_in1>;
+ };
+ };
+ };
+ };
+
+ cluster2_rep_2_2: replicator@1d2b0000 {
+ compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
+ reg = <0x0 0x1d2b0000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+ power-domains = <&cluster2_pd>;
+
+ in-ports {
+ port {
+ ncc2_2_rep_in: endpoint {
+ remote-endpoint = <&etm14_out>;
+ };
+ };
+ };
+
+ out-ports {
+ port {
+ ncc2_2_rep_out: endpoint {
+ remote-endpoint = <&ncc2_1_funnel_in2>;
+ };
+ };
+ };
+ };
+
+ cluster2_rep_2_3: replicator@1d2c0000 {
+ compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
+ reg = <0x0 0x1d2c0000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+ power-domains = <&cluster2_pd>;
+
+ in-ports {
+ port {
+ ncc2_3_rep_in: endpoint {
+ remote-endpoint = <&etm15_out>;
+ };
+ };
+ };
+
+ out-ports {
+ port {
+ ncc2_3_rep_out: endpoint {
+ remote-endpoint = <&ncc2_1_funnel_in3>;
+ };
+ };
+ };
+ };
+
+ cluster2_rep_2_4: replicator@1d2d0000 {
+ compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
+ reg = <0x0 0x1d2d0000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+ power-domains = <&cluster2_pd>;
+
+ in-ports {
+ port {
+ ncc2_4_rep_in: endpoint {
+ remote-endpoint = <&etm16_out>;
+ };
+ };
+ };
+
+ out-ports {
+ port {
+ ncc2_4_rep_out: endpoint {
+ remote-endpoint = <&ncc2_1_funnel_in4>;
+ };
+ };
+ };
+ };
+
+ cluster2_rep_2_5: replicator@1d2e0000 {
+ compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
+ reg = <0x0 0x1d2e0000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+ power-domains = <&cluster2_pd>;
+
+ in-ports {
+ port {
+ ncc2_5_rep_in: endpoint {
+ remote-endpoint = <&etm17_out>;
+ };
+ };
+ };
+
+ out-ports {
+ port {
+ ncc2_5_rep_out: endpoint {
+ remote-endpoint = <&ncc2_1_funnel_in5>;
+ };
+ };
+ };
+ };
+
nsi_noc: interconnect@1d600000 {
compatible = "qcom,glymur-nsinoc";
reg = <0x0 0x1d600000 0x0 0x14080>;
diff --git a/arch/arm64/boot/dts/qcom/mahua.dtsi b/arch/arm64/boot/dts/qcom/mahua.dtsi
index a59c5ed7b48e..77a456fb0772 100644
--- a/arch/arm64/boot/dts/qcom/mahua.dtsi
+++ b/arch/arm64/boot/dts/qcom/mahua.dtsi
@@ -6,8 +6,18 @@
/* Mahua is heavily based on Glymur, with some meaningful differences */
#include "glymur.dtsi"
+/delete-node/ &apss_funnel_in2;
/delete-node/ &bwmon_cluster2;
+/delete-node/ &cluster2_etf;
+/delete-node/ &cluster2_funnel_l1;
+/delete-node/ &cluster2_funnel_l2;
/delete-node/ &cluster2_pd;
+/delete-node/ &cluster2_rep_2_0;
+/delete-node/ &cluster2_rep_2_1;
+/delete-node/ &cluster2_rep_2_2;
+/delete-node/ &cluster2_rep_2_3;
+/delete-node/ &cluster2_rep_2_4;
+/delete-node/ &cluster2_rep_2_5;
/delete-node/ &cpu_map_cluster2;
/delete-node/ &cpu12;
/delete-node/ &cpu13;
@@ -22,6 +32,12 @@
/delete-node/ &cpu_pd16;
/delete-node/ &cpu_pd17;
/delete-node/ &cti_wpss;
+/delete-node/ &etm12;
+/delete-node/ &etm13;
+/delete-node/ &etm14;
+/delete-node/ &etm15;
+/delete-node/ &etm16;
+/delete-node/ &etm17;
/delete-node/ &pcie3_phy;
/delete-node/ &pcie3a;
/delete-node/ &thermal_aoss_6;
--
2.34.1
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