[PATCH 0/2] arm64: dts: qcom: sm8350: Add CPU and LLCC BWMON

[PATCH 0/2] arm64: dts: qcom: sm8350: Add CPU and LLCC BWMON

[Demeter Barna via B4 Relay]

Add the CPU (CPU to LLCC) and LLCC (LLCC to DDR) bandwidth monitors of
SM8350, as SM8250 and SM8550 have them.

Tested on a Razer Edge 5G, whose board support is not upstream yet:
both monitors probe and their votes follow the memory traffic, also
after a system suspend. On top of the CPU OPP votes of [1], they add
14-15 % copy bandwidth on the A55 and A78 cores.

[1] https://patch.msgid.link/20261016-sm8350-cpu-bw-v1-0-044ac6dc9565@fromdisposition.org

---
Demeter Barna (2):
      dt-bindings: interconnect: qcom,msm8998-bwmon: Add SM8350 CPU and LLCC BWMON
      arm64: dts: qcom: sm8350: Add CPU and LLCC BWMON

 .../bindings/interconnect/qcom,msm8998-bwmon.yaml  |   2 +
 arch/arm64/boot/dts/qcom/sm8350.dtsi               | 100 +++++++++++++++++++++
 2 files changed, 102 insertions(+)
---
base-commit: 4eb2586bd40db27d77cc5b724ca9386ed0c71d53
change-id: 20261016-sm8350-bwmon-a36568cb203c

Best regards,
--  
Demeter Barna <me@fromdisposition.org>

[PATCH 1/2] dt-bindings: interconnect: qcom,msm8998-bwmon: Add SM8350 CPU and LLCC BWMON

[Demeter Barna via B4 Relay]

From: Demeter Barna <me@fromdisposition.org>

Document the SM8350 CPU BWMON, compatible with the SDM845 one (v4),
and the LLCC BWMON, compatible with the SC7280 one (v5).

Assisted-by: LLM
Signed-off-by: Demeter Barna <me@fromdisposition.org>
---
 Documentation/devicetree/bindings/interconnect/qcom,msm8998-bwmon.yaml | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/Documentation/devicetree/bindings/interconnect/qcom,msm8998-bwmon.yaml b/Documentation/devicetree/bindings/interconnect/qcom,msm8998-bwmon.yaml
index f6969910bded..af4a81ca080c 100644
--- a/Documentation/devicetree/bindings/interconnect/qcom,msm8998-bwmon.yaml
+++ b/Documentation/devicetree/bindings/interconnect/qcom,msm8998-bwmon.yaml
@@ -41,6 +41,7 @@ properties:
               - qcom,sm6115-cpu-bwmon
               - qcom,sm6350-llcc-bwmon
               - qcom,sm8250-cpu-bwmon
+              - qcom,sm8350-cpu-bwmon
               - qcom,sm8550-cpu-bwmon
               - qcom,sm8650-cpu-bwmon
               - qcom,sm8750-cpu-bwmon
@@ -59,6 +60,7 @@ properties:
               - qcom,shikra-cpu-bwmon
               - qcom,sm6350-cpu-bwmon
               - qcom,sm8250-llcc-bwmon
+              - qcom,sm8350-llcc-bwmon
               - qcom,sm8550-llcc-bwmon
               - qcom,sm8650-llcc-bwmon
               - qcom,x1e80100-llcc-bwmon

-- 
2.53.0

[PATCH 2/2] arm64: dts: qcom: sm8350: Add CPU and LLCC BWMON

[Demeter Barna via B4 Relay]

From: Demeter Barna <me@fromdisposition.org>

Add the CPU-to-LLCC and LLCC-to-DDR bandwidth monitors, so that the
interconnect votes follow the measured memory traffic.

The levels are those of the downstream llcc-bw-opp-table and
ddr-bw-opp-table. Downstream limits two DDR levels (5161 and 8136 MB/s)
to LPDDR4X; leave them out, as was done for SM8250.

Assisted-by: LLM
Signed-off-by: Demeter Barna <me@fromdisposition.org>
---
 arch/arm64/boot/dts/qcom/sm8350.dtsi | 100 +++++++++++++++++++++++++++++++++++
 1 file changed, 100 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi
index 55b32050ce9c..6335c7809d17 100644
--- a/arch/arm64/boot/dts/qcom/sm8350.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi
@@ -2476,6 +2476,106 @@ usb_2_qmpphy: phy@88eb000 {
 				      "phy_phy";
 		};
 
+		pmu@9091000 {
+			compatible = "qcom,sm8350-llcc-bwmon", "qcom,sc7280-llcc-bwmon";
+			reg = <0 0x09091000 0 0x1000>;
+			interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
+			interconnects = <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY
+					 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>;
+
+			operating-points-v2 = <&llcc_bwmon_opp_table>;
+
+			llcc_bwmon_opp_table: opp-table {
+				compatible = "operating-points-v2";
+
+				opp-0 {
+					opp-peak-kBps = <762000>;
+				};
+
+				opp-1 {
+					opp-peak-kBps = <1720000>;
+				};
+
+				opp-2 {
+					opp-peak-kBps = <2086000>;
+				};
+
+				opp-3 {
+					opp-peak-kBps = <2597000>;
+				};
+
+				opp-4 {
+					opp-peak-kBps = <2929000>;
+				};
+
+				opp-5 {
+					opp-peak-kBps = <3879000>;
+				};
+
+				opp-6 {
+					opp-peak-kBps = <5931000>;
+				};
+
+				opp-7 {
+					opp-peak-kBps = <6515000>;
+				};
+
+				opp-8 {
+					opp-peak-kBps = <7980000>;
+				};
+
+				opp-9 {
+					opp-peak-kBps = <10437000>;
+				};
+
+				opp-10 {
+					opp-peak-kBps = <12191000>;
+				};
+			};
+		};
+
+		pmu@90b6400 {
+			compatible = "qcom,sm8350-cpu-bwmon", "qcom,sdm845-bwmon";
+			reg = <0 0x090b6400 0 0x600>;
+			interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>;
+			interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+					 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>;
+
+			operating-points-v2 = <&cpu_bwmon_opp_table>;
+
+			cpu_bwmon_opp_table: opp-table {
+				compatible = "operating-points-v2";
+
+				opp-0 {
+					opp-peak-kBps = <2288000>;
+				};
+
+				opp-1 {
+					opp-peak-kBps = <4577000>;
+				};
+
+				opp-2 {
+					opp-peak-kBps = <7110000>;
+				};
+
+				opp-3 {
+					opp-peak-kBps = <9155000>;
+				};
+
+				opp-4 {
+					opp-peak-kBps = <12298000>;
+				};
+
+				opp-5 {
+					opp-peak-kBps = <14236000>;
+				};
+
+				opp-6 {
+					opp-peak-kBps = <15258000>;
+				};
+			};
+		};
+
 		dc_noc: interconnect@90c0000 {
 			compatible = "qcom,sm8350-dc-noc";
 			reg = <0 0x090c0000 0 0x4200>;

-- 
2.53.0

Re: [PATCH 2/2] arm64: dts: qcom: sm8350: Add CPU and LLCC BWMON

[Konrad Dybcio]

On 10/16/26 8:13 AM, Demeter Barna via B4 Relay wrote:
> From: Demeter Barna <me@fromdisposition.org>
> 
> Add the CPU-to-LLCC and LLCC-to-DDR bandwidth monitors, so that the
> interconnect votes follow the measured memory traffic.
> 
> The levels are those of the downstream llcc-bw-opp-table and
> ddr-bw-opp-table. Downstream limits two DDR levels (5161 and 8136 MB/s)
> to LPDDR4X; leave them out, as was done for SM8250.
> 
> Assisted-by: LLM
> Signed-off-by: Demeter Barna <me@fromdisposition.org>
> ---

Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>

Konrad