From: Kishon Vijay Abraham I <kishon@ti.com>
To: Swapnil Jakhade <sjakhade@cadence.com>, <vkoul@kernel.org>,
<p.zabel@pengutronix.de>, <linux-phy@lists.infradead.org>,
<linux-kernel@vger.kernel.org>
Cc: <mparab@cadence.com>, <lokeshvutla@ti.com>
Subject: Re: [PATCH 10/14] phy: cadence-torrent: Add function to get PLL to be configured for DP
Date: Thu, 13 May 2021 12:42:55 +0530 [thread overview]
Message-ID: <b5e1cf48-7a19-4f5e-8530-e28e98a16e6a@ti.com> (raw)
In-Reply-To: <1617946456-27773-11-git-send-email-sjakhade@cadence.com>
Hi Swapnil,
On 09/04/21 11:04 am, Swapnil Jakhade wrote:
> Torrent PHY PLL0 or PLL1 is used for DP depending on the single link or
> multilink protocol configuration for which PHY is configured. In multilink
> configurations with other protocols, either PLL0 or PLL1 will be used
> for DP. For single link DP, both PLLs need to be configured at POR.
>
> Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com>
> ---
> drivers/phy/cadence/phy-cadence-torrent.c | 32 +++++++++++++++++++++++
> 1 file changed, 32 insertions(+)
>
> diff --git a/drivers/phy/cadence/phy-cadence-torrent.c b/drivers/phy/cadence/phy-cadence-torrent.c
> index e4dd8d1711a6..44e28ea8ffa7 100644
> --- a/drivers/phy/cadence/phy-cadence-torrent.c
> +++ b/drivers/phy/cadence/phy-cadence-torrent.c
> @@ -288,6 +288,11 @@ enum cdns_torrent_ssc_mode {
> INTERNAL_SSC
> };
>
> +enum cdns_torrent_dp_pll {
> + DP_PLL0 = 0x1,
> + DP_PLL1 = 0x2
Using BIT() macro might be better since you are using this as bitfield.
> +};
> +
> struct cdns_torrent_inst {
> struct phy *phy;
> u32 mlane;
> @@ -301,6 +306,7 @@ struct cdns_torrent_phy {
> void __iomem *base; /* DPTX registers base */
> void __iomem *sd_base; /* SD0801 registers base */
> u32 max_bit_rate; /* Maximum link bit rate to use (in Mbps) */
> + u32 dp_pll;
enum cdns_torrent_dp_pll?
Thanks
Kishon
> struct reset_control *phy_rst;
> struct reset_control *apb_rst;
> struct device *dev;
> @@ -900,6 +906,30 @@ void cdns_torrent_dp_pma_cmn_vco_cfg_100mhz(struct cdns_torrent_phy *cdns_phy,
> }
> }
>
> +/* Set PLL used for DP configuration */
> +static int cdns_torrent_dp_get_pll(struct cdns_torrent_phy *cdns_phy,
> + enum cdns_torrent_phy_type phy_t2)
> +{
> + switch (phy_t2) {
> + case TYPE_PCIE:
> + case TYPE_USB:
> + cdns_phy->dp_pll = DP_PLL1;
> + break;
> + case TYPE_SGMII:
> + case TYPE_QSGMII:
> + cdns_phy->dp_pll = DP_PLL0;
> + break;
> + case TYPE_NONE:
> + cdns_phy->dp_pll = DP_PLL0 | DP_PLL1;
> + break;
> + default:
> + dev_err(cdns_phy->dev, "Unsupported PHY configuration\n");
> + return -EINVAL;
> + }
> +
> + return 0;
> +}
> +
> /*
> * Enable or disable PLL for selected lanes.
> */
> @@ -1554,6 +1584,8 @@ static int cdns_torrent_dp_init(struct phy *phy)
> return -EINVAL;
> }
>
> + cdns_torrent_dp_get_pll(cdns_phy, TYPE_NONE);
> +
> cdns_torrent_dp_common_init(cdns_phy, inst);
>
> return cdns_torrent_dp_start(cdns_phy, inst, phy);
>
next prev parent reply other threads:[~2021-05-13 7:13 UTC|newest]
Thread overview: 27+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-04-09 5:34 [PATCH 00/14] PHY: Add multilink DP support in Cadence Torrent PHY driver Swapnil Jakhade
2021-04-09 5:34 ` [PATCH 01/14] phy: cadence-torrent: Remove use of CamelCase to fix checkpatch CHECK message Swapnil Jakhade
2021-05-13 6:35 ` Kishon Vijay Abraham I
2021-04-09 5:34 ` [PATCH 02/14] phy: cadence-torrent: Reorder few functions to remove function declarations Swapnil Jakhade
2021-05-13 6:37 ` Kishon Vijay Abraham I
2021-04-09 5:34 ` [PATCH 03/14] phy: cadence-torrent: Add enum to support different input reference clocks Swapnil Jakhade
2021-05-13 6:43 ` Kishon Vijay Abraham I
2021-04-09 5:34 ` [PATCH 04/14] phy: cadence-torrent: Select register configuration based on PHY reference clock Swapnil Jakhade
2021-05-13 6:48 ` Kishon Vijay Abraham I
2021-04-09 5:34 ` [PATCH 05/14] phy: cadence-torrent: Add PHY registers for DP in array format Swapnil Jakhade
2021-05-13 6:52 ` Kishon Vijay Abraham I
2021-04-09 5:34 ` [PATCH 06/14] phy: cadence-torrent: Reorder functions to avoid function declarations Swapnil Jakhade
2021-04-09 5:34 ` [PATCH 07/14] " Swapnil Jakhade
2021-04-09 5:34 ` [PATCH 08/14] phy: cadence-torrent: Add PHY configuration for DP with 100MHz ref clock Swapnil Jakhade
2021-05-13 6:59 ` Kishon Vijay Abraham I
2021-04-09 5:34 ` [PATCH 09/14] phy: cadence-torrent: Add separate functions for reusable code Swapnil Jakhade
2021-05-13 7:00 ` Kishon Vijay Abraham I
2021-04-09 5:34 ` [PATCH 10/14] phy: cadence-torrent: Add function to get PLL to be configured for DP Swapnil Jakhade
2021-05-13 7:12 ` Kishon Vijay Abraham I [this message]
2021-04-09 5:34 ` [PATCH 11/14] phy: cadence-torrent: Add multilink DP support Swapnil Jakhade
2021-05-13 7:44 ` Kishon Vijay Abraham I
2021-04-09 5:34 ` [PATCH 12/14] phy: cadence-torrent: Add PCIe + DP multilink configuration Swapnil Jakhade
2021-05-13 7:47 ` Kishon Vijay Abraham I
2021-04-09 5:34 ` [PATCH 13/14] phy: cadence-torrent: Add debug information for PHY configuration Swapnil Jakhade
2021-05-13 7:54 ` Kishon Vijay Abraham I
2021-04-09 5:34 ` [PATCH 14/14] phy: cadence-torrent: Check PIPE mode PHY status to be ready for operation Swapnil Jakhade
2021-05-13 7:55 ` Kishon Vijay Abraham I
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