* [PATCH v2] arm64: dts: ti: Add k3-am62p-wakeup.dtsi for AM62PX efuse GP_SW1
@ 2026-09-22 16:57 Judith Mendez
2026-10-05 15:44 ` Moteen Shah
0 siblings, 1 reply; 3+ messages in thread
From: Judith Mendez @ 2026-09-22 16:57 UTC (permalink / raw)
To: Judith Mendez, Nishanth Menon
Cc: Vignesh Raghavendra, Tero Kristo, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, linux-arm-kernel, devicetree,
linux-kernel, Moteen Shah
Create k3-am62p-wakeup.dtsi which includes AM62P-specific WAKEUP
domain nodes.
In k3-am62p-wakeup.dtsi, add the efuse node for GP_SW1 register at
offset 0x230. GP_SW1 will be used to determine AM62P silicon revision.
Signed-off-by: Judith Mendez <jm@ti.com>
---
This patch adds GP_SW1 efuse node for AM62PX only now that bindings [0]
are in place.
Changes since v1:
- Move gpsw_efuse from k3-am62p-j722s-common-wakeup.dtsi to the new
k3-am62p-wakeup.dtsi [1] since GP_SW efuse registers are marked
reserved for J722S.
[0] https://lore.kernel.org/all/178942274041.683176.599438200260103620.b4-ty@kernel.org/
[1] https://lore.kernel.org/all/5d4742fa-e26a-4b49-8eb4-b6291c402334@ti.com/#t
Link to v1:
https://lore.kernel.org/all/20260915001304.3781247-1-jm@ti.com/
---
arch/arm64/boot/dts/ti/k3-am62p-wakeup.dtsi | 25 +++++++++++++++++++++
arch/arm64/boot/dts/ti/k3-am62p.dtsi | 1 +
2 files changed, 26 insertions(+)
create mode 100644 arch/arm64/boot/dts/ti/k3-am62p-wakeup.dtsi
diff --git a/arch/arm64/boot/dts/ti/k3-am62p-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-am62p-wakeup.dtsi
new file mode 100644
index 0000000000000..c56fb3890c983
--- /dev/null
+++ b/arch/arm64/boot/dts/ti/k3-am62p-wakeup.dtsi
@@ -0,0 +1,25 @@
+// SPDX-License-Identifier: GPL-2.0-only OR MIT
+/*
+ * Device Tree file for the AM62P WAKEUP domain peripherals
+ *
+ * Copyright (C) 2026 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+&wkup_conf {
+ gpsw_efuse: efuse@230 {
+ compatible = "ti,am62p-efuse", "socionext,uniphier-efuse";
+ reg = <0x230 0x10>;
+ #address-cells = <1>;
+ bootph-all;
+ #size-cells = <1>;
+
+ gpsw1: gpsw1@4 {
+ reg = <0x4 0x4>;
+ };
+ };
+};
+
+&chipid {
+ nvmem-cells = <&gpsw1>;
+ nvmem-cell-names = "gpsw1";
+};
diff --git a/arch/arm64/boot/dts/ti/k3-am62p.dtsi b/arch/arm64/boot/dts/ti/k3-am62p.dtsi
index 9d6266d6ddb82..058f264ee0646 100644
--- a/arch/arm64/boot/dts/ti/k3-am62p.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am62p.dtsi
@@ -154,3 +154,4 @@ cbass_wakeup: bus@b00000 {
/* Include AM62P specific peripherals */
#include "k3-am62p-main.dtsi"
+#include "k3-am62p-wakeup.dtsi"
--
2.34.1
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [PATCH v2] arm64: dts: ti: Add k3-am62p-wakeup.dtsi for AM62PX efuse GP_SW1
2026-09-22 16:57 [PATCH v2] arm64: dts: ti: Add k3-am62p-wakeup.dtsi for AM62PX efuse GP_SW1 Judith Mendez
@ 2026-10-05 15:44 ` Moteen Shah
2026-10-05 22:33 ` Judith Mendez
0 siblings, 1 reply; 3+ messages in thread
From: Moteen Shah @ 2026-10-05 15:44 UTC (permalink / raw)
To: Judith Mendez, Nishanth Menon
Cc: Vignesh Raghavendra, Tero Kristo, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, linux-arm-kernel, devicetree,
linux-kernel
Hey Judith,
Thanks for the patch.
On 22/09/26 22:27, Judith Mendez wrote:
> Create k3-am62p-wakeup.dtsi which includes AM62P-specific WAKEUP
> domain nodes.
>
> In k3-am62p-wakeup.dtsi, add the efuse node for GP_SW1 register at
> offset 0x230. GP_SW1 will be used to determine AM62P silicon revision.
Nit: Isn't GP_SW1 0x230 + offset? might need fixing of the msg.
>
> Signed-off-by: Judith Mendez <jm@ti.com>
> ---
> This patch adds GP_SW1 efuse node for AM62PX only now that bindings [0]
> are in place.
>
> Changes since v1:
> - Move gpsw_efuse from k3-am62p-j722s-common-wakeup.dtsi to the new
> k3-am62p-wakeup.dtsi [1] since GP_SW efuse registers are marked
> reserved for J722S.
>
> [0] https://lore.kernel.org/all/178942274041.683176.599438200260103620.b4-ty@kernel.org/
> [1] https://lore.kernel.org/all/5d4742fa-e26a-4b49-8eb4-b6291c402334@ti.com/#t
>
> Link to v1:
> https://lore.kernel.org/all/20260915001304.3781247-1-jm@ti.com/
> ---
> arch/arm64/boot/dts/ti/k3-am62p-wakeup.dtsi | 25 +++++++++++++++++++++
> arch/arm64/boot/dts/ti/k3-am62p.dtsi | 1 +
> 2 files changed, 26 insertions(+)
> create mode 100644 arch/arm64/boot/dts/ti/k3-am62p-wakeup.dtsi
>
> diff --git a/arch/arm64/boot/dts/ti/k3-am62p-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-am62p-wakeup.dtsi
> new file mode 100644
> index 0000000000000..c56fb3890c983
> --- /dev/null
> +++ b/arch/arm64/boot/dts/ti/k3-am62p-wakeup.dtsi
> @@ -0,0 +1,25 @@
> +// SPDX-License-Identifier: GPL-2.0-only OR MIT
> +/*
> + * Device Tree file for the AM62P WAKEUP domain peripherals
> + *
> + * Copyright (C) 2026 Texas Instruments Incorporated - https://www.ti.com/
> + */
> +
> +&wkup_conf {
> + gpsw_efuse: efuse@230 {
> + compatible = "ti,am62p-efuse", "socionext,uniphier-efuse";
> + reg = <0x230 0x10>;
> + #address-cells = <1>;
> + bootph-all;
Nit: I think the property ordering for bootph-all doesn't look correct.
With the above two changes, if valid.
Reviewed-by: Moteen Shah <m-shah@ti.com>
Regards,
Moteen
> + #size-cells = <1>;
> +
> + gpsw1: gpsw1@4 {
> + reg = <0x4 0x4>;
> + };
> + };
> +};
> +
> +&chipid {
> + nvmem-cells = <&gpsw1>;
> + nvmem-cell-names = "gpsw1";
> +};
> diff --git a/arch/arm64/boot/dts/ti/k3-am62p.dtsi b/arch/arm64/boot/dts/ti/k3-am62p.dtsi
> index 9d6266d6ddb82..058f264ee0646 100644
> --- a/arch/arm64/boot/dts/ti/k3-am62p.dtsi
> +++ b/arch/arm64/boot/dts/ti/k3-am62p.dtsi
> @@ -154,3 +154,4 @@ cbass_wakeup: bus@b00000 {
>
> /* Include AM62P specific peripherals */
> #include "k3-am62p-main.dtsi"
> +#include "k3-am62p-wakeup.dtsi"
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [PATCH v2] arm64: dts: ti: Add k3-am62p-wakeup.dtsi for AM62PX efuse GP_SW1
2026-10-05 15:44 ` Moteen Shah
@ 2026-10-05 22:33 ` Judith Mendez
0 siblings, 0 replies; 3+ messages in thread
From: Judith Mendez @ 2026-10-05 22:33 UTC (permalink / raw)
To: Moteen Shah, Nishanth Menon, Vignesh Raghavendra
Cc: Tero Kristo, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
linux-arm-kernel, devicetree, linux-kernel
Hi Moteen,
On 10/5/26 10:44 AM, Moteen Shah wrote:
> Hey Judith,
> Thanks for the patch.
>
> On 22/09/26 22:27, Judith Mendez wrote:
>> Create k3-am62p-wakeup.dtsi which includes AM62P-specific WAKEUP
>> domain nodes.
>>
>> In k3-am62p-wakeup.dtsi, add the efuse node for GP_SW1 register at
>> offset 0x230. GP_SW1 will be used to determine AM62P silicon revision.
>
>
> Nit: Isn't GP_SW1 0x230 + offset? might need fixing of the msg.
>
>>
>> Signed-off-by: Judith Mendez <jm@ti.com>
>> ---
>> This patch adds GP_SW1 efuse node for AM62PX only now that bindings [0]
>> are in place.
>>
>> Changes since v1:
>> - Move gpsw_efuse from k3-am62p-j722s-common-wakeup.dtsi to the new
>> k3-am62p-wakeup.dtsi [1] since GP_SW efuse registers are marked
>> reserved for J722S.
>>
>> [0] https://lore.kernel.org/
>> all/178942274041.683176.599438200260103620.b4-ty@kernel.org/
>> [1] https://lore.kernel.org/all/5d4742fa-e26a-4b49-8eb4-
>> b6291c402334@ti.com/#t
>>
>> Link to v1:
>> https://lore.kernel.org/all/20260915001304.3781247-1-jm@ti.com/
>> ---
>> arch/arm64/boot/dts/ti/k3-am62p-wakeup.dtsi | 25 +++++++++++++++++++++
>> arch/arm64/boot/dts/ti/k3-am62p.dtsi | 1 +
>> 2 files changed, 26 insertions(+)
>> create mode 100644 arch/arm64/boot/dts/ti/k3-am62p-wakeup.dtsi
>>
>> diff --git a/arch/arm64/boot/dts/ti/k3-am62p-wakeup.dtsi b/arch/arm64/
>> boot/dts/ti/k3-am62p-wakeup.dtsi
>> new file mode 100644
>> index 0000000000000..c56fb3890c983
>> --- /dev/null
>> +++ b/arch/arm64/boot/dts/ti/k3-am62p-wakeup.dtsi
>> @@ -0,0 +1,25 @@
>> +// SPDX-License-Identifier: GPL-2.0-only OR MIT
>> +/*
>> + * Device Tree file for the AM62P WAKEUP domain peripherals
>> + *
>> + * Copyright (C) 2026 Texas Instruments Incorporated - https://
>> www.ti.com/
>> + */
>> +
>> +&wkup_conf {
>> + gpsw_efuse: efuse@230 {
>> + compatible = "ti,am62p-efuse", "socionext,uniphier-efuse";
>> + reg = <0x230 0x10>;
>> + #address-cells = <1>;
>> + bootph-all;
>
>
> Nit: I think the property ordering for bootph-all doesn't look correct.
>
> With the above two changes, if valid.
I ran a DT checker, and it says to put it before size-cells and after
address cells. If I revert, I get these warnings:
+arch/arm64/boot/dts/ti/k3-am62p-wakeup.dtsi:13: [property-order]
property '#address-cells' out of canonical order (should sort before
'bootph-all')
So Ill leave as is for now, I will fix the commit message though.
Thanks for reviewing.
~ Judith
>
> Reviewed-by: Moteen Shah <m-shah@ti.com>
>
> Regards,
> Moteen
>
>> + #size-cells = <1>;
>> +
>> + gpsw1: gpsw1@4 {
>> + reg = <0x4 0x4>;
>> + };
>> + };
>> +};
>> +
>> +&chipid {
>> + nvmem-cells = <&gpsw1>;
>> + nvmem-cell-names = "gpsw1";
>> +};
>> diff --git a/arch/arm64/boot/dts/ti/k3-am62p.dtsi b/arch/arm64/boot/
>> dts/ti/k3-am62p.dtsi
>> index 9d6266d6ddb82..058f264ee0646 100644
>> --- a/arch/arm64/boot/dts/ti/k3-am62p.dtsi
>> +++ b/arch/arm64/boot/dts/ti/k3-am62p.dtsi
>> @@ -154,3 +154,4 @@ cbass_wakeup: bus@b00000 {
>> /* Include AM62P specific peripherals */
>> #include "k3-am62p-main.dtsi"
>> +#include "k3-am62p-wakeup.dtsi"
^ permalink raw reply [flat|nested] 3+ messages in thread
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2026-09-22 16:57 [PATCH v2] arm64: dts: ti: Add k3-am62p-wakeup.dtsi for AM62PX efuse GP_SW1 Judith Mendez
2026-10-05 15:44 ` Moteen Shah
2026-10-05 22:33 ` Judith Mendez
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