[PATCH net-next 0/2] net: stmmac: Add the Siflower SF19A2890 glue

[PATCH net-next 0/2] net: stmmac: Add the Siflower SF19A2890 glue

[Joseph Telaak via B4 Relay]

The Siflower SF19A2890, a MIPS SoC for home routers, has a DesignWare
GMAC 3.73a. Its interface type and RGMII clock delays are set in a
small configuration block next to its clock and reset manager. This
series adds a binding and the glue.

The glue is based on Chuanhong Guo's driver, which read the RGMII delays
from a factory flash cell in the delay line's own units and always
applied them. Here the delays come from rx-internal-delay-ps and
tx-internal-delay-ps and are applied only when those are present. The
interface type is set through set_phy_intf_sel.

The delay line's step is not documented, so I measured it: sweeping
each delay register over 0-255 with the link at 1000 Mb/s, the working
windows repeat every 145 steps (TX) and 144.5 steps (RX), which is one
8 ns period of the 125 MHz RGMII clock. So a step is about 55 ps. The
TX eye is about 3.1 ns wide and the RX eye about 1.75 ns; the delays the
bootloader programs, 17 and 10 steps (935 and 550 ps), sit inside both.

On the GL.iNet GL-SFT1200 the GMAC is the CPU port of a MaxLinear GSW150
switch over RGMII with no delays on the board; the GMAC adds both.

The MAINTAINERS entry that covers these files comes with the MIPS series
"MIPS: Add support for the Siflower SF19A2890"; this series applies on
its own. That entry is also why checkpatch's question about updating
MAINTAINERS for the new files is left unanswered here.

Tested on a GL-SFT1200 with the GSW150 driver:
- each of WAN, LAN 1 and LAN 2 links at 1000 Mb/s full duplex and
  passes iperf3 both ways (160-205 Mb/s out, 262-273 Mb/s in, well
  under line rate; I have not looked into where the limit is);
- 10 GB each way through LAN 1, after which every CRC, alignment,
  error, drop, overflow and underflow counter on eth0 and lan1 is 0;
- 50 link down/up cycles, after which the link and traffic recover;
- the MAC address from the factory partition, and ethtool reporting the
  link with no PCS workaround.

---
Joseph Telaak (2):
      dt-bindings: net: Add Siflower SF19A2890 GMAC
      net: stmmac: Add Siflower SF19A2890 glue

 .../bindings/net/siflower,sf19a2890-gmac.yaml      | 110 ++++++++++++++
 .../devicetree/bindings/net/snps,dwmac.yaml        |   1 +
 drivers/net/ethernet/stmicro/stmmac/Kconfig        |  11 ++
 drivers/net/ethernet/stmicro/stmmac/Makefile       |   1 +
 .../net/ethernet/stmicro/stmmac/dwmac-sf19a2890.c  | 158 +++++++++++++++++++++
 5 files changed, 281 insertions(+)
---
base-commit: 7b6ab4dbc156e2f96419715130b3d5738a306c93
change-id: 20261102-sf19a2890-gmac-4fb4808f869c

Best regards,
--  
Joseph Telaak <joseph@telaak.dev>

[PATCH net-next 1/2] dt-bindings: net: Add Siflower SF19A2890 GMAC

[Joseph Telaak via B4 Relay]

From: Joseph Telaak <joseph@telaak.dev>

The Siflower SF19A2890 has a DesignWare GMAC 3.73a whose interface
type and RGMII clock delays are set in a configuration block of their
own, next to its clock and reset manager. It takes a fourth clock, the
RGMII transmit reference.

Signed-off-by: Joseph Telaak <joseph@telaak.dev>
---
 .../bindings/net/siflower,sf19a2890-gmac.yaml      | 110 +++++++++++++++++++++
 .../devicetree/bindings/net/snps,dwmac.yaml        |   1 +
 2 files changed, 111 insertions(+)

diff --git a/Documentation/devicetree/bindings/net/siflower,sf19a2890-gmac.yaml b/Documentation/devicetree/bindings/net/siflower,sf19a2890-gmac.yaml
new file mode 100644
index 000000000..377f24a65
--- /dev/null
+++ b/Documentation/devicetree/bindings/net/siflower,sf19a2890-gmac.yaml
@@ -0,0 +1,110 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/net/siflower,sf19a2890-gmac.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Siflower SF19A2890 GMAC
+
+maintainers:
+  - Joseph Telaak <joseph@telaak.dev>
+
+description:
+  The Siflower SF19A2890 has a Synopsys DesignWare GMAC 3.73a. Its
+  interface type and RGMII clock delays are set in a configuration block
+  of their own. The MAC adds an RGMII delay only where the
+  rx-internal-delay-ps or tx-internal-delay-ps property says so.
+
+select:
+  properties:
+    compatible:
+      contains:
+        const: siflower,sf19a2890-gmac
+  required:
+    - compatible
+
+properties:
+  compatible:
+    items:
+      - const: siflower,sf19a2890-gmac
+      - const: snps,dwmac
+
+  reg:
+    items:
+      - description: MAC registers
+      - description: Interface configuration registers
+
+  interrupts:
+    maxItems: 3
+
+  interrupt-names:
+    items:
+      - const: macirq
+      - const: eth_wake_irq
+      - const: eth_lpi
+
+  clocks:
+    items:
+      - description: GMAC main clock
+      - description: Peripheral registers interface clock
+      - description: PTP reference clock
+      - description: RGMII transmit reference clock
+
+  clock-names:
+    items:
+      - const: stmmaceth
+      - const: pclk
+      - const: ptp_ref
+      - const: byp_ref
+
+  rx-internal-delay-ps:
+    description:
+      Applied in steps of about 55 ps, rounded to the nearest step.
+    maximum: 14025
+
+  tx-internal-delay-ps:
+    description:
+      Applied in steps of about 55 ps, rounded to the nearest step.
+    maximum: 14025
+
+required:
+  - compatible
+  - reg
+  - interrupts
+  - interrupt-names
+  - clocks
+  - clock-names
+  - resets
+  - reset-names
+
+allOf:
+  - $ref: snps,dwmac.yaml#
+
+unevaluatedProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/interrupt-controller/irq.h>
+    #include <dt-bindings/interrupt-controller/mips-gic.h>
+
+    ethernet@10800000 {
+        compatible = "siflower,sf19a2890-gmac", "snps,dwmac";
+        reg = <0x10800000 0x200000>, <0x19e04440 0x10>;
+        interrupt-parent = <&gic>;
+        interrupts = <GIC_SHARED 32 IRQ_TYPE_LEVEL_HIGH>,
+                     <GIC_SHARED 34 IRQ_TYPE_LEVEL_HIGH>,
+                     <GIC_SHARED 33 IRQ_TYPE_LEVEL_HIGH>;
+        interrupt-names = "macirq", "eth_wake_irq", "eth_lpi";
+        clocks = <&gmac_crm 0>, <&gmac_crm 1>, <&gmac_crm 3>, <&gmac_crm 2>;
+        clock-names = "stmmaceth", "pclk", "ptp_ref", "byp_ref";
+        resets = <&gmac_crm 0>;
+        reset-names = "stmmaceth";
+        phy-mode = "rgmii-id";
+        rx-internal-delay-ps = <550>;
+        tx-internal-delay-ps = <935>;
+
+        fixed-link {
+            speed = <1000>;
+            full-duplex;
+        };
+    };
diff --git a/Documentation/devicetree/bindings/net/snps,dwmac.yaml b/Documentation/devicetree/bindings/net/snps,dwmac.yaml
index 2c4842404..c3d96d58a 100644
--- a/Documentation/devicetree/bindings/net/snps,dwmac.yaml
+++ b/Documentation/devicetree/bindings/net/snps,dwmac.yaml
@@ -98,6 +98,7 @@ properties:
         - rockchip,rk3588-gmac
         - rockchip,rv1108-gmac
         - rockchip,rv1126-gmac
+        - siflower,sf19a2890-gmac
         - snps,dwmac
         - snps,dwmac-3.40a
         - snps,dwmac-3.50a

-- 
Git-155)

Re: [PATCH net-next 1/2] dt-bindings: net: Add Siflower SF19A2890 GMAC

[Andrew Lunn]

> +  rx-internal-delay-ps:
> +    description:
> +      Applied in steps of about 55 ps, rounded to the nearest step.
> +    maximum: 14025

Please add minimum, and multipleOf.

I've not looked at the code yet, but default: 0 would also be good.

> +        rx-internal-delay-ps = <550>;
> +        tx-internal-delay-ps = <935>;

These values are odd. The RGMII standard says 2ns is required. Where
is the rest coming from.

> +        fixed-link {
> +            speed = <1000>;
> +            full-duplex;
> +        };

Does this mean there is a switch on the other end? Maybe look at what
the switch is doing for RGMII delays.

	Andrew

Re: [PATCH net-next 1/2] dt-bindings: net: Add Siflower SF19A2890 GMAC

[Joseph Telaak]

> Please add minimum, and multipleOf.
>
> I've not looked at the code yet, but default: 0 would also be good.

Will do: minimum 0, multipleOf 55 and default 0.

> These values are odd. The RGMII standard says 2ns is required. Where
> is the rest coming from.

They are the values the vendor bootloader programs, and I checked them
against the hardware. Sweeping each delay over its 256 steps at
1000 Mb/s, TX works from 0 to about 2.8 ns and RX from 0 to about
1.5 ns; 935 and 550 ps sit inside both windows, and a 2 ns RX delay in
the MAC fails.

The rest of the skew is not programmed anywhere: the switch's PCDU
register for this port reads back 0, and with the MAC's delays at 0 as
well the link still passes traffic. So it comes from the board routing
or the chips themselves, which I can't separate from software.

If you'd rather see this described another way in the DT, I'm happy to
change it for v2.

> Does this mean there is a switch on the other end? Maybe look at what
> the switch is doing for RGMII delays.

Yes, a MaxLinear GSW150 on its CPU port, with phy-mode "rgmii-id" and no
*-internal-delay-ps. As above, its delays read back as 0.

Re: [PATCH net-next 1/2] dt-bindings: net: Add Siflower SF19A2890 GMAC

[Joseph Telaak]

> They are the values the vendor bootloader programs, and I checked them
> against the hardware.

Correction: they are the board's factory calibration, stored in its
factory partition as 17 and 10 steps; the vendor bootloader leaves 23
steps in both, also inside the measured windows. The rest stands.

[PATCH net-next 2/2] net: stmmac: Add Siflower SF19A2890 glue

[Joseph Telaak via B4 Relay]

From: Joseph Telaak <joseph@telaak.dev>

Add the glue for the DesignWare GMAC of the Siflower SF19A2890. The
interface type is set in the GMAC's configuration block through the
set_phy_intf_sel hook, and so are the RGMII clock delays, which the
MAC adds only where rx-internal-delay-ps or tx-internal-delay-ps is
present.

The delay line's step is not documented. Sweeping each delay over its
whole range with the link at 1000 Mb/s, the working windows repeat every
145 steps, one 8 ns clock period, so a step is about 55 ps; the driver
rounds to the nearest step.

Based on Chuanhong Guo's driver from OpenWrt and his siflower-7.1
branch, which read the delays from a factory flash cell in the delay
line's own units and always applied them. That driver also set
STMMAC_FLAG_HAS_INTEGRATED_PCS, because the core reports a PCS that
does not work in RGMII mode; stmmac now uses the integrated PCS only
for SGMII, and the flag is gone.

Signed-off-by: Joseph Telaak <joseph@telaak.dev>
---
 drivers/net/ethernet/stmicro/stmmac/Kconfig        |  11 ++
 drivers/net/ethernet/stmicro/stmmac/Makefile       |   1 +
 .../net/ethernet/stmicro/stmmac/dwmac-sf19a2890.c  | 158 +++++++++++++++++++++
 3 files changed, 170 insertions(+)

diff --git a/drivers/net/ethernet/stmicro/stmmac/Kconfig b/drivers/net/ethernet/stmicro/stmmac/Kconfig
index c6559e749..78efe7859 100644
--- a/drivers/net/ethernet/stmicro/stmmac/Kconfig
+++ b/drivers/net/ethernet/stmicro/stmmac/Kconfig
@@ -201,6 +201,17 @@ config DWMAC_S32
 	  SOCs GMAC ethernet controller, ie. S32G2xx, S32G3xx and
 	  S32R45.
 
+config DWMAC_SF19A2890
+	tristate "Siflower SF19A2890 GMAC support"
+	default MACH_SIFLOWER_MIPS
+	depends on OF && (MACH_SIFLOWER_MIPS || COMPILE_TEST)
+	help
+	  Support for the Ethernet controller of the Siflower SF19A2890 SoC.
+
+	  This selects the SF19A2890 glue layer support for the stmmac
+	  device driver. It sets the interface type and the RGMII clock
+	  delays in the GMAC's configuration block.
+
 config DWMAC_SOCFPGA
 	tristate "SOCFPGA dwmac support"
 	default ARCH_INTEL_SOCFPGA
diff --git a/drivers/net/ethernet/stmicro/stmmac/Makefile b/drivers/net/ethernet/stmicro/stmmac/Makefile
index b16a456b7..9330de094 100644
--- a/drivers/net/ethernet/stmicro/stmmac/Makefile
+++ b/drivers/net/ethernet/stmicro/stmmac/Makefile
@@ -26,6 +26,7 @@ obj-$(CONFIG_DWMAC_RENESAS_GBETH) += dwmac-renesas-gbeth.o
 obj-$(CONFIG_DWMAC_ROCKCHIP)	+= dwmac-rk.o
 obj-$(CONFIG_DWMAC_RZN1)	+= dwmac-rzn1.o
 obj-$(CONFIG_DWMAC_S32)		+= dwmac-s32.o
+obj-$(CONFIG_DWMAC_SF19A2890)	+= dwmac-sf19a2890.o
 obj-$(CONFIG_DWMAC_SOCFPGA)	+= dwmac-altr-socfpga.o
 obj-$(CONFIG_DWMAC_SOPHGO)	+= dwmac-sophgo.o
 obj-$(CONFIG_DWMAC_SPACEMIT)	+= dwmac-spacemit.o
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-sf19a2890.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-sf19a2890.c
new file mode 100644
index 000000000..41bfe7a4a
--- /dev/null
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-sf19a2890.c
@@ -0,0 +1,158 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Siflower SF19A2890 GMAC glue
+ *
+ * The SF19A2890 has a DWMAC 3.73a. Its interface type and RGMII clock
+ * delays are set in a register block of their own.
+ *
+ * Based on the driver by Chuanhong Guo <gch981213@gmail.com>.
+ */
+
+#include <linux/bitfield.h>
+#include <linux/clk.h>
+#include <linux/io.h>
+#include <linux/math.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+#include <linux/stmmac.h>
+
+#include "stmmac_platform.h"
+
+/* GMAC configuration block */
+#define SF19A2890_GMAC_MISC		0x0
+#define  SF19A2890_PHY_INTF_SEL		GENMASK(2, 0)
+#define SF19A2890_GMAC_TX_DELAY		0x4
+#define SF19A2890_GMAC_RX_DELAY		0x8
+#define SF19A2890_GMAC_RX_DELAY_EN	0xc
+#define  SF19A2890_DELAY_MAX		0xff
+
+/*
+ * The delay line's step is not documented. Sweeping a full 8 ns RGMII clock
+ * period at 1000 Mb/s takes 145 steps, so one step is about 55 ps.
+ */
+#define SF19A2890_DELAY_STEP_PS		55
+
+struct sf19a2890_gmac {
+	struct device *dev;
+	void __iomem *cfg;
+};
+
+static int sf19a2890_gmac_set_phy_intf_sel(void *bsp_priv, u8 phy_intf_sel)
+{
+	struct sf19a2890_gmac *gmac = bsp_priv;
+	u32 val;
+
+	if (phy_intf_sel != PHY_INTF_SEL_GMII_MII &&
+	    phy_intf_sel != PHY_INTF_SEL_RGMII &&
+	    phy_intf_sel != PHY_INTF_SEL_RMII)
+		return -EINVAL;
+
+	val = readl(gmac->cfg + SF19A2890_GMAC_MISC);
+	val &= ~SF19A2890_PHY_INTF_SEL;
+	val |= FIELD_PREP(SF19A2890_PHY_INTF_SEL, phy_intf_sel);
+	writel(val, gmac->cfg + SF19A2890_GMAC_MISC);
+
+	return 0;
+}
+
+static int sf19a2890_gmac_get_delay(struct sf19a2890_gmac *gmac,
+				    const char *prop, u32 *steps)
+{
+	u32 ps;
+
+	*steps = 0;
+	if (of_property_read_u32(gmac->dev->of_node, prop, &ps))
+		return 0;
+
+	*steps = DIV_ROUND_CLOSEST(ps, SF19A2890_DELAY_STEP_PS);
+	if (*steps > SF19A2890_DELAY_MAX)
+		return dev_err_probe(gmac->dev, -EINVAL,
+				     "%s too large: %u\n", prop, ps);
+
+	return 0;
+}
+
+/* The MAC adds an RGMII delay only where the device tree asks for one */
+static int sf19a2890_gmac_set_delays(struct sf19a2890_gmac *gmac)
+{
+	u32 tx, rx;
+	int ret;
+
+	ret = sf19a2890_gmac_get_delay(gmac, "tx-internal-delay-ps", &tx);
+	if (ret)
+		return ret;
+
+	ret = sf19a2890_gmac_get_delay(gmac, "rx-internal-delay-ps", &rx);
+	if (ret)
+		return ret;
+
+	writel(tx, gmac->cfg + SF19A2890_GMAC_TX_DELAY);
+	writel(rx, gmac->cfg + SF19A2890_GMAC_RX_DELAY);
+	writel(!!rx, gmac->cfg + SF19A2890_GMAC_RX_DELAY_EN);
+
+	return 0;
+}
+
+static int sf19a2890_gmac_probe(struct platform_device *pdev)
+{
+	struct plat_stmmacenet_data *plat_dat;
+	struct stmmac_resources stmmac_res;
+	struct device *dev = &pdev->dev;
+	struct sf19a2890_gmac *gmac;
+	struct clk *clk;
+	int ret;
+
+	gmac = devm_kzalloc(dev, sizeof(*gmac), GFP_KERNEL);
+	if (!gmac)
+		return -ENOMEM;
+
+	gmac->dev = dev;
+
+	gmac->cfg = devm_platform_ioremap_resource(pdev, 1);
+	if (IS_ERR(gmac->cfg))
+		return dev_err_probe(dev, PTR_ERR(gmac->cfg),
+				     "failed to map the configuration block\n");
+
+	clk = devm_clk_get_enabled(dev, "byp_ref");
+	if (IS_ERR(clk))
+		return dev_err_probe(dev, PTR_ERR(clk),
+				     "failed to enable the byp_ref clock\n");
+
+	ret = sf19a2890_gmac_set_delays(gmac);
+	if (ret)
+		return ret;
+
+	ret = stmmac_get_platform_resources(pdev, &stmmac_res);
+	if (ret)
+		return ret;
+
+	plat_dat = devm_stmmac_probe_config_dt(pdev, stmmac_res.mac);
+	if (IS_ERR(plat_dat))
+		return PTR_ERR(plat_dat);
+
+	plat_dat->bsp_priv = gmac;
+	plat_dat->set_phy_intf_sel = sf19a2890_gmac_set_phy_intf_sel;
+
+	return stmmac_dvr_probe(dev, plat_dat, &stmmac_res);
+}
+
+static const struct of_device_id sf19a2890_gmac_match[] = {
+	{ .compatible = "siflower,sf19a2890-gmac" },
+	{ }
+};
+MODULE_DEVICE_TABLE(of, sf19a2890_gmac_match);
+
+static struct platform_driver sf19a2890_gmac_driver = {
+	.probe = sf19a2890_gmac_probe,
+	.remove = stmmac_pltfr_remove,
+	.driver = {
+		.name = "sf19a2890-gmac",
+		.pm = &stmmac_pltfr_pm_ops,
+		.of_match_table = sf19a2890_gmac_match,
+	},
+};
+module_platform_driver(sf19a2890_gmac_driver);
+
+MODULE_DESCRIPTION("Siflower SF19A2890 GMAC glue");
+MODULE_LICENSE("GPL");

-- 
Git-155)

Re: [PATCH net-next 2/2] net: stmmac: Add Siflower SF19A2890 glue

[Maxime Chevallier]

Hi Joseph,

On 11/4/26 08:22, Joseph Telaak via B4 Relay wrote:
> From: Joseph Telaak <joseph@telaak.dev>
> 
> Add the glue for the DesignWare GMAC of the Siflower SF19A2890. The
> interface type is set in the GMAC's configuration block through the
> set_phy_intf_sel hook, and so are the RGMII clock delays, which the
> MAC adds only where rx-internal-delay-ps or tx-internal-delay-ps is
> present.
> 
> The delay line's step is not documented. Sweeping each delay over its
> whole range with the link at 1000 Mb/s, the working windows repeat every
> 145 steps, one 8 ns clock period, so a step is about 55 ps; the driver
> rounds to the nearest step.
> 
> Based on Chuanhong Guo's driver from OpenWrt and his siflower-7.1
> branch, which read the delays from a factory flash cell in the delay
> line's own units and always applied them. That driver also set
> STMMAC_FLAG_HAS_INTEGRATED_PCS, because the core reports a PCS that
> does not work in RGMII mode; stmmac now uses the integrated PCS only
> for SGMII, and the flag is gone.
> 
> Signed-off-by: Joseph Telaak <joseph@telaak.dev>

Looking good, I have a small nit below :)

> ---
>  drivers/net/ethernet/stmicro/stmmac/Kconfig        |  11 ++
>  drivers/net/ethernet/stmicro/stmmac/Makefile       |   1 +
>  .../net/ethernet/stmicro/stmmac/dwmac-sf19a2890.c  | 158 +++++++++++++++++++++
>  3 files changed, 170 insertions(+)
> 
> diff --git a/drivers/net/ethernet/stmicro/stmmac/Kconfig b/drivers/net/ethernet/stmicro/stmmac/Kconfig
> index c6559e749..78efe7859 100644
> --- a/drivers/net/ethernet/stmicro/stmmac/Kconfig
> +++ b/drivers/net/ethernet/stmicro/stmmac/Kconfig
> @@ -201,6 +201,17 @@ config DWMAC_S32
>  	  SOCs GMAC ethernet controller, ie. S32G2xx, S32G3xx and
>  	  S32R45.
>  
> +config DWMAC_SF19A2890
> +	tristate "Siflower SF19A2890 GMAC support"
> +	default MACH_SIFLOWER_MIPS
> +	depends on OF && (MACH_SIFLOWER_MIPS || COMPILE_TEST)
> +	help
> +	  Support for the Ethernet controller of the Siflower SF19A2890 SoC.
> +
> +	  This selects the SF19A2890 glue layer support for the stmmac
> +	  device driver. It sets the interface type and the RGMII clock
> +	  delays in the GMAC's configuration block.
> +
>  config DWMAC_SOCFPGA
>  	tristate "SOCFPGA dwmac support"
>  	default ARCH_INTEL_SOCFPGA
> diff --git a/drivers/net/ethernet/stmicro/stmmac/Makefile b/drivers/net/ethernet/stmicro/stmmac/Makefile
> index b16a456b7..9330de094 100644
> --- a/drivers/net/ethernet/stmicro/stmmac/Makefile
> +++ b/drivers/net/ethernet/stmicro/stmmac/Makefile
> @@ -26,6 +26,7 @@ obj-$(CONFIG_DWMAC_RENESAS_GBETH) += dwmac-renesas-gbeth.o
>  obj-$(CONFIG_DWMAC_ROCKCHIP)	+= dwmac-rk.o
>  obj-$(CONFIG_DWMAC_RZN1)	+= dwmac-rzn1.o
>  obj-$(CONFIG_DWMAC_S32)		+= dwmac-s32.o
> +obj-$(CONFIG_DWMAC_SF19A2890)	+= dwmac-sf19a2890.o
>  obj-$(CONFIG_DWMAC_SOCFPGA)	+= dwmac-altr-socfpga.o
>  obj-$(CONFIG_DWMAC_SOPHGO)	+= dwmac-sophgo.o
>  obj-$(CONFIG_DWMAC_SPACEMIT)	+= dwmac-spacemit.o
> diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-sf19a2890.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-sf19a2890.c
> new file mode 100644
> index 000000000..41bfe7a4a
> --- /dev/null
> +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-sf19a2890.c
> @@ -0,0 +1,158 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * Siflower SF19A2890 GMAC glue
> + *
> + * The SF19A2890 has a DWMAC 3.73a. Its interface type and RGMII clock
> + * delays are set in a register block of their own.
> + *
> + * Based on the driver by Chuanhong Guo <gch981213@gmail.com>.
> + */
> +
> +#include <linux/bitfield.h>
> +#include <linux/clk.h>
> +#include <linux/io.h>
> +#include <linux/math.h>
> +#include <linux/module.h>
> +#include <linux/of.h>
> +#include <linux/platform_device.h>
> +#include <linux/stmmac.h>
> +
> +#include "stmmac_platform.h"
> +
> +/* GMAC configuration block */
> +#define SF19A2890_GMAC_MISC		0x0
> +#define  SF19A2890_PHY_INTF_SEL		GENMASK(2, 0)
> +#define SF19A2890_GMAC_TX_DELAY		0x4
> +#define SF19A2890_GMAC_RX_DELAY		0x8
> +#define SF19A2890_GMAC_RX_DELAY_EN	0xc
> +#define  SF19A2890_DELAY_MAX		0xff
> +
> +/*
> + * The delay line's step is not documented. Sweeping a full 8 ns RGMII clock
> + * period at 1000 Mb/s takes 145 steps, so one step is about 55 ps.
> + */
> +#define SF19A2890_DELAY_STEP_PS		55
> +
> +struct sf19a2890_gmac {
> +	struct device *dev;

This is only used during the probe sequence, you can simply pass it as
function parameters, this avoids using up memory to store that :)

> +	void __iomem *cfg;
> +};
> +
> +static int sf19a2890_gmac_set_phy_intf_sel(void *bsp_priv, u8 phy_intf_sel)
> +{
> +	struct sf19a2890_gmac *gmac = bsp_priv;
> +	u32 val;
> +
> +	if (phy_intf_sel != PHY_INTF_SEL_GMII_MII &&
> +	    phy_intf_sel != PHY_INTF_SEL_RGMII &&
> +	    phy_intf_sel != PHY_INTF_SEL_RMII)
> +		return -EINVAL;
> +
> +	val = readl(gmac->cfg + SF19A2890_GMAC_MISC);
> +	val &= ~SF19A2890_PHY_INTF_SEL;
> +	val |= FIELD_PREP(SF19A2890_PHY_INTF_SEL, phy_intf_sel);
> +	writel(val, gmac->cfg + SF19A2890_GMAC_MISC);
> +
> +	return 0;
> +}
> +
> +static int sf19a2890_gmac_get_delay(struct sf19a2890_gmac *gmac,
> +				    const char *prop, u32 *steps)
> +{
> +	u32 ps;
> +
> +	*steps = 0;
> +	if (of_property_read_u32(gmac->dev->of_node, prop, &ps))
> +		return 0;
> +
> +	*steps = DIV_ROUND_CLOSEST(ps, SF19A2890_DELAY_STEP_PS);
> +	if (*steps > SF19A2890_DELAY_MAX)
> +		return dev_err_probe(gmac->dev, -EINVAL,
> +				     "%s too large: %u\n", prop, ps);
> +
> +	return 0;
> +}
> +
> +/* The MAC adds an RGMII delay only where the device tree asks for one */
> +static int sf19a2890_gmac_set_delays(struct sf19a2890_gmac *gmac)
> +{
> +	u32 tx, rx;
> +	int ret;
> +
> +	ret = sf19a2890_gmac_get_delay(gmac, "tx-internal-delay-ps", &tx);
> +	if (ret)
> +		return ret;
> +
> +	ret = sf19a2890_gmac_get_delay(gmac, "rx-internal-delay-ps", &rx);
> +	if (ret)
> +		return ret;
> +
> +	writel(tx, gmac->cfg + SF19A2890_GMAC_TX_DELAY);
> +	writel(rx, gmac->cfg + SF19A2890_GMAC_RX_DELAY);
> +	writel(!!rx, gmac->cfg + SF19A2890_GMAC_RX_DELAY_EN);
> +
> +	return 0;
> +}
> +
> +static int sf19a2890_gmac_probe(struct platform_device *pdev)
> +{
> +	struct plat_stmmacenet_data *plat_dat;
> +	struct stmmac_resources stmmac_res;
> +	struct device *dev = &pdev->dev;
> +	struct sf19a2890_gmac *gmac;
> +	struct clk *clk;
> +	int ret;
> +
> +	gmac = devm_kzalloc(dev, sizeof(*gmac), GFP_KERNEL);
> +	if (!gmac)
> +		return -ENOMEM;
> +
> +	gmac->dev = dev;
> +
> +	gmac->cfg = devm_platform_ioremap_resource(pdev, 1);
> +	if (IS_ERR(gmac->cfg))
> +		return dev_err_probe(dev, PTR_ERR(gmac->cfg),
> +				     "failed to map the configuration block\n");
> +
> +	clk = devm_clk_get_enabled(dev, "byp_ref");
> +	if (IS_ERR(clk))
> +		return dev_err_probe(dev, PTR_ERR(clk),
> +				     "failed to enable the byp_ref clock\n");
> +
> +	ret = sf19a2890_gmac_set_delays(gmac);
> +	if (ret)
> +		return ret;
> +
> +	ret = stmmac_get_platform_resources(pdev, &stmmac_res);
> +	if (ret)
> +		return ret;
> +
> +	plat_dat = devm_stmmac_probe_config_dt(pdev, stmmac_res.mac);
> +	if (IS_ERR(plat_dat))
> +		return PTR_ERR(plat_dat);
> +
> +	plat_dat->bsp_priv = gmac;
> +	plat_dat->set_phy_intf_sel = sf19a2890_gmac_set_phy_intf_sel;
> +
> +	return stmmac_dvr_probe(dev, plat_dat, &stmmac_res);
> +}
> +
> +static const struct of_device_id sf19a2890_gmac_match[] = {
> +	{ .compatible = "siflower,sf19a2890-gmac" },
> +	{ }
> +};
> +MODULE_DEVICE_TABLE(of, sf19a2890_gmac_match);
> +
> +static struct platform_driver sf19a2890_gmac_driver = {
> +	.probe = sf19a2890_gmac_probe,
> +	.remove = stmmac_pltfr_remove,
> +	.driver = {
> +		.name = "sf19a2890-gmac",
> +		.pm = &stmmac_pltfr_pm_ops,
> +		.of_match_table = sf19a2890_gmac_match,
> +	},
> +};
> +module_platform_driver(sf19a2890_gmac_driver);
> +
> +MODULE_DESCRIPTION("Siflower SF19A2890 GMAC glue");
> +MODULE_LICENSE("GPL");

Thanks :)

Maxime 

Re: [PATCH net-next 2/2] net: stmmac: Add Siflower SF19A2890 glue

[Joseph Telaak]

> This is only used during the probe sequence, you can simply pass it as
> function parameters, this avoids using up memory to store that :)

Thanks, v2 will pass the device to the delay helpers and drop the
member.

Re: [PATCH net-next 2/2] net: stmmac: Add Siflower SF19A2890 glue

[Andrew Lunn]

> +/* The MAC adds an RGMII delay only where the device tree asks for one */
> +static int sf19a2890_gmac_set_delays(struct sf19a2890_gmac *gmac)
> +{
> +	u32 tx, rx;
> +	int ret;
> +
> +	ret = sf19a2890_gmac_get_delay(gmac, "tx-internal-delay-ps", &tx);
> +	if (ret)
> +		return ret;
> +
> +	ret = sf19a2890_gmac_get_delay(gmac, "rx-internal-delay-ps", &rx);
> +	if (ret)
> +		return ret;
> +
> +	writel(tx, gmac->cfg + SF19A2890_GMAC_TX_DELAY);
> +	writel(rx, gmac->cfg + SF19A2890_GMAC_RX_DELAY);
> +	writel(!!rx, gmac->cfg + SF19A2890_GMAC_RX_DELAY_EN);

What does SF19A2890_GMAC_RX_DELAY_EN do? By default rx is 0, so the
delay is not enabled. Is that any different to actually enabling it
with SF19A2890_GMAC_RX_DELAY set to 0?

	Andrew

Re: [PATCH net-next 2/2] net: stmmac: Add Siflower SF19A2890 glue

[Joseph Telaak]

> What does SF19A2890_GMAC_RX_DELAY_EN do? By default rx is 0, so the
> delay is not enabled. Is that any different to actually enabling it
> with SF19A2890_GMAC_RX_DELAY set to 0?

RX_DELAY_EN switches the RX delay line in; with it clear the line is
bypassed. I checked on the board: with it clear, the link passes
traffic at every RX_DELAY value, including 40 and 80 steps, which fail
with it set; with it set, RX_DELAY applies as measured in the sweep.

With RX_DELAY at 0, enabled and bypassed both pass traffic, so any
difference between them is too small to show at 1000 Mb/s. v2 will
explain this in a comment.

Re: [PATCH net-next 0/2] net: stmmac: Add the Siflower SF19A2890 glue

[Maxime Chevallier]

Hi Joseph,

On 11/4/26 08:22, Joseph Telaak via B4 Relay wrote:
> The Siflower SF19A2890, a MIPS SoC for home routers, has a DesignWare
> GMAC 3.73a. Its interface type and RGMII clock delays are set in a
> small configuration block next to its clock and reset manager. This
> series adds a binding and the glue.
> 
> The glue is based on Chuanhong Guo's driver, which read the RGMII delays
> from a factory flash cell in the delay line's own units and always
> applied them. Here the delays come from rx-internal-delay-ps and
> tx-internal-delay-ps and are applied only when those are present. The
> interface type is set through set_phy_intf_sel.
> 
> The delay line's step is not documented, so I measured it: sweeping
> each delay register over 0-255 with the link at 1000 Mb/s, the working
> windows repeat every 145 steps (TX) and 144.5 steps (RX), which is one
> 8 ns period of the 125 MHz RGMII clock. So a step is about 55 ps. The
> TX eye is about 3.1 ns wide and the RX eye about 1.75 ns; the delays the
> bootloader programs, 17 and 10 steps (935 and 550 ps), sit inside both.
> 
> On the GL.iNet GL-SFT1200 the GMAC is the CPU port of a MaxLinear GSW150
> switch over RGMII with no delays on the board; the GMAC adds both.
> 
> The MAINTAINERS entry that covers these files comes with the MIPS series
> "MIPS: Add support for the Siflower SF19A2890"; this series applies on
> its own. That entry is also why checkpatch's question about updating
> MAINTAINERS for the new files is left unanswered here.

hmm not sure this is the common practice, usually you update MAINTAINERS
along with the driver introduction. This should be part of this series.

> 
> Tested on a GL-SFT1200 with the GSW150 driver:
> - each of WAN, LAN 1 and LAN 2 links at 1000 Mb/s full duplex and
>   passes iperf3 both ways (160-205 Mb/s out, 262-273 Mb/s in, well
>   under line rate; I have not looked into where the limit is);
> - 10 GB each way through LAN 1, after which every CRC, alignment,
>   error, drop, overflow and underflow counter on eth0 and lan1 is 0;
> - 50 link down/up cycles, after which the link and traffic recover;
> - the MAC address from the factory partition, and ethtool reporting the
>   link with no PCS workaround.

no PCS workaround ? what's that about ?

Besides that, nice and simple glue, thanks ! :)

Maxime

> 
> ---
> Joseph Telaak (2):
>       dt-bindings: net: Add Siflower SF19A2890 GMAC
>       net: stmmac: Add Siflower SF19A2890 glue
> 
>  .../bindings/net/siflower,sf19a2890-gmac.yaml      | 110 ++++++++++++++
>  .../devicetree/bindings/net/snps,dwmac.yaml        |   1 +
>  drivers/net/ethernet/stmicro/stmmac/Kconfig        |  11 ++
>  drivers/net/ethernet/stmicro/stmmac/Makefile       |   1 +
>  .../net/ethernet/stmicro/stmmac/dwmac-sf19a2890.c  | 158 +++++++++++++++++++++
>  5 files changed, 281 insertions(+)
> ---
> base-commit: 7b6ab4dbc156e2f96419715130b3d5738a306c93
> change-id: 20261102-sf19a2890-gmac-4fb4808f869c
> 
> Best regards,
> --  
> Joseph Telaak <joseph@telaak.dev>

Re: [PATCH net-next 0/2] net: stmmac: Add the Siflower SF19A2890 glue

[Joseph Telaak]

On 11/4/26 08:53, Maxime Chevallier wrote:
>> The MAINTAINERS entry that covers these files comes with the MIPS series
>> "MIPS: Add support for the Siflower SF19A2890"; this series applies on
>> its own. That entry is also why checkpatch's question about updating
>> MAINTAINERS for the new files is left unanswered here.
>
> hmm not sure this is the common practice, usually you update MAINTAINERS
> along with the driver introduction. This should be part of this series.

Makes sense, v2 will add a MAINTAINERS entry for the glue and its
binding.

>> - the MAC address from the factory partition, and ethtool reporting the
>>   link with no PCS workaround.
>
> no PCS workaround ? what's that about ?

The OpenWrt driver this is based on set STMMAC_FLAG_HAS_INTEGRATED_PCS,
because the core reports a PCS whose link status doesn't work in RGMII
mode. stmmac now only uses the integrated PCS for SGMII and the flag is
gone, so the glue needs nothing for it. That line was only meant to say
the link is reported correctly without it; I'll word it better in v2.

On Wed, Nov 4, 2026 at 2:59 AM Maxime Chevallier
<maxime.chevallier@bootlin.com> wrote:
>
> Hi Joseph,
>
> On 11/4/26 08:22, Joseph Telaak via B4 Relay wrote:
> > The Siflower SF19A2890, a MIPS SoC for home routers, has a DesignWare
> > GMAC 3.73a. Its interface type and RGMII clock delays are set in a
> > small configuration block next to its clock and reset manager. This
> > series adds a binding and the glue.
> >
> > The glue is based on Chuanhong Guo's driver, which read the RGMII delays
> > from a factory flash cell in the delay line's own units and always
> > applied them. Here the delays come from rx-internal-delay-ps and
> > tx-internal-delay-ps and are applied only when those are present. The
> > interface type is set through set_phy_intf_sel.
> >
> > The delay line's step is not documented, so I measured it: sweeping
> > each delay register over 0-255 with the link at 1000 Mb/s, the working
> > windows repeat every 145 steps (TX) and 144.5 steps (RX), which is one
> > 8 ns period of the 125 MHz RGMII clock. So a step is about 55 ps. The
> > TX eye is about 3.1 ns wide and the RX eye about 1.75 ns; the delays the
> > bootloader programs, 17 and 10 steps (935 and 550 ps), sit inside both.
> >
> > On the GL.iNet GL-SFT1200 the GMAC is the CPU port of a MaxLinear GSW150
> > switch over RGMII with no delays on the board; the GMAC adds both.
> >
> > The MAINTAINERS entry that covers these files comes with the MIPS series
> > "MIPS: Add support for the Siflower SF19A2890"; this series applies on
> > its own. That entry is also why checkpatch's question about updating
> > MAINTAINERS for the new files is left unanswered here.
>
> hmm not sure this is the common practice, usually you update MAINTAINERS
> along with the driver introduction. This should be part of this series.
>
> >
> > Tested on a GL-SFT1200 with the GSW150 driver:
> > - each of WAN, LAN 1 and LAN 2 links at 1000 Mb/s full duplex and
> >   passes iperf3 both ways (160-205 Mb/s out, 262-273 Mb/s in, well
> >   under line rate; I have not looked into where the limit is);
> > - 10 GB each way through LAN 1, after which every CRC, alignment,
> >   error, drop, overflow and underflow counter on eth0 and lan1 is 0;
> > - 50 link down/up cycles, after which the link and traffic recover;
> > - the MAC address from the factory partition, and ethtool reporting the
> >   link with no PCS workaround.
>
> no PCS workaround ? what's that about ?
>
> Besides that, nice and simple glue, thanks ! :)
>
> Maxime
>
> >
> > ---
> > Joseph Telaak (2):
> >       dt-bindings: net: Add Siflower SF19A2890 GMAC
> >       net: stmmac: Add Siflower SF19A2890 glue
> >
> >  .../bindings/net/siflower,sf19a2890-gmac.yaml      | 110 ++++++++++++++
> >  .../devicetree/bindings/net/snps,dwmac.yaml        |   1 +
> >  drivers/net/ethernet/stmicro/stmmac/Kconfig        |  11 ++
> >  drivers/net/ethernet/stmicro/stmmac/Makefile       |   1 +
> >  .../net/ethernet/stmicro/stmmac/dwmac-sf19a2890.c  | 158 +++++++++++++++++++++
> >  5 files changed, 281 insertions(+)
> > ---
> > base-commit: 7b6ab4dbc156e2f96419715130b3d5738a306c93
> > change-id: 20261102-sf19a2890-gmac-4fb4808f869c
> >
> > Best regards,
> > --
> > Joseph Telaak <joseph@telaak.dev>
>
>