From: Stanimir Varbanov <svarbanov@suse.de>
To: Stanimir Varbanov <svarbanov@suse.de>,
Jim Quinlan <james.quinlan@broadcom.com>,
linux-pci@vger.kernel.org,
Nicolas Saenz Julienne <nsaenz@kernel.org>,
Bjorn Helgaas <bhelgaas@google.com>,
Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>,
Cyril Brulebois <kibi@debian.org>,
bcm-kernel-feedback-list@broadcom.com, jim2101024@gmail.com
Cc: "Florian Fainelli" <florian.fainelli@broadcom.com>,
"Lorenzo Pieralisi" <lpieralisi@kernel.org>,
"Krzysztof Wilczyński" <kw@linux.com>,
"Rob Herring" <robh@kernel.org>,
"moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE"
<linux-rpi-kernel@lists.infradead.org>,
"moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE"
<linux-arm-kernel@lists.infradead.org>,
"open list" <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH v2 09/12] PCI: brcmstb: Refactor for chips with many regular inbound BARs
Date: Thu, 4 Jul 2024 23:11:55 +0300 [thread overview]
Message-ID: <bd097824-17a7-407f-ba92-6c4ef2c0029f@suse.de> (raw)
In-Reply-To: <8433a148-47d5-49a0-b7ed-75801060bce7@suse.de>
Hi,
On 7/4/24 16:30, Stanimir Varbanov wrote:
> Hi Jim,
>
> On 7/3/24 21:02, Jim Quinlan wrote:
>> Previously, our chips provided three inbound "BARS" with fixed purposes:
>> the first was for mapping SOC registers, the second was for memory, and the
>> third was for memory but with the endian swapped. We typically only used
>> one of these BARs.
>>
>> Complicating that BARs usage was the fact that the PCIe HW would do a
>> baroque internal mapping of system memory, and concatenate the regions of
>> multiple memory controllers.
>>
>> Newer chips such as the 7712 and Cable Modem SOCs have taken a step forward
>> and now provide multiple inbound BARs. This works in concert with the
>> dma-ranges property, where each provided range becomes an inbound BAR.
>>
>> This commit provides support for these new chips and their multiple
>> inbound BARs but also keeps the legacy support for the older system.
>>
>> Signed-off-by: Jim Quinlan <james.quinlan@broadcom.com>
>> ---
>> drivers/pci/controller/pcie-brcmstb.c | 199 +++++++++++++++++++-------
>> 1 file changed, 150 insertions(+), 49 deletions(-)
<cut>
>> static int brcm_pcie_setup(struct brcm_pcie *pcie)
>> {
>> - u64 rc_bar2_offset, rc_bar2_size;
>> + struct rc_bar rc_bars[PCIE_BRCM_MAX_RC_BARS];
>> void __iomem *base = pcie->base;
>> struct pci_host_bridge *bridge;
>> struct resource_entry *entry;
>> u32 tmp, burst, aspm_support;
>> - int num_out_wins = 0;
>> - int ret, memc;
>> + int num_out_wins = 0, num_rc_bars = 0;
>> + int i, memc;
>>
>> /* Reset the bridge */
>> pcie->bridge_sw_init_set(pcie, 1);
>> @@ -933,17 +1016,47 @@ static int brcm_pcie_setup(struct brcm_pcie *pcie)
>> u32p_replace_bits(&tmp, 1, PCIE_MISC_MISC_CTRL_PCIE_RCB_64B_MODE_MASK);
>> writel(tmp, base + PCIE_MISC_MISC_CTRL);
>>
>> - ret = brcm_pcie_get_rc_bar2_size_and_offset(pcie, &rc_bar2_size,
>> - &rc_bar2_offset);
>> - if (ret)
>> - return ret;
>> + num_rc_bars = brcm_pcie_get_rc_bar_sizes_and_offsets(pcie, rc_bars);
>
> Can we change the function name to brcm_pcie_get_inbound_regions? ...
... or better brcm_pcie_get_inbound_wins() ?
~Stan
next prev parent reply other threads:[~2024-07-04 20:12 UTC|newest]
Thread overview: 42+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-07-03 18:02 [PATCH v2 00/12] PCI: brcnstb: Enable STB 7712 SOC Jim Quinlan
2024-07-03 18:02 ` [PATCH v2 01/12] dt-bindings: PCI: Add Broadcom STB 7712 SOC, update maintainer Jim Quinlan
2024-07-04 6:40 ` Krzysztof Kozlowski
2024-07-05 20:02 ` Jim Quinlan
2024-07-07 11:58 ` Krzysztof Kozlowski
2024-07-12 20:13 ` Jim Quinlan
2024-07-13 9:53 ` Krzysztof Kozlowski
2024-07-12 19:54 ` Jim Quinlan
2024-07-13 9:52 ` Krzysztof Kozlowski
2024-07-03 18:02 ` [PATCH v2 02/12] PCI: brcmstb: Use "clk_out" error path label Jim Quinlan
2024-07-04 11:40 ` Markus Elfring
2024-07-05 14:48 ` Jim Quinlan
2024-07-05 15:45 ` [v2 " Markus Elfring
2024-07-05 17:07 ` Jim Quinlan
2024-07-04 12:53 ` [PATCH v2 " Stanimir Varbanov
2024-07-03 18:02 ` [PATCH v2 03/12] PCI: brcmstb: Use bridge reset if available Jim Quinlan
2024-07-03 18:02 ` [PATCH v2 04/12] PCI: brcmstb: Use swinit " Jim Quinlan
2024-07-04 12:56 ` Stanimir Varbanov
2024-07-05 17:46 ` Jim Quinlan
2024-07-08 9:37 ` Philipp Zabel
2024-07-08 11:14 ` Stanimir Varbanov
2024-07-08 13:26 ` Philipp Zabel
2024-07-08 14:38 ` Jim Quinlan
2024-07-05 8:23 ` Stanimir Varbanov
2024-07-03 18:02 ` [PATCH v2 05/12] PCI: brcmstb: Get resource before we start asserting reset controllers Jim Quinlan
2024-07-04 13:00 ` Stanimir Varbanov
2024-07-03 18:02 ` [PATCH v2 06/12] PCI: brcmstb: PCI: brcmstb: Make HARD_DEBUG, INTR2_CPU_BASE offsets SoC-specific Jim Quinlan
2024-07-04 13:05 ` Stanimir Varbanov
2024-07-03 18:02 ` [PATCH v2 07/12] PCI: brcmstb: Remove two unused constants from driver Jim Quinlan
2024-07-04 13:06 ` Stanimir Varbanov
2024-07-03 18:02 ` [PATCH v2 08/12] PCI: brcmstb: Don't conflate the reset rescal with phy ctrl Jim Quinlan
2024-07-04 13:08 ` Stanimir Varbanov
2024-07-03 18:02 ` [PATCH v2 09/12] PCI: brcmstb: Refactor for chips with many regular inbound BARs Jim Quinlan
2024-07-04 13:30 ` Stanimir Varbanov
2024-07-04 20:11 ` Stanimir Varbanov [this message]
2024-07-04 20:17 ` Stanimir Varbanov
2024-07-03 18:02 ` [PATCH v2 10/12] PCI: brcmstb: Check return value of all reset_control_xxx calls Jim Quinlan
2024-07-04 13:49 ` Stanimir Varbanov
2024-07-05 14:28 ` Jim Quinlan
2024-07-03 18:02 ` [PATCH v2 11/12] PCI: brcmstb: Enable 7712 SOCs Jim Quinlan
2024-07-04 13:51 ` Stanimir Varbanov
2024-07-03 18:02 ` [PATCH v2 12/12] PCI: brcmstb: Change field name from 'type' to 'model' Jim Quinlan
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