From: "Chen, Yu C" <yu.c.chen@intel.com>
To: Reinette Chatre <reinette.chatre@intel.com>
Cc: <x86@kernel.org>, <linux-kernel@vger.kernel.org>, <bp@alien8.de>,
<mingo@redhat.com>, <dave.hansen@linux.intel.com>,
<hpa@zytor.com>, <dave.martin@arm.com>, <james.morse@arm.com>,
<fenghuay@nvidia.com>, <babu.moger@amd.com>,
<anil.keshavamurthy@broadcom.com>, <tony.luck@intel.com>,
Thomas Gleixner <tglx@kernel.org>
Subject: Re: [PATCH v3 5/6] fs/resctrl: Do not invoke smp_processor_id() in preemptible context
Date: Tue, 9 Jun 2026 00:45:58 +0800 [thread overview]
Message-ID: <c024b55e-586c-465d-8476-ae1881b5610f@intel.com> (raw)
In-Reply-To: <7bb16cf1-567f-4a08-b399-d6069023a02b@intel.com>
Hi Reinette,
On 6/8/2026 11:10 PM, Reinette Chatre wrote:
> Hi Chenyu,
>
> On 6/8/26 4:26 AM, Chen, Yu C wrote:
>> On 6/8/2026 4:36 PM, Thomas Gleixner wrote:
>>> On Sat, Jun 06 2026 at 10:38, Chen Yu wrote:
>>>> From: Tony Luck <tony.luck@intel.com>
>>>>
>>>> __l3_mon_event_count() and __l3_mon_event_count_sum() call
>>>> smp_processor_id() to obtain the current CPU. However, some
>>>> monitor events can be read from any CPU in task context via
>>>> mon_event_count(); in that case the calling context is
>>>> preemptible and smp_processor_id() triggers a debug warning.
>>>
>>> Is this new with this MMIO stuff or is this an existing issue? If the
>>> latter then this patch should be in front of the series and get a fixes
>>> tag. If not the change log should explain it.
>>>
>>
>> It is an existing issue. I'll adjust the sequence and provide a fixes tag.
>> Thanks!
>
>
> Could you please elaborate how this is an existing issue?
>
> At this point in implementation mon_evt::any_cpu is and can only be false for
> all events associated with resource RDT_RESOURCE_L3. This is highlighted by
> the existing splat that will be triggered by the
> WARN_ON_ONCE(rr->evt->any_cpu);
> that is removed by this patch.
>
> It is this series that makes it possible to read L3 cache occupancy from any CPU.
> This is only done in the following patch (6/6) that makes mon_evt::any_cpu for
> L3 cache occupancy be conditional on MMIO support enabled by this series.
>
> This patch (5/6) replaces the above mentioned splat with a subtler check since it
> is about to become possible for L3 cache occupancy events to be read from any CPU.
>
> I thus do not see this as an existing issue needing fixing but instead a
> necessary part of this series that is specifically a preparatory patch for the
> final MMIO based event enabling done in patch 6/6.
>
You are right. For RDT_RESOURCE_L3 monitor data reading, before MMIO
monitor read is
introduced, any_cpu is false, and MSRs are always read on the CPU of
that domain in the
IPI context. Let me refine the commit log for [PATCH 5/6].
thanks,
Chenyu
next prev parent reply other threads:[~2026-06-08 16:46 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-06-06 2:31 [PATCH v3 0/6] Introduce MMIO-based CMT access for Enhanced RDT Chen Yu
2026-06-06 2:32 ` [PATCH v3 1/6] x86/resctrl: Parse ACPI ERDT table and map RMDD domains by L3 cache ID Chen Yu
2026-06-08 8:59 ` Thomas Gleixner
2026-06-08 11:20 ` Chen, Yu C
2026-06-06 2:33 ` [PATCH v3 2/6] x86/resctrl: Parse ACPI CMRC table Chen Yu
2026-06-08 8:30 ` Thomas Gleixner
2026-06-06 2:35 ` [PATCH v3 3/6] x86/resctrl: Rename prev_msr to prev_mon_val Chen Yu
2026-06-08 8:32 ` Thomas Gleixner
2026-06-06 2:38 ` [PATCH v3 4/6] x86/resctrl: Refactor the monitor read function Chen Yu
2026-06-06 2:38 ` [PATCH v3 5/6] fs/resctrl: Do not invoke smp_processor_id() in preemptible context Chen Yu
2026-06-08 8:36 ` Thomas Gleixner
2026-06-08 11:26 ` Chen, Yu C
2026-06-08 15:10 ` Reinette Chatre
2026-06-08 16:45 ` Chen, Yu C [this message]
2026-06-08 15:32 ` Luck, Tony
2026-06-08 16:54 ` Chen, Yu C
2026-06-06 2:38 ` [PATCH v3 6/6] x86/resctrl: Add support for L3 occupancy monitoring via RMID MMIO read Chen Yu
2026-06-08 8:33 ` Thomas Gleixner
2026-06-10 1:49 ` [PATCH v3 0/6] Introduce MMIO-based CMT access for Enhanced RDT Ning, Hongyu
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=c024b55e-586c-465d-8476-ae1881b5610f@intel.com \
--to=yu.c.chen@intel.com \
--cc=anil.keshavamurthy@broadcom.com \
--cc=babu.moger@amd.com \
--cc=bp@alien8.de \
--cc=dave.hansen@linux.intel.com \
--cc=dave.martin@arm.com \
--cc=fenghuay@nvidia.com \
--cc=hpa@zytor.com \
--cc=james.morse@arm.com \
--cc=linux-kernel@vger.kernel.org \
--cc=mingo@redhat.com \
--cc=reinette.chatre@intel.com \
--cc=tglx@kernel.org \
--cc=tony.luck@intel.com \
--cc=x86@kernel.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox
all inboxes | Powered by JetHome®