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From: "Ning, Hongyu" <hongyu.ning@linux.intel.com>
To: Chen Yu <yu.c.chen@intel.com>,
	tony.luck@intel.com, reinette.chatre@intel.com
Cc: x86@kernel.org, linux-kernel@vger.kernel.org, bp@alien8.de,
	tglx@kernel.org, mingo@redhat.com, dave.hansen@linux.intel.com,
	hpa@zytor.com, dave.martin@arm.com, james.morse@arm.com,
	fenghuay@nvidia.com, babu.moger@amd.com,
	anil.keshavamurthy@broadcom.com
Subject: Re: [PATCH v3 0/6] Introduce MMIO-based CMT access for Enhanced RDT
Date: Wed, 10 Jun 2026 09:49:10 +0800	[thread overview]
Message-ID: <c183e564-82e7-48a1-9df3-8d0553199d10@linux.intel.com> (raw)
In-Reply-To: <cover.1780710620.git.yu.c.chen@intel.com>



On 6/6/2026 10:31 AM, Chen Yu wrote:
> Intel Enhanced Resource Director Technology (ERDT) extends the existing
> RDT framework with two major capabilities:
> 
>    1. MMIO-based access to monitoring and allocation registers, replacing
>       the legacy MSR-based interface.
>    2. Region-aware RDT for fine-grained control over different tiers of
>       memory (e.g., CXL.mem, DDR).
> 
> This is described in the Intel RDT Architecture Specification:
> https://cdrdv2-public.intel.com/789566/356688-intel-rdt-arch-spec.pdf
> 
> This patch set focuses on the first part: enabling MMIO-based access for
> Cache Monitoring Technology (CMT), while CAT/MBM/MBA are still using MSR.
> The platform advertises the MMIO register layout through the ACPI ERDT
> (Enhanced Resource Director Technology) table, which contains sub-tables
> describing per-domain register regions for monitoring and allocation.
> 
> With ERDT, L3 cache occupancy counters are read via MMIO rather than
> MSR, allowing the reads to be performed from any CPU without requiring
> cross-CPU IPIs. This series parses the relevant ACPI sub-tables (RMDD,
> CMRC), prepares the resctrl monitor infrastructure for MMIO-based reads,
> and adds initial support for reading L3 occupancy via the CMRC interface.
> 
> kselftest of CMT and L3_CAT has passed with minor adjustment at
> https://lore.kernel.org/lkml/20260523101715.3964456-1-yu.c.chen@intel.com/.
> 
> Changes from V2 to V3:
> - Wrap __resctrl_arch_late_init() to avoid the goto logic. (Thomas Gleixner)
> - Make the variables in struct erdt_domain_info tabular format (Thomas Gleixner)
> - Remove tail comments (Thomas Gleixner)
> - Make the name of erdt_enabled() and variable in it consistent and
>    comprehensible. (Thomas Gleixner)
> - Use topo_lookup_cpuid() to search the CPU id according to the x2apic id
>    (Thomas Gleixner)
> - Fix kernel doc comment format (Thomas Gleixner)
> - Use brackets for multiple lines "if" case. (Thomas Gleixner)
> - Let the parameter for cacd_init() to fully utilize 100 characters.
>    (Thomas Gleixner)
> - Variables are reordered in reverse fir-tree.(Thomas Gleixner)
> - Added a named constant and use it in the rmdd->flags check.
>    (Thomas Gleixner)
> - Introduce helper functions to make the code readable when iterating
>    the RMDD tables. (Thomas Gleixner)
> - Make the macros tabular format. (Thomas Gleixner)
> 
> Changes from V1 to V2:
> - Add #include <linux/cleanup.h> to follow the "include-what-you-use" best
>    practice (Tony Luck)
> - Fix 3 issues reported by:
>    https://sashiko.dev/#/patchset/cover.1779872016.git.yu.c.chen%40intel.com
>    Remove the variable of cacd in struct erdt_domain_info as it will
>    never be used after initialization.
>    Invoke erdt_exit() to avoid resource leak if rdt_alloc_capable and
>    rdt_mon_capable are both false.
>    Adjust the comments suggested by sashiko.
> 
> Anil S Keshavamurthy (1):
>    x86/resctrl: Parse ACPI ERDT table and map RMDD domains by L3 cache ID
> 
> Chen Yu (4):
>    x86/resctrl: Parse ACPI CMRC table
>    x86/resctrl: Rename prev_msr to prev_mon_val
>    x86/resctrl: Refactor the monitor read function
>    x86/resctrl: Add support for L3 occupancy monitoring via RMID MMIO
>      read
> 
> Tony Luck (1):
>    fs/resctrl: Do not invoke smp_processor_id() in preemptible context
> 
>   arch/x86/Kconfig                       |   4 +-
>   arch/x86/include/asm/apic.h            |   1 +
>   arch/x86/include/asm/resctrl.h         |   4 +
>   arch/x86/kernel/cpu/resctrl/Makefile   |   1 +
>   arch/x86/kernel/cpu/resctrl/core.c     |  16 +-
>   arch/x86/kernel/cpu/resctrl/erdt.c     | 433 +++++++++++++++++++++++++
>   arch/x86/kernel/cpu/resctrl/internal.h |  11 +-
>   arch/x86/kernel/cpu/resctrl/monitor.c  |  64 ++--
>   arch/x86/kernel/cpu/topology.c         |   2 +-
>   fs/resctrl/monitor.c                   |  41 ++-
>   10 files changed, 535 insertions(+), 42 deletions(-)
>   create mode 100644 arch/x86/kernel/cpu/resctrl/erdt.c
> 

Tested-by: Hongyu Ning <hongyu.ning@linux.intel.com>

      parent reply	other threads:[~2026-06-10  1:49 UTC|newest]

Thread overview: 19+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-06-06  2:31 Chen Yu
2026-06-06  2:32 ` [PATCH v3 1/6] x86/resctrl: Parse ACPI ERDT table and map RMDD domains by L3 cache ID Chen Yu
2026-06-08  8:59   ` Thomas Gleixner
2026-06-08 11:20     ` Chen, Yu C
2026-06-06  2:33 ` [PATCH v3 2/6] x86/resctrl: Parse ACPI CMRC table Chen Yu
2026-06-08  8:30   ` Thomas Gleixner
2026-06-06  2:35 ` [PATCH v3 3/6] x86/resctrl: Rename prev_msr to prev_mon_val Chen Yu
2026-06-08  8:32   ` Thomas Gleixner
2026-06-06  2:38 ` [PATCH v3 4/6] x86/resctrl: Refactor the monitor read function Chen Yu
2026-06-06  2:38 ` [PATCH v3 5/6] fs/resctrl: Do not invoke smp_processor_id() in preemptible context Chen Yu
2026-06-08  8:36   ` Thomas Gleixner
2026-06-08 11:26     ` Chen, Yu C
2026-06-08 15:10       ` Reinette Chatre
2026-06-08 16:45         ` Chen, Yu C
2026-06-08 15:32       ` Luck, Tony
2026-06-08 16:54         ` Chen, Yu C
2026-06-06  2:38 ` [PATCH v3 6/6] x86/resctrl: Add support for L3 occupancy monitoring via RMID MMIO read Chen Yu
2026-06-08  8:33   ` Thomas Gleixner
2026-06-10  1:49 ` Ning, Hongyu [this message]

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