From: Suzuki K Poulose <Suzuki.Poulose@arm.com>
To: Julien Thierry <julien.thierry@arm.com>,
linux-arm-kernel@lists.infradead.org
Cc: linux-kernel@vger.kernel.org, daniel.thompson@linaro.org,
joel@joelfernandes.org, marc.zyngier@arm.com,
mark.rutland@arm.com, christoffer.dall@arm.com,
james.morse@arm.com, catalin.marinas@arm.com,
will.deacon@arm.com
Subject: Re: [PATCH v4 02/26] arm64: cpufeature: Add cpufeature for IRQ priority masking
Date: Fri, 25 May 2018 11:36:25 +0100 [thread overview]
Message-ID: <c4e5f8ff-ecde-7b88-8a37-39e47ef22917@arm.com> (raw)
In-Reply-To: <b0673d7e-9a1e-7dcb-5322-c05fe0821349@arm.com>
On 25/05/18 11:17, Julien Thierry wrote:
>
>
> On 25/05/18 11:04, Suzuki K Poulose wrote:
>> On 25/05/18 10:49, Julien Thierry wrote:
>>> Add a cpufeature indicating whether a cpu supports masking interrupts
>>> by priority.
>>
>> How is this different from the SYSREG_GIC_CPUIF cap ? Is it just
>> the description ?
>
> More or less.
>
> It is just to have an easier condition in the rest of the series. Basically the PRIO masking feature is enabled if we have a GICv3 CPUIF working *and* the option was selected at build time. Before this meant that I was checking for the GIC_CPUIF cap inside #ifdefs (and putting alternatives depending on that inside #ifdefs as well).
>
> Having this as a separate feature feels easier to manage in the code. It also makes it clearer at boot time that the kernel will be using irq priorities (although I admit it was not the initial intention):
>
> [ 0.000000] CPU features: detected: IRQ priority masking
>
>
> But yes that new feature will be detected only if SYSREG_GIC_CPUIF gets detected as well.
Well, you could always wrap the check like :
static inline bool system_has_irq_priority_masking(void)
{
return (IS_ENABLED(CONFIG_YOUR_CONFIG) && cpus_have_const_cap(HWCAP_SYSREG_GIC_CPUIF));
}
and use it everywhere.
The description could be statically changed to reflect based on the #ifdef.
static const struct arm64_cpu_capabilities arm64_features[] = {
{
#ifdef CONFIG_YOUR_CONFIG
.desc = "GIC System register CPU interface with IRQ priority masking"
#else
.desc = "GIC system register CPU interface",
#endif
.capability = ARM64_HAS_SYSREG_GIC_CPUIF,
.type = ARM64_CPUCAP_SYSTEM_FEATURE,
.matches = has_useable_gicv3_cpuif,
.sys_reg = SYS_ID_AA64PFR0_EL1,
.field_pos = ID_AA64PFR0_GIC_SHIFT,
.sign = FTR_UNSIGNED,
.min_field_value = 1,
Cheers
Suzuki
next prev parent reply other threads:[~2018-05-25 10:36 UTC|newest]
Thread overview: 44+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-05-25 9:49 [PATCH v4 00/26] arm64: provide pseudo NMI with GICv3 Julien Thierry
2018-05-25 9:49 ` [PATCH v4 01/26] arm64: cpufeature: Set SYSREG_GIC_CPUIF as a boot system feature Julien Thierry
2018-05-25 9:49 ` [PATCH v4 02/26] arm64: cpufeature: Add cpufeature for IRQ priority masking Julien Thierry
2018-05-25 10:04 ` Suzuki K Poulose
2018-05-25 10:17 ` Julien Thierry
2018-05-25 10:36 ` Suzuki K Poulose [this message]
2018-05-25 10:39 ` Julien Thierry
2018-05-25 10:41 ` Suzuki K Poulose
2018-05-25 10:48 ` Julien Thierry
2018-06-12 13:46 ` Julien Thierry
2018-06-15 10:16 ` Suzuki K Poulose
2018-05-25 9:49 ` [PATCH v4 03/26] arm64: cpufeature: Use alternatives for VHE cpu_enable Julien Thierry
2018-05-25 9:49 ` [PATCH v4 04/26] arm64: alternative: Apply alternatives early in boot process Julien Thierry
2018-05-25 10:00 ` Suzuki K Poulose
2018-05-25 10:25 ` Julien Thierry
2018-05-25 9:49 ` [PATCH v4 05/26] irqchip/gic: Unify GIC priority definitions Julien Thierry
2018-05-25 9:49 ` [PATCH v4 06/26] irqchip/gic: Lower priority of GIC interrupts Julien Thierry
2018-05-25 9:49 ` [PATCH v4 07/26] irqchip/gic-v3: Remove acknowledge loop Julien Thierry
2018-05-25 9:49 ` [PATCH v4 08/26] arm64: daifflags: Use irqflags functions for daifflags Julien Thierry
2018-05-25 9:49 ` [PATCH v4 09/26] arm64: Use daifflag_restore after bp_hardening Julien Thierry
2018-05-25 9:49 ` [PATCH v4 10/26] arm64: Delay daif masking for user return Julien Thierry
2018-05-25 9:49 ` [PATCH v4 11/26] arm64: Make PMR part of task context Julien Thierry
2018-05-25 9:49 ` [PATCH v4 12/26] arm64: Unmask PMR before going idle Julien Thierry
2018-05-25 9:49 ` [PATCH v4 13/26] arm/arm64: gic-v3: Add helper functions to manage IRQ priorities Julien Thierry
2018-05-25 9:49 ` [PATCH v4 14/26] arm64: kvm: Unmask PMR before entering guest Julien Thierry
2018-05-25 9:49 ` [PATCH v4 15/26] arm64: irqflags: Use ICC_PMR_EL1 for interrupt masking Julien Thierry
2018-05-25 9:49 ` [PATCH v4 16/26] arm64: daifflags: Include PMR in daifflags restore operations Julien Thierry
2018-05-25 9:49 ` [PATCH v4 17/26] irqchip/gic-v3: Factor group0 detection into functions Julien Thierry
2018-05-25 9:49 ` [PATCH v4 18/26] irqchip/gic-v3: Do not overwrite PMR value Julien Thierry
2018-05-25 9:49 ` [PATCH v4 19/26] irqchip/gic-v3: Switch to PMR masking after IRQ acknowledge Julien Thierry
2018-05-25 9:49 ` [PATCH v4 20/26] arm64: Switch to PMR masking when starting CPUs Julien Thierry
2018-05-25 9:49 ` [PATCH v4 21/26] arm64: Add build option for IRQ masking via priority Julien Thierry
2018-05-25 9:49 ` [PATCH v4 22/26] arm64: Detect current view of GIC priorities Julien Thierry
2018-05-25 9:49 ` [PATCH v4 23/26] irqchip/gic: Add functions to access irq priorities Julien Thierry
2018-05-25 9:49 ` [PATCH v4 24/26] irqchip/gic-v3: Add base support for pseudo-NMI Julien Thierry
2018-06-13 11:14 ` Julien Thierry
2018-05-25 9:49 ` [PATCH v4 25/26] irqchip/gic-v3: Provide NMI handlers Julien Thierry
2018-05-25 9:49 ` [PATCH v4 26/26] irqchip/gic-v3: Allow interrupts to be set as pseudo-NMI Julien Thierry
2018-06-13 11:07 ` Julien Thierry
2018-05-25 10:16 ` [PATCH v4 00/26] arm64: provide pseudo NMI with GICv3 Daniel Thompson
2018-05-25 10:40 ` Julien Thierry
2018-05-25 13:42 ` Julien Thierry
2018-07-20 15:09 ` Daniel Thompson
2018-07-23 12:39 ` Julien Thierry
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=c4e5f8ff-ecde-7b88-8a37-39e47ef22917@arm.com \
--to=suzuki.poulose@arm.com \
--cc=catalin.marinas@arm.com \
--cc=christoffer.dall@arm.com \
--cc=daniel.thompson@linaro.org \
--cc=james.morse@arm.com \
--cc=joel@joelfernandes.org \
--cc=julien.thierry@arm.com \
--cc=linux-arm-kernel@lists.infradead.org \
--cc=linux-kernel@vger.kernel.org \
--cc=marc.zyngier@arm.com \
--cc=mark.rutland@arm.com \
--cc=will.deacon@arm.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox
all inboxes | Powered by JetHome®