From: Alejandro Lucero Palau <alucerop@amd.com>
To: Wei Huang <wei.huang2@amd.com>,
linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-doc@vger.kernel.org, netdev@vger.kernel.org
Cc: Jonathan.Cameron@Huawei.com, helgaas@kernel.org, corbet@lwn.net,
davem@davemloft.net, edumazet@google.com, kuba@kernel.org,
pabeni@redhat.com, alex.williamson@redhat.com,
gospo@broadcom.com, michael.chan@broadcom.com,
ajit.khaparde@broadcom.com, somnath.kotur@broadcom.com,
andrew.gospodarek@broadcom.com, manoj.panicker2@amd.com,
Eric.VanTassell@amd.com, vadim.fedorenko@linux.dev,
horms@kernel.org, bagasdotme@gmail.com, bhelgaas@google.com,
lukas@wunner.de, paul.e.luse@intel.com, jing2.liu@intel.com
Subject: Re: [PATCH V4 11/12] bnxt_en: Add TPH support in BNXT driver
Date: Wed, 11 Sep 2024 16:37:20 +0100 [thread overview]
Message-ID: <c7b9cafc-4d9d-f443-12b5-bf3d7b178d2c@amd.com> (raw)
In-Reply-To: <20240822204120.3634-12-wei.huang2@amd.com>
On 8/22/24 21:41, Wei Huang wrote:
> From: Manoj Panicker <manoj.panicker2@amd.com>
>
> Implement TPH support in Broadcom BNXT device driver. The driver uses
> TPH functions to retrieve and configure the device's Steering Tags when
> its interrupt affinity is being changed.
>
> Co-developed-by: Wei Huang <wei.huang2@amd.com>
> Signed-off-by: Wei Huang <wei.huang2@amd.com>
> Signed-off-by: Manoj Panicker <manoj.panicker2@amd.com>
> Reviewed-by: Ajit Khaparde <ajit.khaparde@broadcom.com>
> Reviewed-by: Somnath Kotur <somnath.kotur@broadcom.com>
> Reviewed-by: Andy Gospodarek <andrew.gospodarek@broadcom.com>
> ---
> drivers/net/ethernet/broadcom/bnxt/bnxt.c | 78 +++++++++++++++++++++++
> drivers/net/ethernet/broadcom/bnxt/bnxt.h | 4 ++
> 2 files changed, 82 insertions(+)
>
> diff --git a/drivers/net/ethernet/broadcom/bnxt/bnxt.c b/drivers/net/ethernet/broadcom/bnxt/bnxt.c
> index ffa74c26ee53..5903cd36b54d 100644
> --- a/drivers/net/ethernet/broadcom/bnxt/bnxt.c
> +++ b/drivers/net/ethernet/broadcom/bnxt/bnxt.c
> @@ -55,6 +55,7 @@
> #include <net/page_pool/helpers.h>
> #include <linux/align.h>
> #include <net/netdev_queues.h>
> +#include <linux/pci-tph.h>
>
> #include "bnxt_hsi.h"
> #include "bnxt.h"
> @@ -10821,6 +10822,58 @@ int bnxt_reserve_rings(struct bnxt *bp, bool irq_re_init)
> return 0;
> }
>
> +static void __bnxt_irq_affinity_notify(struct irq_affinity_notify *notify,
> + const cpumask_t *mask)
> +{
> + struct bnxt_irq *irq;
> + u16 tag;
> +
> + irq = container_of(notify, struct bnxt_irq, affinity_notify);
> + cpumask_copy(irq->cpu_mask, mask);
> +
> + if (pcie_tph_get_cpu_st(irq->bp->pdev, TPH_MEM_TYPE_VM,
> + cpumask_first(irq->cpu_mask), &tag))
I understand just one cpu from the mask has to be used, but I wonder if
some check should be done for ensuring the mask is not mad.
This is control path and the related queue is going to be restarted, so
maybe a sanity check for ensuring all the cpus in the mask are from the
same CCX complex?
That would be an iteration checking the tag is the same one for all of
them. If not, at least a warning stating the tag/CCX/cpu used.
> + return;
> +
> + if (pcie_tph_set_st_entry(irq->bp->pdev, irq->msix_nr, tag))
> + return;
> +
> + if (netif_running(irq->bp->dev)) {
> + rtnl_lock();
> + bnxt_close_nic(irq->bp, false, false);
> + bnxt_open_nic(irq->bp, false, false);
> + rtnl_unlock();
> + }
> +}
> +
> +static void __bnxt_irq_affinity_release(struct kref __always_unused *ref)
> +{
> +}
> +
> +static void bnxt_release_irq_notifier(struct bnxt_irq *irq)
> +{
> + irq_set_affinity_notifier(irq->vector, NULL);
> +}
> +
> +static void bnxt_register_irq_notifier(struct bnxt *bp, struct bnxt_irq *irq)
> +{
> + struct irq_affinity_notify *notify;
> +
> + /* Nothing to do if TPH is not enabled */
> + if (!pcie_tph_enabled(bp->pdev))
> + return;
> +
> + irq->bp = bp;
> +
> + /* Register IRQ affinility notifier */
> + notify = &irq->affinity_notify;
> + notify->irq = irq->vector;
> + notify->notify = __bnxt_irq_affinity_notify;
> + notify->release = __bnxt_irq_affinity_release;
> +
> + irq_set_affinity_notifier(irq->vector, notify);
> +}
> +
> static void bnxt_free_irq(struct bnxt *bp)
> {
> struct bnxt_irq *irq;
> @@ -10843,11 +10896,17 @@ static void bnxt_free_irq(struct bnxt *bp)
> free_cpumask_var(irq->cpu_mask);
> irq->have_cpumask = 0;
> }
> +
> + bnxt_release_irq_notifier(irq);
> +
> free_irq(irq->vector, bp->bnapi[i]);
> }
>
> irq->requested = 0;
> }
> +
> + /* Disable TPH support */
> + pcie_disable_tph(bp->pdev);
> }
>
> static int bnxt_request_irq(struct bnxt *bp)
> @@ -10870,6 +10929,13 @@ static int bnxt_request_irq(struct bnxt *bp)
> if (!(bp->flags & BNXT_FLAG_USING_MSIX))
> flags = IRQF_SHARED;
>
> + /* Enable TPH support as part of IRQ request */
> + if (pcie_tph_modes(bp->pdev) & PCI_TPH_CAP_INT_VEC) {
> + rc = pcie_enable_tph(bp->pdev, PCI_TPH_CAP_INT_VEC);
> + if (rc)
> + netdev_warn(bp->dev, "failed enabling TPH support\n");
> + }
> +
> for (i = 0, j = 0; i < bp->cp_nr_rings; i++) {
> int map_idx = bnxt_cp_num_to_irq_num(bp, i);
> struct bnxt_irq *irq = &bp->irq_tbl[map_idx];
> @@ -10893,8 +10959,10 @@ static int bnxt_request_irq(struct bnxt *bp)
>
> if (zalloc_cpumask_var(&irq->cpu_mask, GFP_KERNEL)) {
> int numa_node = dev_to_node(&bp->pdev->dev);
> + u16 tag;
>
> irq->have_cpumask = 1;
> + irq->msix_nr = map_idx;
> cpumask_set_cpu(cpumask_local_spread(i, numa_node),
> irq->cpu_mask);
> rc = irq_set_affinity_hint(irq->vector, irq->cpu_mask);
> @@ -10904,6 +10972,16 @@ static int bnxt_request_irq(struct bnxt *bp)
> irq->vector);
> break;
> }
> +
> + bnxt_register_irq_notifier(bp, irq);
> +
> + /* Init ST table entry */
> + if (pcie_tph_get_cpu_st(irq->bp->pdev, TPH_MEM_TYPE_VM,
> + cpumask_first(irq->cpu_mask),
> + &tag))
> + break;
> +
> + pcie_tph_set_st_entry(irq->bp->pdev, irq->msix_nr, tag);
> }
> }
> return rc;
> diff --git a/drivers/net/ethernet/broadcom/bnxt/bnxt.h b/drivers/net/ethernet/broadcom/bnxt/bnxt.h
> index 6bbdc718c3a7..ae1abcc1bddf 100644
> --- a/drivers/net/ethernet/broadcom/bnxt/bnxt.h
> +++ b/drivers/net/ethernet/broadcom/bnxt/bnxt.h
> @@ -1224,6 +1224,10 @@ struct bnxt_irq {
> u8 have_cpumask:1;
> char name[IFNAMSIZ + 2];
> cpumask_var_t cpu_mask;
> +
> + struct bnxt *bp;
> + int msix_nr;
> + struct irq_affinity_notify affinity_notify;
> };
>
> #define HWRM_RING_ALLOC_TX 0x1
next prev parent reply other threads:[~2024-09-11 15:38 UTC|newest]
Thread overview: 43+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-08-22 20:41 [PATCH V4 00/12] PCIe TPH and cache direct injection support Wei Huang
2024-08-22 20:41 ` [PATCH V4 01/12] PCI: Introduce PCIe TPH support framework Wei Huang
2024-08-22 20:41 ` [PATCH V4 02/12] PCI: Add TPH related register definition Wei Huang
2024-09-04 19:52 ` Bjorn Helgaas
2024-09-05 15:08 ` Wei Huang
2024-09-05 16:41 ` Bjorn Helgaas
2024-09-16 21:08 ` Wei Huang
2024-08-22 20:41 ` [PATCH V4 03/12] PCI/TPH: Add pcie_tph_modes() to query TPH modes Wei Huang
2024-09-04 19:40 ` Bjorn Helgaas
2024-09-05 14:46 ` Wei Huang
2024-09-05 15:12 ` Bjorn Helgaas
2024-08-22 20:41 ` [PATCH V4 04/12] PCI/TPH: Add pcie_enable_tph() to enable TPH Wei Huang
2024-09-13 11:35 ` Alejandro Lucero Palau
2024-08-22 20:41 ` [PATCH V4 05/12] PCI/TPH: Add pcie_disable_tph() to disable TPH Wei Huang
2024-08-22 20:41 ` [PATCH V4 06/12] PCI/TPH: Add pcie_tph_enabled() to check TPH state Wei Huang
2024-08-22 20:41 ` [PATCH V4 07/12] PCI/TPH: Add pcie_tph_set_st_entry() to set ST tag Wei Huang
2024-08-26 11:46 ` kernel test robot
2024-08-22 20:41 ` [PATCH V4 08/12] PCI/TPH: Add pcie_tph_get_cpu_st() to get " Wei Huang
2024-09-14 10:10 ` Alejandro Lucero Palau
2024-09-16 18:58 ` Wei Huang
2024-08-22 20:41 ` [PATCH V4 09/12] PCI/TPH: Add save/restore support for TPH Wei Huang
2024-09-04 20:11 ` Bjorn Helgaas
2024-08-22 20:41 ` [PATCH V4 10/12] PCI/TPH: Add pci=nostmode to force TPH No ST Mode Wei Huang
2024-08-22 20:41 ` [PATCH V4 11/12] bnxt_en: Add TPH support in BNXT driver Wei Huang
2024-08-26 20:22 ` Jakub Kicinski
2024-08-26 20:56 ` Andy Gospodarek
2024-08-26 22:49 ` Jakub Kicinski
2024-08-27 14:50 ` Andy Gospodarek
2024-08-27 19:05 ` Jakub Kicinski
2024-08-27 19:20 ` Michael Chan
2024-09-05 15:06 ` Bjorn Helgaas
2024-09-11 15:37 ` Alejandro Lucero Palau [this message]
2024-09-16 18:55 ` Wei Huang
2024-09-18 17:31 ` Alejandro Lucero Palau
2024-09-19 16:14 ` Wei Huang
2024-08-22 20:41 ` [PATCH V4 12/12] bnxt_en: Pass NQ ID to the FW when allocating RX/RX AGG rings Wei Huang
2024-09-03 22:42 ` [PATCH V4 00/12] PCIe TPH and cache direct injection support Wei Huang
2024-09-04 18:49 ` Bjorn Helgaas
2024-09-04 19:48 ` Wei Huang
2024-09-04 20:03 ` Bjorn Helgaas
2024-09-04 20:20 ` Bjorn Helgaas
2024-09-05 15:45 ` Wei Huang
2024-09-05 16:44 ` Bjorn Helgaas
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