[PATCH 0/9] Flatten USB Controller Nodes on IPQ SoCs

[PATCH 0/9] Flatten USB Controller Nodes on IPQ SoCs

[George Moussalem via B4 Relay]

Add property to select UTMI as reference clock for the DWC3 core to
calculate the right values for the period and frame length adjustment.

Flatten usb controller node and update to using latest bindings and
flattened driver approach.

In addition, set the right UTMI clock rate and override any clock
rate inherited from the bootloader.

I've split these patches from a larger patch set to add USB3 support on
IPQ5018 and IPQ5332 SoCs where these patches are required to ensure new
functionality is added to the new flattened driver and binding model.

link: https://lore.kernel.org/all/20260812-ipq5018-usb3-v2-0-8f355d7ff0ef@outlook.com/

Signed-off-by: George Moussalem <george.moussalem@outlook.com>
---
George Moussalem (9):
      dt-bindings: usb: qcom,snps-dwc3: Add ability to select UTMI as reference clock
      usb: dwc3: core: Allow glue layer to pass reference clock
      usb: dwc3: qcom: Add support for selecting UTMI as reference clock
      arm64: dts: qcom: ipq5018: Flatten usb controller node
      arm64: dts: qcom: ipq5332: Flatten usb controller node
      arm64: dts: qcom: ipq5424: Flatten usb controller nodes
      arm64: dts: qcom: ipq6018: Flatten usb controller nodes
      arm64: dts: qcom: ipq8074: Flatten usb controller nodes
      arm64: dts: qcom: ipq9574: Flatten usb controller node

 .../devicetree/bindings/usb/qcom,snps-dwc3.yaml    |   9 ++
 arch/arm64/boot/dts/qcom/ipq5018-rdp432-c2.dts     |   6 +-
 arch/arm64/boot/dts/qcom/ipq5018.dtsi              |  52 +++++-----
 arch/arm64/boot/dts/qcom/ipq5332-rdp468.dts        |   6 +-
 arch/arm64/boot/dts/qcom/ipq5332.dtsi              |  58 +++++------
 arch/arm64/boot/dts/qcom/ipq5424-rdp466.dts        |  12 +--
 arch/arm64/boot/dts/qcom/ipq5424.dtsi              |  89 ++++++++--------
 arch/arm64/boot/dts/qcom/ipq6018.dtsi              |  99 +++++++++---------
 arch/arm64/boot/dts/qcom/ipq8074.dtsi              | 112 ++++++++++-----------
 arch/arm64/boot/dts/qcom/ipq9574-rdp-common.dtsi   |   6 +-
 arch/arm64/boot/dts/qcom/ipq9574.dtsi              |  42 ++++----
 drivers/usb/dwc3/core.c                            |  12 +++
 drivers/usb/dwc3/core.h                            |   2 +
 drivers/usb/dwc3/dwc3-qcom.c                       |  14 +++
 drivers/usb/dwc3/glue.h                            |   2 +
 15 files changed, 257 insertions(+), 264 deletions(-)
---
base-commit: 4b18edbd8e70f7e6860d56370f13244896d0f95c
change-id: 20260825-ipq-flatten-usb-c7d7f15f3966

Best regards,
-- 
George Moussalem <george.moussalem@outlook.com>

[PATCH 1/9] dt-bindings: usb: qcom,snps-dwc3: Add ability to select UTMI as reference clock

[George Moussalem via B4 Relay]

From: George Moussalem <george.moussalem@outlook.com>

Add ability to select the UTMI clock as reference clock which is passed
by the glue layer to the DWC3 core to calculate the reference clock
period and frame length adjustment based on its clock rate.

In the flattened snsp-dwc3 model, it is currently not possible to pass a
reference clock that differs from the default since:
commit 613a2e655d4d ("usb: dwc3: core: Expose core driver as library")

This prevents moving chipsets such as IPQ5018, IPQ6018, IPQ5332, IPQ5424
and IPQ9574 with a reference clock rate different from 19.2 MHz from
moving to the flattened model.

The Qualcomm takes care of clock and resets management itself and sets
the ignore_clocks_and_resets flag in dwc3_probe_data to true, so the
core doesn't acquire the reference clock from the devicetree.

The existing DT property 'snps,quirk-ref-clk-period-ns' has been
deprecated.

So, add a property to select the UTMI clock used by many (if not all)
Qualcomm USB controllers as the reference clock.

Signed-off-by: George Moussalem <george.moussalem@outlook.com>
---
 Documentation/devicetree/bindings/usb/qcom,snps-dwc3.yaml | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/Documentation/devicetree/bindings/usb/qcom,snps-dwc3.yaml b/Documentation/devicetree/bindings/usb/qcom,snps-dwc3.yaml
index ea60f7220afe..aa263dfd42a1 100644
--- a/Documentation/devicetree/bindings/usb/qcom,snps-dwc3.yaml
+++ b/Documentation/devicetree/bindings/usb/qcom,snps-dwc3.yaml
@@ -155,6 +155,15 @@ properties:
       HS/FS/LS modes are supported.
     type: boolean
 
+  qcom,select-utmi-as-ref-clk:
+    description:
+      If present, pass the UTMI clock as the reference clock to the DWC3 core to
+      use its clock rate to calculate the reference clock period and frame
+      length adjustment in GUCTL and GFLADJ registers. This is needed when these
+      values based on the standard clock rate deviate from the hardware default
+      values. If not set, the hardware default values are used.
+    type: boolean
+
   wakeup-source: true
 
 required:

-- 
2.53.0

[PATCH 2/9] usb: dwc3: core: Allow glue layer to pass reference clock

[George Moussalem via B4 Relay]

From: George Moussalem <george.moussalem@outlook.com>

Add ability to pass a reference clock from the glue layer to the DWC3
core driver. The core calculates the reference clock period and frame
length adjustment based on the reference clock rate.

In the flattened snsp-dwc3 model, it is currently not possible to pass a
reference clock that differs from the default since:
commit 613a2e655d4d ("usb: dwc3: core: Expose core driver as library")

The new glue layers (incl. Qualcomm's) set the ignore_clocks_and_resets
flag in dwc3_probe_data to true, which disables the core driver's clock
management, thus it also doesn't acquire the reference clock from the
devicetree needed in dwc3_ref_clk_period.

There's an existing DT property 'snps,quirk-ref-clk-period-ns', but
that's been deprecated. In addition, basing the rate from the period is
often not accurate enough to derive the frame length adjustment value.

This prevents moving chipsets such as IPQ5018, IPQ6018, IPQ5332, IPQ5424
and IPQ9574 with a different reference clock rate from moving to the
flattened model.

So, add ability to set the reference clock in dwc3_probe_data, then
have the core obtain the clock rate and use that to calculate the
required period and frame length adjustment.

Signed-off-by: George Moussalem <george.moussalem@outlook.com>
---
 drivers/usb/dwc3/core.c | 12 ++++++++++++
 drivers/usb/dwc3/core.h |  2 ++
 drivers/usb/dwc3/glue.h |  2 ++
 3 files changed, 16 insertions(+)

diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
index fd5c2cd36c59..c52920148588 100644
--- a/drivers/usb/dwc3/core.c
+++ b/drivers/usb/dwc3/core.c
@@ -420,6 +420,10 @@ static void dwc3_ref_clk_period(struct dwc3 *dwc)
 	} else if (dwc->ref_clk_per) {
 		period = dwc->ref_clk_per;
 		rate = NSEC_PER_SEC / period;
+	} else if (dwc->ref_clk_rate) {
+		rate = dwc->ref_clk_rate;
+		period = NSEC_PER_SEC / rate;
+
 	} else {
 		return;
 	}
@@ -2332,6 +2336,14 @@ int dwc3_core_probe(const struct dwc3_probe_data *data)
 		ret = dwc3_get_clocks(dwc);
 		if (ret)
 			goto err_put_psy;
+	} else if (data->ref_clk) {
+		dwc->ref_clk_rate = clk_get_rate(data->ref_clk);
+		if (!dwc->ref_clk_rate) {
+			dev_err(dev,
+				"failed to get rate from ref clock provided by glue layer\n");
+			ret = -EINVAL;
+			goto err_put_psy;
+		}
 	}
 
 	ret = reset_control_deassert(dwc->reset);
diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h
index 608daeb7ef10..04b15defccf3 100644
--- a/drivers/usb/dwc3/core.h
+++ b/drivers/usb/dwc3/core.h
@@ -1032,6 +1032,7 @@ struct dwc3_glue_ops {
  * @regs_size: address space size
  * @fladj: frame length adjustment
  * @ref_clk_per: reference clock period configuration
+ * @ref_clk_rate: clock rate taken from reference clock provided by glue layer
  * @irq_gadget: peripheral controller's IRQ number
  * @otg_irq: IRQ number for OTG IRQs
  * @current_otg_role: current role of operation while using the OTG block
@@ -1261,6 +1262,7 @@ struct dwc3 {
 
 	u32			fladj;
 	u32			ref_clk_per;
+	unsigned long		ref_clk_rate;
 	u32			irq_gadget;
 	u32			otg_irq;
 	u32			current_otg_role;
diff --git a/drivers/usb/dwc3/glue.h b/drivers/usb/dwc3/glue.h
index d738e1739ae0..75c9612527a5 100644
--- a/drivers/usb/dwc3/glue.h
+++ b/drivers/usb/dwc3/glue.h
@@ -33,6 +33,7 @@ struct dwc3_properties {
  * @skip_core_init_mode: Skip the finial initialization of the target mode, as
  *		it must be managed by the glue
  * @properties: dwc3 software manage properties
+ * @ref_clk: optional reference clock for the DWC3 core
  */
 struct dwc3_probe_data {
 	struct dwc3 *dwc;
@@ -40,6 +41,7 @@ struct dwc3_probe_data {
 	bool ignore_clocks_and_resets;
 	bool skip_core_init_mode;
 	struct dwc3_properties properties;
+	struct clk *ref_clk;
 };
 
 /**

-- 
2.53.0

[PATCH 3/9] usb: dwc3: qcom: Add support for selecting UTMI as reference clock

[George Moussalem via B4 Relay]

From: George Moussalem <george.moussalem@outlook.com>

On many Qualcomm chipsets, the UTMI clock is used as the reference clock
(ex. IPQ5018, IPQ6018, and IPQ9574 and more). Since moving to the new
flattened snps-dwc3 model, it is no longer possible to pass the
reference clock to the dwc3 core driver.

The clock rate is used by dwc3 core to derive the reference clock period
and frame length adjusment. This is needed when the reference clock
deviates from the hardware default (typically 19.2MHz). Above mentioned
SoCs use different rates and, as such, the core initializes with the
wrong values which leads to non-functional USB operation.

Read the "qcom,select-utmi-as-ref-clk" property to determine if the UTMI
clock should be used as the reference clock. If so, set it as the
reference clock in the dwc3_probe_data structure.
The dwc3 core driver will then use this clock to derive the clock rate.

Signed-off-by: George Moussalem <george.moussalem@outlook.com>
---
 drivers/usb/dwc3/dwc3-qcom.c | 14 ++++++++++++++
 1 file changed, 14 insertions(+)

diff --git a/drivers/usb/dwc3/dwc3-qcom.c b/drivers/usb/dwc3/dwc3-qcom.c
index ac68b4218b56..17292517c594 100644
--- a/drivers/usb/dwc3/dwc3-qcom.c
+++ b/drivers/usb/dwc3/dwc3-qcom.c
@@ -617,6 +617,8 @@ static int dwc3_qcom_probe(struct platform_device *pdev)
 	int			ret;
 	bool			ignore_pipe_clk;
 	bool			wakeup_source;
+	bool			select_utmi_as_ref_clk;
+	struct clk		*ref_clk;
 
 	qcom = devm_kzalloc(&pdev->dev, sizeof(*qcom), GFP_KERNEL);
 	if (!qcom)
@@ -698,6 +700,18 @@ static int dwc3_qcom_probe(struct platform_device *pdev)
 			qcom->current_role = USB_ROLE_DEVICE;
 	}
 
+	select_utmi_as_ref_clk = device_property_read_bool(dev,
+					"qcom,select-utmi-as-ref-clk");
+	if (select_utmi_as_ref_clk) {
+		ref_clk = devm_clk_get_optional(dev, "mock_utmi");
+		if (IS_ERR(ref_clk)) {
+			ret = PTR_ERR(ref_clk);
+			dev_warn(dev, "failed to get ref clock: %d\n", ret);
+		} else {
+			probe_data.ref_clk = ref_clk;
+		}
+	}
+
 	qcom->dwc.glue_ops = &dwc3_qcom_glue_ops;
 
 	qcom->dwc.dev = dev;

-- 
2.53.0

[PATCH 4/9] arm64: dts: qcom: ipq5018: Flatten usb controller node

[George Moussalem via B4 Relay]

From: George Moussalem <george.moussalem@outlook.com>

Flatten usb controller node and update to using latest bindings and
flattened driver approach.

Add property to select UTMI as reference clock for the DWC3 core to
calculate the right values for the period and frame length adjustment.

In addition, set the right UTMI clock rate and override any clock
rate inherited from the bootloader.

Signed-off-by: George Moussalem <george.moussalem@outlook.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
---
 arch/arm64/boot/dts/qcom/ipq5018-rdp432-c2.dts |  6 +--
 arch/arm64/boot/dts/qcom/ipq5018.dtsi          | 52 ++++++++++++--------------
 2 files changed, 26 insertions(+), 32 deletions(-)

diff --git a/arch/arm64/boot/dts/qcom/ipq5018-rdp432-c2.dts b/arch/arm64/boot/dts/qcom/ipq5018-rdp432-c2.dts
index 33eef92b19b1..8efb2b21ed9e 100644
--- a/arch/arm64/boot/dts/qcom/ipq5018-rdp432-c2.dts
+++ b/arch/arm64/boot/dts/qcom/ipq5018-rdp432-c2.dts
@@ -110,11 +110,9 @@ data-pins {
 };
 
 &usb {
-	status = "okay";
-};
-
-&usb_dwc {
 	dr_mode = "host";
+
+	status = "okay";
 };
 
 &usbphy0 {
diff --git a/arch/arm64/boot/dts/qcom/ipq5018.dtsi b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
index 4fc627b47fe7..71834606535e 100644
--- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
@@ -580,16 +580,9 @@ qpic_nand: spi@79b0000 {
 			status = "disabled";
 		};
 
-		usb: usb@8af8800 {
-			compatible = "qcom,ipq5018-dwc3", "qcom,dwc3";
-			reg = <0x08af8800 0x400>;
-
-			interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
-			interrupt-names = "pwr_event",
-					  "dp_hs_phy_irq",
-					  "dm_hs_phy_irq";
+		usb: usb@8a00000 {
+			compatible = "qcom,ipq5018-dwc3", "qcom,snps-dwc3";
+			reg = <0x08a00000 0xfc100>;
 
 			clocks = <&gcc GCC_USB0_MASTER_CLK>,
 				 <&gcc GCC_SYS_NOC_USB0_AXI_CLK>,
@@ -599,30 +592,33 @@ usb: usb@8af8800 {
 				      "iface",
 				      "sleep",
 				      "mock_utmi";
+			assigned-clocks = <&gcc GCC_USB0_MOCK_UTMI_CLK>;
+			assigned-clock-rates = <60000000>;
+
+			interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "dwc_usb3",
+					  "pwr_event",
+					  "dp_hs_phy_irq",
+					  "dm_hs_phy_irq";
 
 			resets = <&gcc GCC_USB0_BCR>;
 
+			phys = <&usbphy0>;
+			phy-names = "usb2-phy";
+
 			qcom,select-utmi-as-pipe-clk;
-			#address-cells = <1>;
-			#size-cells = <1>;
-			ranges;
+			qcom,select-utmi-as-ref-clk;
 
-			status = "disabled";
+			tx-fifo-resize;
+			snps,is-utmi-l1-suspend;
+			snps,hird-threshold = /bits/ 8 <0x0>;
+			snps,dis_u2_susphy_quirk;
+			snps,dis_u3_susphy_quirk;
 
-			usb_dwc: usb@8a00000 {
-				compatible = "snps,dwc3";
-				reg = <0x08a00000 0xe000>;
-				clocks = <&gcc GCC_USB0_MOCK_UTMI_CLK>;
-				clock-names = "ref";
-				interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
-				phy-names = "usb2-phy";
-				phys = <&usbphy0>;
-				tx-fifo-resize;
-				snps,is-utmi-l1-suspend;
-				snps,hird-threshold = /bits/ 8 <0x0>;
-				snps,dis_u2_susphy_quirk;
-				snps,dis_u3_susphy_quirk;
-			};
+			status = "disabled";
 		};
 
 		intc: interrupt-controller@b000000 {

-- 
2.53.0

[PATCH 5/9] arm64: dts: qcom: ipq5332: Flatten usb controller node

[George Moussalem via B4 Relay]

From: George Moussalem <george.moussalem@outlook.com>

Flatten usb controller node and update to using latest bindings and
flattened driver approach.

Add property to select UTMI as reference clock for the DWC3 core to
calculate the right values for the period and frame length adjustment.

In addition, set the right UTMI clock rate and override any clock rate
inherited from the bootloader.

Signed-off-by: George Moussalem <george.moussalem@outlook.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
---
 arch/arm64/boot/dts/qcom/ipq5332-rdp468.dts |  6 +--
 arch/arm64/boot/dts/qcom/ipq5332.dtsi       | 58 ++++++++++++++---------------
 2 files changed, 29 insertions(+), 35 deletions(-)

diff --git a/arch/arm64/boot/dts/qcom/ipq5332-rdp468.dts b/arch/arm64/boot/dts/qcom/ipq5332-rdp468.dts
index c224ffc65b08..25a70cd884c0 100644
--- a/arch/arm64/boot/dts/qcom/ipq5332-rdp468.dts
+++ b/arch/arm64/boot/dts/qcom/ipq5332-rdp468.dts
@@ -90,11 +90,9 @@ spi_0_cs_pins: spi-0-cs-state {
 };
 
 &usb {
-	status = "okay";
-};
-
-&usb_dwc {
 	dr_mode = "host";
+
+	status = "okay";
 };
 
 &usbphy0 {
diff --git a/arch/arm64/boot/dts/qcom/ipq5332.dtsi b/arch/arm64/boot/dts/qcom/ipq5332.dtsi
index 74d9de8d7641..87579a6b0e30 100644
--- a/arch/arm64/boot/dts/qcom/ipq5332.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq5332.dtsi
@@ -493,16 +493,9 @@ qpic_nand: spi@79b0000 {
 			status = "disabled";
 		};
 
-		usb: usb@8af8800 {
-			compatible = "qcom,ipq5332-dwc3", "qcom,dwc3";
-			reg = <0x08af8800 0x400>;
-
-			interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
-			interrupt-names = "pwr_event",
-					  "dp_hs_phy_irq",
-					  "dm_hs_phy_irq";
+		usb: usb@8a00000 {
+			compatible = "qcom,ipq5332-dwc3", "qcom,snps-dwc3";
+			reg = <0x08a00000 0xfc100>;
 
 			clocks = <&gcc GCC_USB0_MASTER_CLK>,
 				 <&gcc GCC_USB0_SLEEP_CLK>,
@@ -510,34 +503,37 @@ usb: usb@8af8800 {
 			clock-names = "core",
 				      "sleep",
 				      "mock_utmi";
+			assigned-clocks = <&gcc GCC_USB0_MOCK_UTMI_CLK>;
+			assigned-clock-rates = <60000000>;
 
-			resets = <&gcc GCC_USB_BCR>;
-
-			qcom,select-utmi-as-pipe-clk;
+			interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "dwc_usb3",
+					  "pwr_event",
+					  "dp_hs_phy_irq",
+					  "dm_hs_phy_irq";
 
-			#address-cells = <1>;
-			#size-cells = <1>;
-			ranges;
 			interconnects = <&gcc MASTER_SNOC_USB &gcc SLAVE_SNOC_USB>,
 					<&gcc MASTER_SNOC_USB &gcc SLAVE_SNOC_USB>;
 			interconnect-names = "usb-ddr", "apps-usb";
 
-			status = "disabled";
+			resets = <&gcc GCC_USB_BCR>;
 
-			usb_dwc: usb@8a00000 {
-				compatible = "snps,dwc3";
-				reg = <0x08a00000 0xe000>;
-				clocks = <&gcc GCC_USB0_MOCK_UTMI_CLK>;
-				clock-names = "ref";
-				interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
-				phy-names = "usb2-phy";
-				phys = <&usbphy0>;
-				tx-fifo-resize;
-				snps,is-utmi-l1-suspend;
-				snps,hird-threshold = /bits/ 8 <0x0>;
-				snps,dis_u2_susphy_quirk;
-				snps,dis_u3_susphy_quirk;
-			};
+			phys = <&usbphy0>;
+			phy-names = "usb2-phy";
+
+			qcom,select-utmi-as-pipe-clk;
+			qcom,select-utmi-as-ref-clk;
+
+			tx-fifo-resize;
+			snps,is-utmi-l1-suspend;
+			snps,hird-threshold = /bits/ 8 <0x0>;
+			snps,dis_u2_susphy_quirk;
+			snps,dis_u3_susphy_quirk;
+
+			status = "disabled";
 		};
 
 		intc: interrupt-controller@b000000 {

-- 
2.53.0

[PATCH 6/9] arm64: dts: qcom: ipq5424: Flatten usb controller nodes

[George Moussalem via B4 Relay]

From: George Moussalem <george.moussalem@outlook.com>

Flatten usb controller nodes and update to using latest bindings and
flattened driver approach.

Add property to both USB controller nodes to select UTMI as reference
clock for the DWC3 core to calculate the right values for the period and
frame length adjustment.

Signed-off-by: George Moussalem <george.moussalem@outlook.com>
---
 arch/arm64/boot/dts/qcom/ipq5424-rdp466.dts | 12 ++--
 arch/arm64/boot/dts/qcom/ipq5424.dtsi       | 89 +++++++++++++----------------
 2 files changed, 44 insertions(+), 57 deletions(-)

diff --git a/arch/arm64/boot/dts/qcom/ipq5424-rdp466.dts b/arch/arm64/boot/dts/qcom/ipq5424-rdp466.dts
index be8657239c46..dfd6a124686a 100644
--- a/arch/arm64/boot/dts/qcom/ipq5424-rdp466.dts
+++ b/arch/arm64/boot/dts/qcom/ipq5424-rdp466.dts
@@ -74,14 +74,6 @@ vreg_misc_0p925: regulator-usb-0p925 {
 	};
 };
 
-&dwc_0 {
-	dr_mode = "host";
-};
-
-&dwc_1 {
-	dr_mode = "host";
-};
-
 &pcie2 {
 	pinctrl-0 = <&pcie2_default_state>;
 	pinctrl-names = "default";
@@ -282,10 +274,14 @@ &uart1 {
 };
 
 &usb2 {
+	dr_mode = "host";
+
 	status = "okay";
 };
 
 &usb3 {
+	dr_mode = "host";
+
 	status = "okay";
 };
 
diff --git a/arch/arm64/boot/dts/qcom/ipq5424.dtsi b/arch/arm64/boot/dts/qcom/ipq5424.dtsi
index 702061e16a58..648f95d70448 100644
--- a/arch/arm64/boot/dts/qcom/ipq5424.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq5424.dtsi
@@ -639,12 +639,9 @@ qusb_phy_1: phy@71000 {
 			status = "disabled";
 		};
 
-		usb2: usb2@1ef8800 {
-			compatible = "qcom,ipq5424-dwc3", "qcom,dwc3";
-			reg = <0 0x01ef8800 0 0x400>;
-			#address-cells = <2>;
-			#size-cells = <2>;
-			ranges;
+		usb2: usb2@1e00000 {
+			compatible = "qcom,ipq5424-dwc3", "qcom,snps-dwc3";
+			reg = <0 0x01e00000 0 0xfc100>;
 
 			clocks = <&gcc GCC_USB1_MASTER_CLK>,
 				 <&gcc GCC_USB1_SLEEP_CLK>,
@@ -663,33 +660,32 @@ usb2: usb2@1ef8800 {
 			assigned-clock-rates = <200000000>,
 					       <24000000>;
 
-			interrupts-extended = <&intc GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
+			interrupts-extended = <&intc GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
+					      <&intc GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
 					      <&intc GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
 					      <&intc GIC_SPI 387 IRQ_TYPE_LEVEL_HIGH>,
 					      <&intc GIC_SPI 388 IRQ_TYPE_LEVEL_HIGH>;
-			interrupt-names = "pwr_event",
+			interrupt-names = "dwc_usb3",
+					  "pwr_event",
 					  "qusb2_phy",
 					  "dm_hs_phy_irq",
 					  "dp_hs_phy_irq";
 
 			resets = <&gcc GCC_USB1_BCR>;
+
+			phys = <&qusb_phy_1>;
+			phy-names = "usb2-phy";
+
 			qcom,select-utmi-as-pipe-clk;
-			status = "disabled";
+			qcom,select-utmi-as-ref-clk;
 
-			dwc_1: usb@1e00000 {
-				compatible = "snps,dwc3";
-				reg = <0 0x01e00000 0 0xe000>;
-				clocks = <&gcc GCC_USB1_MOCK_UTMI_CLK>;
-				clock-names = "ref";
-				interrupts = <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>;
-				phys = <&qusb_phy_1>;
-				phy-names = "usb2-phy";
-				tx-fifo-resize;
-				snps,is-utmi-l1-suspend;
-				snps,hird-threshold = /bits/ 8 <0x0>;
-				snps,dis_u2_susphy_quirk;
-				snps,dis_u3_susphy_quirk;
-			};
+			tx-fifo-resize;
+			snps,is-utmi-l1-suspend;
+			snps,hird-threshold = /bits/ 8 <0x0>;
+			snps,dis_u2_susphy_quirk;
+			snps,dis_u3_susphy_quirk;
+
+			status = "disabled";
 		};
 
 		qusb_phy_0: phy@7b000 {
@@ -730,13 +726,9 @@ ssphy_0: phy@7d000 {
 			status = "disabled";
 		};
 
-		usb3: usb3@8af8800 {
-			compatible = "qcom,ipq5424-dwc3", "qcom,dwc3";
-			reg = <0 0x08af8800 0 0x400>;
-
-			#address-cells = <2>;
-			#size-cells = <2>;
-			ranges;
+		usb3: usb3@8a00000 {
+			compatible = "qcom,ipq5424-dwc3", "qcom,snps-dwc3";
+			reg = <0 0x08a00000 0 0xfc100>;
 
 			clocks = <&gcc GCC_USB0_MASTER_CLK>,
 				 <&gcc GCC_USB0_SLEEP_CLK>,
@@ -755,34 +747,33 @@ usb3: usb3@8af8800 {
 			assigned-clock-rates = <200000000>,
 					       <24000000>;
 
-			interrupts-extended = <&intc GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>,
+			interrupts-extended = <&intc GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>,
+					      <&intc GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>,
 					      <&intc GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>,
 					      <&intc GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
 					      <&intc GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>;
-			interrupt-names = "pwr_event",
+			interrupt-names = "dwc_usb3",
+					  "pwr_event",
 					  "qusb2_phy",
 					  "dm_hs_phy_irq",
 					  "dp_hs_phy_irq";
 
 			resets = <&gcc GCC_USB_BCR>;
-			status = "disabled";
 
-			dwc_0: usb@8a00000 {
-				compatible = "snps,dwc3";
-				reg = <0 0x08a00000 0 0xcd00>;
-				clocks = <&gcc GCC_USB0_MOCK_UTMI_CLK>;
-				clock-names = "ref";
-				interrupts = <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>;
-				phys = <&qusb_phy_0>, <&ssphy_0>;
-				phy-names = "usb2-phy", "usb3-phy";
-				tx-fifo-resize;
-				snps,is-utmi-l1-suspend;
-				snps,hird-threshold = /bits/ 8 <0x0>;
-				snps,dis_u2_susphy_quirk;
-				snps,dis_u3_susphy_quirk;
-				snps,dis-u1-entry-quirk;
-				snps,dis-u2-entry-quirk;
-			};
+			phys = <&qusb_phy_0>, <&ssphy_0>;
+			phy-names = "usb2-phy", "usb3-phy";
+
+			qcom,select-utmi-as-ref-clk;
+
+			tx-fifo-resize;
+			snps,is-utmi-l1-suspend;
+			snps,hird-threshold = /bits/ 8 <0x0>;
+			snps,dis_u2_susphy_quirk;
+			snps,dis_u3_susphy_quirk;
+			snps,dis-u1-entry-quirk;
+			snps,dis-u2-entry-quirk;
+
+			status = "disabled";
 		};
 
 		timer@f420000 {

-- 
2.53.0

[PATCH 7/9] arm64: dts: qcom: ipq6018: Flatten usb controller nodes

[George Moussalem via B4 Relay]

From: George Moussalem <george.moussalem@outlook.com>

Flatten usb controller nodes and update to using latest bindings and
flattened driver approach.

This SoC has two USB controllers of which the USB3 node had a ref clock
populated in the DWC3 child node. Add property to the USB3 node only to
select UTMI as reference clock for the DWC3 core to calculate the right
values for the period and frame length adjustment.

Signed-off-by: George Moussalem <george.moussalem@outlook.com>
---
 arch/arm64/boot/dts/qcom/ipq6018.dtsi | 99 ++++++++++++++++-------------------
 1 file changed, 46 insertions(+), 53 deletions(-)

diff --git a/arch/arm64/boot/dts/qcom/ipq6018.dtsi b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
index 0701517275d4..4b39616dd899 100644
--- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
@@ -423,12 +423,10 @@ pwm: pwm@1941010 {
 			status = "disabled";
 		};
 
-		usb2: usb@70f8800 {
-			compatible = "qcom,ipq6018-dwc3", "qcom,dwc3";
-			reg = <0x0 0x070f8800 0x0 0x400>;
-			#address-cells = <2>;
-			#size-cells = <2>;
-			ranges;
+		usb2: usb@7000000 {
+			compatible = "qcom,ipq6018-dwc3", "qcom,snps-dwc3";
+			reg = <0x0 0x07000000 0x0 0xfc100>;
+
 			clocks = <&gcc GCC_USB1_MASTER_CLK>,
 				 <&gcc GCC_USB1_SLEEP_CLK>,
 				 <&gcc GCC_USB1_MOCK_UTMI_CLK>;
@@ -441,27 +439,26 @@ usb2: usb@70f8800 {
 			assigned-clock-rates = <133330000>,
 					       <24000000>;
 
-			interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
+			interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
 				     <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
-			interrupt-names = "pwr_event",
+			interrupt-names = "dwc_usb3",
+					  "pwr_event",
 					  "qusb2_phy";
 
 			resets = <&gcc GCC_USB1_BCR>;
-			status = "disabled";
 
-			dwc_1: usb@7000000 {
-				compatible = "snps,dwc3";
-				reg = <0x0 0x07000000 0x0 0xcd00>;
-				interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
-				phys = <&qusb_phy_1>;
-				phy-names = "usb2-phy";
-				tx-fifo-resize;
-				snps,is-utmi-l1-suspend;
-				snps,hird-threshold = /bits/ 8 <0x0>;
-				snps,dis_u2_susphy_quirk;
-				snps,dis_u3_susphy_quirk;
-				dr_mode = "host";
-			};
+			phys = <&qusb_phy_1>;
+			phy-names = "usb2-phy";
+
+			tx-fifo-resize;
+			snps,is-utmi-l1-suspend;
+			snps,hird-threshold = /bits/ 8 <0x0>;
+			snps,dis_u2_susphy_quirk;
+			snps,dis_u3_susphy_quirk;
+			dr_mode = "host";
+
+			status = "disabled";
 		};
 
 		sdhc: mmc@7804000 {
@@ -669,21 +666,18 @@ qpic_nand: nand-controller@79b0000 {
 			status = "disabled";
 		};
 
-		usb3: usb@8af8800 {
-			compatible = "qcom,ipq6018-dwc3", "qcom,dwc3";
-			reg = <0x0 0x08af8800 0x0 0x400>;
-			#address-cells = <2>;
-			#size-cells = <2>;
-			ranges;
+		usb3: usb@8a00000 {
+			compatible = "qcom,ipq6018-dwc3", "qcom,snps-dwc3";
+			reg = <0x0 0x08a00000 0x0 0xfc100>;
 
 			clocks = <&gcc GCC_SYS_NOC_USB0_AXI_CLK>,
-				<&gcc GCC_USB0_MASTER_CLK>,
-				<&gcc GCC_USB0_SLEEP_CLK>,
-				<&gcc GCC_USB0_MOCK_UTMI_CLK>;
+				 <&gcc GCC_USB0_MASTER_CLK>,
+				 <&gcc GCC_USB0_SLEEP_CLK>,
+				 <&gcc GCC_USB0_MOCK_UTMI_CLK>;
 			clock-names = "cfg_noc",
-				"core",
-				"sleep",
-				"mock_utmi";
+				      "core",
+				      "sleep",
+				      "mock_utmi";
 
 			assigned-clocks = <&gcc GCC_SYS_NOC_USB0_AXI_CLK>,
 					  <&gcc GCC_USB0_MASTER_CLK>,
@@ -692,32 +686,31 @@ usb3: usb@8af8800 {
 					       <133330000>,
 					       <24000000>;
 
-			interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
+			interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
 				     <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
 				     <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
-			interrupt-names = "pwr_event",
+			interrupt-names = "dwc_usb3",
+					  "pwr_event",
 					  "qusb2_phy",
 					  "ss_phy_irq";
 
 			resets = <&gcc GCC_USB0_BCR>;
-			status = "disabled";
 
-			dwc_0: usb@8a00000 {
-				compatible = "snps,dwc3";
-				reg = <0x0 0x08a00000 0x0 0xcd00>;
-				interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
-				phys = <&qusb_phy_0>, <&ssphy_0>;
-				phy-names = "usb2-phy", "usb3-phy";
-				clocks = <&xo>;
-				clock-names = "ref";
-				tx-fifo-resize;
-				snps,parkmode-disable-ss-quirk;
-				snps,is-utmi-l1-suspend;
-				snps,hird-threshold = /bits/ 8 <0x0>;
-				snps,dis_u2_susphy_quirk;
-				snps,dis_u3_susphy_quirk;
-				dr_mode = "host";
-			};
+			phys = <&qusb_phy_0>, <&ssphy_0>;
+			phy-names = "usb2-phy", "usb3-phy";
+
+			qcom,select-utmi-as-ref-clk;
+
+			tx-fifo-resize;
+			snps,parkmode-disable-ss-quirk;
+			snps,is-utmi-l1-suspend;
+			snps,hird-threshold = /bits/ 8 <0x0>;
+			snps,dis_u2_susphy_quirk;
+			snps,dis_u3_susphy_quirk;
+			dr_mode = "host";
+
+			status = "disabled";
 		};
 
 		intc: interrupt-controller@b000000 {

-- 
2.53.0

[PATCH 8/9] arm64: dts: qcom: ipq8074: Flatten usb controller nodes

[George Moussalem via B4 Relay]

From: George Moussalem <george.moussalem@outlook.com>

Flatten usb controller nodes and update to using latest bindings and
flattened driver approach.

In addition, fix indentation of properties in both nodes.

Signed-off-by: George Moussalem <george.moussalem@outlook.com>
---
 arch/arm64/boot/dts/qcom/ipq8074.dtsi | 112 ++++++++++++++++------------------
 1 file changed, 52 insertions(+), 60 deletions(-)

diff --git a/arch/arm64/boot/dts/qcom/ipq8074.dtsi b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
index 75a5ae30d966..d4a86b3815f2 100644
--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
@@ -625,104 +625,96 @@ qpic_nand: nand-controller@79b0000 {
 			status = "disabled";
 		};
 
-		usb_0: usb@8af8800 {
-			compatible = "qcom,ipq8074-dwc3", "qcom,dwc3";
-			reg = <0x08af8800 0x400>;
-			#address-cells = <1>;
-			#size-cells = <1>;
-			ranges;
+		usb_0: usb@8a00000 {
+			compatible = "qcom,ipq8074-dwc3", "qcom,snps-dwc3";
+			reg = <0x08a00000 0xfc100>;
 
 			clocks = <&gcc GCC_SYS_NOC_USB0_AXI_CLK>,
-				<&gcc GCC_USB0_MASTER_CLK>,
-				<&gcc GCC_USB0_SLEEP_CLK>,
-				<&gcc GCC_USB0_MOCK_UTMI_CLK>;
+				 <&gcc GCC_USB0_MASTER_CLK>,
+				 <&gcc GCC_USB0_SLEEP_CLK>,
+				 <&gcc GCC_USB0_MOCK_UTMI_CLK>;
 			clock-names = "cfg_noc",
-				"core",
-				"sleep",
-				"mock_utmi";
+				      "core",
+				      "sleep",
+				      "mock_utmi";
 
 			assigned-clocks = <&gcc GCC_SYS_NOC_USB0_AXI_CLK>,
 					  <&gcc GCC_USB0_MASTER_CLK>,
 					  <&gcc GCC_USB0_MOCK_UTMI_CLK>;
 			assigned-clock-rates = <133330000>,
-						<133330000>,
-						<19200000>;
+					       <133330000>,
+					       <19200000>;
 
-			interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
+			interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
 				     <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
 				     <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
-			interrupt-names = "pwr_event",
+			interrupt-names = "dwc_usb3",
+					  "pwr_event",
 					  "qusb2_phy",
 					  "ss_phy_irq";
 
 			power-domains = <&gcc USB0_GDSC>;
 
+			phys = <&qusb_phy_0>, <&ssphy_0>;
+			phy-names = "usb2-phy", "usb3-phy";
+
+			snps,parkmode-disable-ss-quirk;
+			snps,is-utmi-l1-suspend;
+			snps,hird-threshold = /bits/ 8 <0x0>;
+			snps,dis_u2_susphy_quirk;
+			snps,dis_u3_susphy_quirk;
+			dr_mode = "host";
+
 			resets = <&gcc GCC_USB0_BCR>;
-			status = "disabled";
 
-			dwc_0: usb@8a00000 {
-				compatible = "snps,dwc3";
-				reg = <0x8a00000 0xcd00>;
-				interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
-				phys = <&qusb_phy_0>, <&ssphy_0>;
-				phy-names = "usb2-phy", "usb3-phy";
-				snps,parkmode-disable-ss-quirk;
-				snps,is-utmi-l1-suspend;
-				snps,hird-threshold = /bits/ 8 <0x0>;
-				snps,dis_u2_susphy_quirk;
-				snps,dis_u3_susphy_quirk;
-				dr_mode = "host";
-			};
+			status = "disabled";
 		};
 
-		usb_1: usb@8cf8800 {
-			compatible = "qcom,ipq8074-dwc3", "qcom,dwc3";
-			reg = <0x08cf8800 0x400>;
-			#address-cells = <1>;
-			#size-cells = <1>;
-			ranges;
+		usb_1: usb@8c00000 {
+			compatible = "qcom,ipq8074-dwc3", "qcom,snps-dwc3";
+			reg = <0x08c00000 0xfc100>;
 
 			clocks = <&gcc GCC_SYS_NOC_USB1_AXI_CLK>,
-				<&gcc GCC_USB1_MASTER_CLK>,
-				<&gcc GCC_USB1_SLEEP_CLK>,
-				<&gcc GCC_USB1_MOCK_UTMI_CLK>;
+				 <&gcc GCC_USB1_MASTER_CLK>,
+				 <&gcc GCC_USB1_SLEEP_CLK>,
+				 <&gcc GCC_USB1_MOCK_UTMI_CLK>;
 			clock-names = "cfg_noc",
-				"core",
-				"sleep",
-				"mock_utmi";
+				      "core",
+				      "sleep",
+				      "mock_utmi";
 
 			assigned-clocks = <&gcc GCC_SYS_NOC_USB1_AXI_CLK>,
 					  <&gcc GCC_USB1_MASTER_CLK>,
 					  <&gcc GCC_USB1_MOCK_UTMI_CLK>;
 			assigned-clock-rates = <133330000>,
-						<133330000>,
-						<19200000>;
+					       <133330000>,
+					       <19200000>;
 
-			interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
+			interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
 				     <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
 				     <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
-			interrupt-names = "pwr_event",
+			interrupt-names = "dwc_usb3",
+					  "pwr_event",
 					  "qusb2_phy",
 					  "ss_phy_irq";
 
 			power-domains = <&gcc USB1_GDSC>;
 
+			phys = <&qusb_phy_1>, <&ssphy_1>;
+			phy-names = "usb2-phy", "usb3-phy";
+
+			snps,parkmode-disable-ss-quirk;
+			snps,is-utmi-l1-suspend;
+			snps,hird-threshold = /bits/ 8 <0x0>;
+			snps,dis_u2_susphy_quirk;
+			snps,dis_u3_susphy_quirk;
+			dr_mode = "host";
+
 			resets = <&gcc GCC_USB1_BCR>;
-			status = "disabled";
 
-			dwc_1: usb@8c00000 {
-				compatible = "snps,dwc3";
-				reg = <0x8c00000 0xcd00>;
-				interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
-				phys = <&qusb_phy_1>, <&ssphy_1>;
-				phy-names = "usb2-phy", "usb3-phy";
-				snps,parkmode-disable-ss-quirk;
-				snps,is-utmi-l1-suspend;
-				snps,hird-threshold = /bits/ 8 <0x0>;
-				snps,dis_u2_susphy_quirk;
-				snps,dis_u3_susphy_quirk;
-				dr_mode = "host";
-			};
+			status = "disabled";
 		};
 
 		intc: interrupt-controller@b000000 {

-- 
2.53.0

[PATCH 9/9] arm64: dts: qcom: ipq9574: Flatten usb controller node

[George Moussalem via B4 Relay]

From: George Moussalem <george.moussalem@outlook.com>

Flatten usb controller nodes and update to using latest bindings and
flattened driver approach.

Add property to the USB node to select UTMI as reference clock for the
DWC3 core to calculate the right values for the period and frame length
adjustment.

Signed-off-by: George Moussalem <george.moussalem@outlook.com>
---
 arch/arm64/boot/dts/qcom/ipq9574-rdp-common.dtsi |  6 ++--
 arch/arm64/boot/dts/qcom/ipq9574.dtsi            | 42 +++++++++++-------------
 2 files changed, 21 insertions(+), 27 deletions(-)

diff --git a/arch/arm64/boot/dts/qcom/ipq9574-rdp-common.dtsi b/arch/arm64/boot/dts/qcom/ipq9574-rdp-common.dtsi
index 62877b46f9b3..0d06a838c233 100644
--- a/arch/arm64/boot/dts/qcom/ipq9574-rdp-common.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq9574-rdp-common.dtsi
@@ -252,10 +252,6 @@ flash@0 {
 	};
 };
 
-&usb_0_dwc3 {
-	dr_mode = "host";
-};
-
 &usb_0_qmpphy {
 	vdda-pll-supply = <&mp5496_l5>;
 	vdda-phy-supply = <&regulator_fixed_0p925>;
@@ -272,6 +268,8 @@ &usb_0_qusbphy {
 };
 
 &usb3 {
+	dr_mode = "host";
+
 	status = "okay";
 };
 
diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
index 5a5bda5f21a1..b56ba76e8b54 100644
--- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
@@ -756,12 +756,9 @@ usb_0_qmpphy: phy@7d000 {
 			status = "disabled";
 		};
 
-		usb3: usb@8af8800 {
-			compatible = "qcom,ipq9574-dwc3", "qcom,dwc3";
-			reg = <0x08af8800 0x400>;
-			#address-cells = <1>;
-			#size-cells = <1>;
-			ranges;
+		usb3: usb@8a00000 {
+			compatible = "qcom,ipq9574-dwc3", "qcom,snps-dwc3";
+			reg = <0x08a00000 0xfc100>;
 
 			clocks = <&gcc GCC_SNOC_USB_CLK>,
 				 <&gcc GCC_USB0_MASTER_CLK>,
@@ -780,32 +777,31 @@ usb3: usb@8af8800 {
 			assigned-clock-rates = <200000000>,
 					       <24000000>;
 
-			interrupts-extended = <&intc GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
+			interrupts-extended = <&intc GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
+					      <&intc GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
 					      <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
 					      <&intc GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
 					      <&intc GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
-			interrupt-names = "pwr_event",
+			interrupt-names = "dwc_usb3",
+					  "pwr_event",
 					  "qusb2_phy",
 					  "dm_hs_phy_irq",
 					  "dp_hs_phy_irq";
 
 			resets = <&gcc GCC_USB_BCR>;
-			status = "disabled";
 
-			usb_0_dwc3: usb@8a00000 {
-				compatible = "snps,dwc3";
-				reg = <0x8a00000 0xcd00>;
-				clocks = <&gcc GCC_USB0_MOCK_UTMI_CLK>;
-				clock-names = "ref";
-				interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
-				phys = <&usb_0_qusbphy>, <&usb_0_qmpphy>;
-				phy-names = "usb2-phy", "usb3-phy";
-				tx-fifo-resize;
-				snps,is-utmi-l1-suspend;
-				snps,hird-threshold = /bits/ 8 <0x0>;
-				snps,dis_u2_susphy_quirk;
-				snps,dis_u3_susphy_quirk;
-			};
+			phys = <&usb_0_qusbphy>, <&usb_0_qmpphy>;
+			phy-names = "usb2-phy", "usb3-phy";
+
+			qcom,select-utmi-as-ref-clk;
+
+			tx-fifo-resize;
+			snps,is-utmi-l1-suspend;
+			snps,hird-threshold = /bits/ 8 <0x0>;
+			snps,dis_u2_susphy_quirk;
+			snps,dis_u3_susphy_quirk;
+
+			status = "disabled";
 		};
 
 		intc: interrupt-controller@b000000 {

-- 
2.53.0

Re: [PATCH 3/9] usb: dwc3: qcom: Add support for selecting UTMI as reference clock

[Konrad Dybcio]

On 8/25/26 12:42 PM, George Moussalem via B4 Relay wrote:
> From: George Moussalem <george.moussalem@outlook.com>
> 
> On many Qualcomm chipsets, the UTMI clock is used as the reference clock
> (ex. IPQ5018, IPQ6018, and IPQ9574 and more). Since moving to the new
> flattened snps-dwc3 model, it is no longer possible to pass the
> reference clock to the dwc3 core driver.
> 
> The clock rate is used by dwc3 core to derive the reference clock period
> and frame length adjusment. This is needed when the reference clock
> deviates from the hardware default (typically 19.2MHz). Above mentioned
> SoCs use different rates and, as such, the core initializes with the
> wrong values which leads to non-functional USB operation.
> 
> Read the "qcom,select-utmi-as-ref-clk" property to determine if the UTMI
> clock should be used as the reference clock. If so, set it as the
> reference clock in the dwc3_probe_data structure.
> The dwc3 core driver will then use this clock to derive the clock rate.
> 
> Signed-off-by: George Moussalem <george.moussalem@outlook.com>
> ---

There's a shorter patch in flight:

https://lore.kernel.org/linux-arm-msm/20260825-ctrl-v1-2-609e2291814d@oss.qualcomm.com/

Konrad

Re: [PATCH 3/9] usb: dwc3: qcom: Add support for selecting UTMI as reference clock

[George Moussalem]

On 8/26/26 13:18, Konrad Dybcio wrote:
> On 8/25/26 12:42 PM, George Moussalem via B4 Relay wrote:
>> From: George Moussalem <george.moussalem@outlook.com>
>>
>> On many Qualcomm chipsets, the UTMI clock is used as the reference clock
>> (ex. IPQ5018, IPQ6018, and IPQ9574 and more). Since moving to the new
>> flattened snps-dwc3 model, it is no longer possible to pass the
>> reference clock to the dwc3 core driver.
>>
>> The clock rate is used by dwc3 core to derive the reference clock period
>> and frame length adjusment. This is needed when the reference clock
>> deviates from the hardware default (typically 19.2MHz). Above mentioned
>> SoCs use different rates and, as such, the core initializes with the
>> wrong values which leads to non-functional USB operation.
>>
>> Read the "qcom,select-utmi-as-ref-clk" property to determine if the UTMI
>> clock should be used as the reference clock. If so, set it as the
>> reference clock in the dwc3_probe_data structure.
>> The dwc3 core driver will then use this clock to derive the clock rate.
>>
>> Signed-off-by: George Moussalem <george.moussalem@outlook.com>
>> ---
> 
> There's a shorter patch in flight:
> 
> https://lore.kernel.org/linux-arm-msm/20260825-ctrl-v1-2-609e2291814d@oss.qualcomm.com/

I'm aware and have discussed that with Varada. My concerns are that
directly setting qcom->dwc->ref_clk from the glue layer is a layering
violation. This patch passes it to the DWC3 core via the probe_data struct.

In addition, if ignore_clocks_and_resets is set in the glue layer (which
is the case for qcom's and others), setting the dwc->ref_clk makes it
become managed by the core which is the opposite of what the
ignore_clocks_and_resets property is there for.

> 
> Konrad

George

Re: [PATCH 3/9] usb: dwc3: qcom: Add support for selecting UTMI as reference clock

[Krishna Kurapati]

On 8/26/2026 3:07 PM, George Moussalem wrote:
> On 8/26/26 13:18, Konrad Dybcio wrote:
>> On 8/25/26 12:42 PM, George Moussalem via B4 Relay wrote:
>>> From: George Moussalem <george.moussalem@outlook.com>
>>>
>>> On many Qualcomm chipsets, the UTMI clock is used as the reference clock
>>> (ex. IPQ5018, IPQ6018, and IPQ9574 and more). Since moving to the new
>>> flattened snps-dwc3 model, it is no longer possible to pass the
>>> reference clock to the dwc3 core driver.
>>>
>>> The clock rate is used by dwc3 core to derive the reference clock period
>>> and frame length adjusment. This is needed when the reference clock
>>> deviates from the hardware default (typically 19.2MHz). Above mentioned
>>> SoCs use different rates and, as such, the core initializes with the
>>> wrong values which leads to non-functional USB operation.
>>>
>>> Read the "qcom,select-utmi-as-ref-clk" property to determine if the UTMI
>>> clock should be used as the reference clock. If so, set it as the
>>> reference clock in the dwc3_probe_data structure.
>>> The dwc3 core driver will then use this clock to derive the clock rate.
>>>
>>> Signed-off-by: George Moussalem <george.moussalem@outlook.com>
>>> ---
>>
>> There's a shorter patch in flight:
>>
>> https://lore.kernel.org/linux-arm-msm/20260825-ctrl-v1-2-609e2291814d@oss.qualcomm.com/
> 
> I'm aware and have discussed that with Varada. My concerns are that
> directly setting qcom->dwc->ref_clk from the glue layer is a layering
> violation. This patch passes it to the DWC3 core via the probe_data struct.
> 
> In addition, if ignore_clocks_and_resets is set in the glue layer (which
> is the case for qcom's and others), setting the dwc->ref_clk makes it
> become managed by the core which is the opposite of what the
> ignore_clocks_and_resets property is there for.
> 
I believe doing it from here is better. In [1], refclk is being added as 
a new clock, but I checked with Varada offline and he said that he 
wanted to pass mock_utmi as ref_clk. IMO This patch is better as it 
reuses mock_utmi instead of adding another new clock.

[1]: 
https://lore.kernel.org/all/20260825-ctrl-v1-2-609e2291814d@oss.qualcomm.com/

Regards,
Krishna,

Re: [PATCH 3/9] usb: dwc3: qcom: Add support for selecting UTMI as reference clock

[Varadarajan Narayanan]

[...]
> diff --git a/drivers/usb/dwc3/dwc3-qcom.c b/drivers/usb/dwc3/dwc3-qcom.c
> index ac68b4218b56..17292517c594 100644
> --- a/drivers/usb/dwc3/dwc3-qcom.c
> +++ b/drivers/usb/dwc3/dwc3-qcom.c
> @@ -617,6 +617,8 @@ static int dwc3_qcom_probe(struct platform_device *pdev)
>  	int			ret;
>  	bool			ignore_pipe_clk;
>  	bool			wakeup_source;
> +	bool			select_utmi_as_ref_clk;
> +	struct clk		*ref_clk;

Any reason why glue layer can't send the ref_clk_rate directly?

-Varada

>  	qcom = devm_kzalloc(&pdev->dev, sizeof(*qcom), GFP_KERNEL);
>  	if (!qcom)
> @@ -698,6 +700,18 @@ static int dwc3_qcom_probe(struct platform_device *pdev)
>  			qcom->current_role = USB_ROLE_DEVICE;
>  	}
>
> +	select_utmi_as_ref_clk = device_property_read_bool(dev,
> +					"qcom,select-utmi-as-ref-clk");
> +	if (select_utmi_as_ref_clk) {
> +		ref_clk = devm_clk_get_optional(dev, "mock_utmi");
> +		if (IS_ERR(ref_clk)) {
> +			ret = PTR_ERR(ref_clk);
> +			dev_warn(dev, "failed to get ref clock: %d\n", ret);
> +		} else {
> +			probe_data.ref_clk = ref_clk;
> +		}
> +	}
> +
>  	qcom->dwc.glue_ops = &dwc3_qcom_glue_ops;
>
>  	qcom->dwc.dev = dev;
>
> --
> 2.53.0
>
>

Re: [PATCH 3/9] usb: dwc3: qcom: Add support for selecting UTMI as reference clock

[George Moussalem]

On 8/27/26 15:42, Varadarajan Narayanan wrote:
> [...]
>> diff --git a/drivers/usb/dwc3/dwc3-qcom.c b/drivers/usb/dwc3/dwc3-qcom.c
>> index ac68b4218b56..17292517c594 100644
>> --- a/drivers/usb/dwc3/dwc3-qcom.c
>> +++ b/drivers/usb/dwc3/dwc3-qcom.c
>> @@ -617,6 +617,8 @@ static int dwc3_qcom_probe(struct platform_device *pdev)
>>  	int			ret;
>>  	bool			ignore_pipe_clk;
>>  	bool			wakeup_source;
>> +	bool			select_utmi_as_ref_clk;
>> +	struct clk		*ref_clk;
> 
> Any reason why glue layer can't send the ref_clk_rate directly?

no, I've tested both. The only reason I passed the clock itself was that
it leaves it open to the core and all glue layers to implement their
requirements (if needed). Happy to switch to ref_clk_rate. I need to
send a revision anyways to change devm_clk_get_optional to devm_clk_get.

> 
> -Varada
> 
>>  	qcom = devm_kzalloc(&pdev->dev, sizeof(*qcom), GFP_KERNEL);
>>  	if (!qcom)
>> @@ -698,6 +700,18 @@ static int dwc3_qcom_probe(struct platform_device *pdev)
>>  			qcom->current_role = USB_ROLE_DEVICE;
>>  	}
>>
>> +	select_utmi_as_ref_clk = device_property_read_bool(dev,
>> +					"qcom,select-utmi-as-ref-clk");
>> +	if (select_utmi_as_ref_clk) {
>> +		ref_clk = devm_clk_get_optional(dev, "mock_utmi");
>> +		if (IS_ERR(ref_clk)) {
>> +			ret = PTR_ERR(ref_clk);
>> +			dev_warn(dev, "failed to get ref clock: %d\n", ret);
>> +		} else {
>> +			probe_data.ref_clk = ref_clk;
>> +		}
>> +	}
>> +
>>  	qcom->dwc.glue_ops = &dwc3_qcom_glue_ops;
>>
>>  	qcom->dwc.dev = dev;
>>
>> --
>> 2.53.0
>>
>>

Re: [PATCH 8/9] arm64: dts: qcom: ipq8074: Flatten usb controller nodes

[Krishna Kurapati]

On 8/25/2026 4:12 PM, George Moussalem via B4 Relay wrote:
> From: George Moussalem <george.moussalem@outlook.com>
> 
> Flatten usb controller nodes and update to using latest bindings and
> flattened driver approach.
> 
> In addition, fix indentation of properties in both nodes.
> 
> Signed-off-by: George Moussalem <george.moussalem@outlook.com>
> ---
>   arch/arm64/boot/dts/qcom/ipq8074.dtsi | 112 ++++++++++++++++------------------
>   1 file changed, 52 insertions(+), 60 deletions(-)
> 
> diff --git a/arch/arm64/boot/dts/qcom/ipq8074.dtsi b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
> index 75a5ae30d966..d4a86b3815f2 100644
> --- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
> +++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
> @@ -625,104 +625,96 @@ qpic_nand: nand-controller@79b0000 {
>   			status = "disabled";
>   		};
>   
> -		usb_0: usb@8af8800 {
> -			compatible = "qcom,ipq8074-dwc3", "qcom,dwc3";
> -			reg = <0x08af8800 0x400>;
> -			#address-cells = <1>;
> -			#size-cells = <1>;
> -			ranges;
> +		usb_0: usb@8a00000 {
> +			compatible = "qcom,ipq8074-dwc3", "qcom,snps-dwc3";
> +			reg = <0x08a00000 0xfc100>;
>   
>   			clocks = <&gcc GCC_SYS_NOC_USB0_AXI_CLK>,
> -				<&gcc GCC_USB0_MASTER_CLK>,
> -				<&gcc GCC_USB0_SLEEP_CLK>,
> -				<&gcc GCC_USB0_MOCK_UTMI_CLK>;
> +				 <&gcc GCC_USB0_MASTER_CLK>,
> +				 <&gcc GCC_USB0_SLEEP_CLK>,
> +				 <&gcc GCC_USB0_MOCK_UTMI_CLK>;
>   			clock-names = "cfg_noc",
> -				"core",
> -				"sleep",
> -				"mock_utmi";
> +				      "core",
> +				      "sleep",
> +				      "mock_utmi";
>   
>   			assigned-clocks = <&gcc GCC_SYS_NOC_USB0_AXI_CLK>,
>   					  <&gcc GCC_USB0_MASTER_CLK>,
>   					  <&gcc GCC_USB0_MOCK_UTMI_CLK>;
>   			assigned-clock-rates = <133330000>,
> -						<133330000>,
> -						<19200000>;
> +					       <133330000>,
> +					       <19200000>;
>   
> -			interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
> +			interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
>   				     <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
>   				     <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
> -			interrupt-names = "pwr_event",
> +			interrupt-names = "dwc_usb3",
> +					  "pwr_event",
>   					  "qusb2_phy",
>   					  "ss_phy_irq";
>   
>   			power-domains = <&gcc USB0_GDSC>;
>   
> +			phys = <&qusb_phy_0>, <&ssphy_0>;
> +			phy-names = "usb2-phy", "usb3-phy";
> +
> +			snps,parkmode-disable-ss-quirk;
> +			snps,is-utmi-l1-suspend;
> +			snps,hird-threshold = /bits/ 8 <0x0>;
> +			snps,dis_u2_susphy_quirk;
> +			snps,dis_u3_susphy_quirk;
> +			dr_mode = "host";
> +

I see this controller is DRD capable. Move this property to platform DTS 
if dr_mode is needed as host.

>   			resets = <&gcc GCC_USB0_BCR>;
> -			status = "disabled";
>   

[...]

> +		usb_1: usb@8c00000 {
> +			compatible = "qcom,ipq8074-dwc3", "qcom,snps-dwc3";
> +			reg = <0x08c00000 0xfc100>;
>   
>   			clocks = <&gcc GCC_SYS_NOC_USB1_AXI_CLK>,
> -				<&gcc GCC_USB1_MASTER_CLK>,
> -				<&gcc GCC_USB1_SLEEP_CLK>,
> -				<&gcc GCC_USB1_MOCK_UTMI_CLK>;
> +				 <&gcc GCC_USB1_MASTER_CLK>,
> +				 <&gcc GCC_USB1_SLEEP_CLK>,
> +				 <&gcc GCC_USB1_MOCK_UTMI_CLK>;
>   			clock-names = "cfg_noc",
> -				"core",
> -				"sleep",
> -				"mock_utmi";
> +				      "core",
> +				      "sleep",
> +				      "mock_utmi";
>   
>   			assigned-clocks = <&gcc GCC_SYS_NOC_USB1_AXI_CLK>,
>   					  <&gcc GCC_USB1_MASTER_CLK>,
>   					  <&gcc GCC_USB1_MOCK_UTMI_CLK>;
>   			assigned-clock-rates = <133330000>,
> -						<133330000>,
> -						<19200000>;
> +					       <133330000>,
> +					       <19200000>;
>   
> -			interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
> +			interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
>   				     <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
>   				     <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
> -			interrupt-names = "pwr_event",
> +			interrupt-names = "dwc_usb3",
> +					  "pwr_event",
>   					  "qusb2_phy",
>   					  "ss_phy_irq";
>   
>   			power-domains = <&gcc USB1_GDSC>;
>   
> +			phys = <&qusb_phy_1>, <&ssphy_1>;
> +			phy-names = "usb2-phy", "usb3-phy";
> +
> +			snps,parkmode-disable-ss-quirk;
> +			snps,is-utmi-l1-suspend;
> +			snps,hird-threshold = /bits/ 8 <0x0>;
> +			snps,dis_u2_susphy_quirk;
> +			snps,dis_u3_susphy_quirk;
> +			dr_mode = "host";
> +

Same comment as above.

Regards,
Krishna,

Re: [PATCH 9/9] arm64: dts: qcom: ipq9574: Flatten usb controller node

[Krishna Kurapati]

On 8/25/2026 4:12 PM, George Moussalem via B4 Relay wrote:
> From: George Moussalem <george.moussalem@outlook.com>
> 
> Flatten usb controller nodes and update to using latest bindings and
> flattened driver approach.
> 
> Add property to the USB node to select UTMI as reference clock for the
> DWC3 core to calculate the right values for the period and frame length
> adjustment.
> 
> Signed-off-by: George Moussalem <george.moussalem@outlook.com>

[...]

> @@ -780,32 +777,31 @@ usb3: usb@8af8800 {
>   			assigned-clock-rates = <200000000>,
>   					       <24000000>;
>   
> -			interrupts-extended = <&intc GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
> +			interrupts-extended = <&intc GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
> +					      <&intc GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
>   					      <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
>   					      <&intc GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
>   					      <&intc GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
> -			interrupt-names = "pwr_event",
> +			interrupt-names = "dwc_usb3",
> +					  "pwr_event",
>   					  "qusb2_phy",
>   					  "dm_hs_phy_irq",
>   					  "dp_hs_phy_irq";
>   

You are adding pwr_event irq here. So please mention that in commit 
message. Or would be better if you can send this interrupt addition as a 
separate patch.

Regards,
Krishna,

Re: [PATCH 7/9] arm64: dts: qcom: ipq6018: Flatten usb controller nodes

[Krishna Kurapati]

On 8/25/2026 4:12 PM, George Moussalem via B4 Relay wrote:
> From: George Moussalem <george.moussalem@outlook.com>
> 
> Flatten usb controller nodes and update to using latest bindings and
> flattened driver approach.
> 
> This SoC has two USB controllers of which the USB3 node had a ref clock
> populated in the DWC3 child node. Add property to the USB3 node only to
> select UTMI as reference clock for the DWC3 core to calculate the right
> values for the period and frame length adjustment.
> 
> Signed-off-by: George Moussalem <george.moussalem@outlook.com>

[...]

>   
> -			interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
> +			interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
>   				     <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
> -			interrupt-names = "pwr_event",
> +			interrupt-names = "dwc_usb3",
> +					  "pwr_event",
>   					  "qusb2_phy";
>   

You are adding pwr_event irq here. Do mention that in the commit message 
or send this particular interrupt addition as a separate patch.

>   			resets = <&gcc GCC_USB1_BCR>;
> -			status = "disabled";
>   
> -			dwc_1: usb@7000000 {
> -				compatible = "snps,dwc3";
> -				reg = <0x0 0x07000000 0x0 0xcd00>;
> -				interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
> -				phys = <&qusb_phy_1>;
> -				phy-names = "usb2-phy";
> -				tx-fifo-resize;
> -				snps,is-utmi-l1-suspend;
> -				snps,hird-threshold = /bits/ 8 <0x0>;
> -				snps,dis_u2_susphy_quirk;
> -				snps,dis_u3_susphy_quirk;
> -				dr_mode = "host";
> -			};
> +			phys = <&qusb_phy_1>;
> +			phy-names = "usb2-phy";
> +
> +			tx-fifo-resize;
> +			snps,is-utmi-l1-suspend;
> +			snps,hird-threshold = /bits/ 8 <0x0>;
> +			snps,dis_u2_susphy_quirk;
> +			snps,dis_u3_susphy_quirk;
> +			dr_mode = "host";
> +

If this is HS only, do we need to add "qcom,select-utmi-as-pipe-clk" ?

[...]

> +		usb3: usb@8a00000 {
> +			compatible = "qcom,ipq6018-dwc3", "qcom,snps-dwc3";
> +			reg = <0x0 0x08a00000 0x0 0xfc100>;
>   
>   			clocks = <&gcc GCC_SYS_NOC_USB0_AXI_CLK>,
> -				<&gcc GCC_USB0_MASTER_CLK>,
> -				<&gcc GCC_USB0_SLEEP_CLK>,
> -				<&gcc GCC_USB0_MOCK_UTMI_CLK>;
> +				 <&gcc GCC_USB0_MASTER_CLK>,
> +				 <&gcc GCC_USB0_SLEEP_CLK>,
> +				 <&gcc GCC_USB0_MOCK_UTMI_CLK>;
>   			clock-names = "cfg_noc",
> -				"core",
> -				"sleep",
> -				"mock_utmi";
> +				      "core",
> +				      "sleep",
> +				      "mock_utmi";
>   
>   			assigned-clocks = <&gcc GCC_SYS_NOC_USB0_AXI_CLK>,
>   					  <&gcc GCC_USB0_MASTER_CLK>,
> @@ -692,32 +686,31 @@ usb3: usb@8af8800 {
>   					       <133330000>,
>   					       <24000000>;
>   
> -			interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
> +			interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
>   				     <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
>   				     <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
> -			interrupt-names = "pwr_event",
> +			interrupt-names = "dwc_usb3",
> +					  "pwr_event",
>   					  "qusb2_phy",
>   					  "ss_phy_irq";

Same comment as above.

>   
>   			resets = <&gcc GCC_USB0_BCR>;
> -			status = "disabled";
>   
> -			dwc_0: usb@8a00000 {
> -				compatible = "snps,dwc3";
> -				reg = <0x0 0x08a00000 0x0 0xcd00>;
> -				interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
> -				phys = <&qusb_phy_0>, <&ssphy_0>;
> -				phy-names = "usb2-phy", "usb3-phy";
> -				clocks = <&xo>;
> -				clock-names = "ref";
> -				tx-fifo-resize;
> -				snps,parkmode-disable-ss-quirk;
> -				snps,is-utmi-l1-suspend;
> -				snps,hird-threshold = /bits/ 8 <0x0>;
> -				snps,dis_u2_susphy_quirk;
> -				snps,dis_u3_susphy_quirk;
> -				dr_mode = "host";
> -			};
> +			phys = <&qusb_phy_0>, <&ssphy_0>;
> +			phy-names = "usb2-phy", "usb3-phy";
> +
> +			qcom,select-utmi-as-ref-clk;
> +
> +			tx-fifo-resize;
> +			snps,parkmode-disable-ss-quirk;
> +			snps,is-utmi-l1-suspend;
> +			snps,hird-threshold = /bits/ 8 <0x0>;
> +			snps,dis_u2_susphy_quirk;
> +			snps,dis_u3_susphy_quirk;
> +			dr_mode = "host";

This controller is DRD capable. Please move this dr_mode property to DTS 
file.

Regards,
Krishna,

Re: [PATCH 7/9] arm64: dts: qcom: ipq6018: Flatten usb controller nodes

[George Moussalem]

On 8/29/26 20:48, Krishna Kurapati wrote:
> 
> 
> On 8/25/2026 4:12 PM, George Moussalem via B4 Relay wrote:
>> From: George Moussalem <george.moussalem@outlook.com>
>>
>> Flatten usb controller nodes and update to using latest bindings and
>> flattened driver approach.
>>
>> This SoC has two USB controllers of which the USB3 node had a ref clock
>> populated in the DWC3 child node. Add property to the USB3 node only to
>> select UTMI as reference clock for the DWC3 core to calculate the right
>> values for the period and frame length adjustment.
>>
>> Signed-off-by: George Moussalem <george.moussalem@outlook.com>
> 
> [...]
> 
>>   -            interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
>> +            interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
>> +                     <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
>>                        <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
>> -            interrupt-names = "pwr_event",
>> +            interrupt-names = "dwc_usb3",
>> +                      "pwr_event",
>>                         "qusb2_phy";
>>   
> 
> You are adding pwr_event irq here. Do mention that in the commit message
> or send this particular interrupt addition as a separate patch.

I think you may have misread, I'm not adding the pwr_event irq. It was
already there. I'm simply moving up the dwc_usb3 irq from the dwc node.

> 
>>               resets = <&gcc GCC_USB1_BCR>;
>> -            status = "disabled";
>>   -            dwc_1: usb@7000000 {
>> -                compatible = "snps,dwc3";
>> -                reg = <0x0 0x07000000 0x0 0xcd00>;
>> -                interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
>> -                phys = <&qusb_phy_1>;
>> -                phy-names = "usb2-phy";
>> -                tx-fifo-resize;
>> -                snps,is-utmi-l1-suspend;
>> -                snps,hird-threshold = /bits/ 8 <0x0>;
>> -                snps,dis_u2_susphy_quirk;
>> -                snps,dis_u3_susphy_quirk;
>> -                dr_mode = "host";
>> -            };
>> +            phys = <&qusb_phy_1>;
>> +            phy-names = "usb2-phy";
>> +
>> +            tx-fifo-resize;
>> +            snps,is-utmi-l1-suspend;
>> +            snps,hird-threshold = /bits/ 8 <0x0>;
>> +            snps,dis_u2_susphy_quirk;
>> +            snps,dis_u3_susphy_quirk;
>> +            dr_mode = "host";
>> +
> 
> If this is HS only, do we need to add "qcom,select-utmi-as-pipe-clk" ?

No, I've not removed it, I've flattened the node as is.

> 
> [...]
> 
>> +        usb3: usb@8a00000 {
>> +            compatible = "qcom,ipq6018-dwc3", "qcom,snps-dwc3";
>> +            reg = <0x0 0x08a00000 0x0 0xfc100>;
>>                 clocks = <&gcc GCC_SYS_NOC_USB0_AXI_CLK>,
>> -                <&gcc GCC_USB0_MASTER_CLK>,
>> -                <&gcc GCC_USB0_SLEEP_CLK>,
>> -                <&gcc GCC_USB0_MOCK_UTMI_CLK>;
>> +                 <&gcc GCC_USB0_MASTER_CLK>,
>> +                 <&gcc GCC_USB0_SLEEP_CLK>,
>> +                 <&gcc GCC_USB0_MOCK_UTMI_CLK>;
>>               clock-names = "cfg_noc",
>> -                "core",
>> -                "sleep",
>> -                "mock_utmi";
>> +                      "core",
>> +                      "sleep",
>> +                      "mock_utmi";
>>                 assigned-clocks = <&gcc GCC_SYS_NOC_USB0_AXI_CLK>,
>>                         <&gcc GCC_USB0_MASTER_CLK>,
>> @@ -692,32 +686,31 @@ usb3: usb@8af8800 {
>>                              <133330000>,
>>                              <24000000>;
>>   -            interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
>> +            interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
>> +                     <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
>>                        <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
>>                        <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
>> -            interrupt-names = "pwr_event",
>> +            interrupt-names = "dwc_usb3",
>> +                      "pwr_event",
>>                         "qusb2_phy",
>>                         "ss_phy_irq";
> 
> Same comment as above.

Same reply as above.
> 
>>                 resets = <&gcc GCC_USB0_BCR>;
>> -            status = "disabled";
>>   -            dwc_0: usb@8a00000 {
>> -                compatible = "snps,dwc3";
>> -                reg = <0x0 0x08a00000 0x0 0xcd00>;
>> -                interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
>> -                phys = <&qusb_phy_0>, <&ssphy_0>;
>> -                phy-names = "usb2-phy", "usb3-phy";
>> -                clocks = <&xo>;
>> -                clock-names = "ref";
>> -                tx-fifo-resize;
>> -                snps,parkmode-disable-ss-quirk;
>> -                snps,is-utmi-l1-suspend;
>> -                snps,hird-threshold = /bits/ 8 <0x0>;
>> -                snps,dis_u2_susphy_quirk;
>> -                snps,dis_u3_susphy_quirk;
>> -                dr_mode = "host";
>> -            };
>> +            phys = <&qusb_phy_0>, <&ssphy_0>;
>> +            phy-names = "usb2-phy", "usb3-phy";
>> +
>> +            qcom,select-utmi-as-ref-clk;
>> +
>> +            tx-fifo-resize;
>> +            snps,parkmode-disable-ss-quirk;
>> +            snps,is-utmi-l1-suspend;
>> +            snps,hird-threshold = /bits/ 8 <0x0>;
>> +            snps,dis_u2_susphy_quirk;
>> +            snps,dis_u3_susphy_quirk;
>> +            dr_mode = "host";
> 
> This controller is DRD capable. Please move this dr_mode property to DTS
> file.

dr_mode was already there. Removing may break existing implementations
and should require a separate patch.

> 
> Regards,
> Krishna,

Re: [PATCH 8/9] arm64: dts: qcom: ipq8074: Flatten usb controller nodes

[George Moussalem]

On 8/29/26 20:41, Krishna Kurapati wrote:
> 
> 
> On 8/25/2026 4:12 PM, George Moussalem via B4 Relay wrote:
>> From: George Moussalem <george.moussalem@outlook.com>
>>
>> Flatten usb controller nodes and update to using latest bindings and
>> flattened driver approach.
>>
>> In addition, fix indentation of properties in both nodes.
>>
>> Signed-off-by: George Moussalem <george.moussalem@outlook.com>
>> ---
>>   arch/arm64/boot/dts/qcom/ipq8074.dtsi | 112 +++++++++++++++
>> +------------------
>>   1 file changed, 52 insertions(+), 60 deletions(-)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/ipq8074.dtsi b/arch/arm64/boot/
>> dts/qcom/ipq8074.dtsi
>> index 75a5ae30d966..d4a86b3815f2 100644
>> --- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
>> @@ -625,104 +625,96 @@ qpic_nand: nand-controller@79b0000 {
>>               status = "disabled";
>>           };
>>   -        usb_0: usb@8af8800 {
>> -            compatible = "qcom,ipq8074-dwc3", "qcom,dwc3";
>> -            reg = <0x08af8800 0x400>;
>> -            #address-cells = <1>;
>> -            #size-cells = <1>;
>> -            ranges;
>> +        usb_0: usb@8a00000 {
>> +            compatible = "qcom,ipq8074-dwc3", "qcom,snps-dwc3";
>> +            reg = <0x08a00000 0xfc100>;
>>                 clocks = <&gcc GCC_SYS_NOC_USB0_AXI_CLK>,
>> -                <&gcc GCC_USB0_MASTER_CLK>,
>> -                <&gcc GCC_USB0_SLEEP_CLK>,
>> -                <&gcc GCC_USB0_MOCK_UTMI_CLK>;
>> +                 <&gcc GCC_USB0_MASTER_CLK>,
>> +                 <&gcc GCC_USB0_SLEEP_CLK>,
>> +                 <&gcc GCC_USB0_MOCK_UTMI_CLK>;
>>               clock-names = "cfg_noc",
>> -                "core",
>> -                "sleep",
>> -                "mock_utmi";
>> +                      "core",
>> +                      "sleep",
>> +                      "mock_utmi";
>>                 assigned-clocks = <&gcc GCC_SYS_NOC_USB0_AXI_CLK>,
>>                         <&gcc GCC_USB0_MASTER_CLK>,
>>                         <&gcc GCC_USB0_MOCK_UTMI_CLK>;
>>               assigned-clock-rates = <133330000>,
>> -                        <133330000>,
>> -                        <19200000>;
>> +                           <133330000>,
>> +                           <19200000>;
>>   -            interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
>> +            interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
>> +                     <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
>>                        <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
>>                        <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
>> -            interrupt-names = "pwr_event",
>> +            interrupt-names = "dwc_usb3",
>> +                      "pwr_event",
>>                         "qusb2_phy",
>>                         "ss_phy_irq";
>>                 power-domains = <&gcc USB0_GDSC>;
>>   +            phys = <&qusb_phy_0>, <&ssphy_0>;
>> +            phy-names = "usb2-phy", "usb3-phy";
>> +
>> +            snps,parkmode-disable-ss-quirk;
>> +            snps,is-utmi-l1-suspend;
>> +            snps,hird-threshold = /bits/ 8 <0x0>;
>> +            snps,dis_u2_susphy_quirk;
>> +            snps,dis_u3_susphy_quirk;
>> +            dr_mode = "host";
>> +
> 
> I see this controller is DRD capable. Move this property to platform DTS
> if dr_mode is needed as host.

That should be part of a separate patch set IMO. The scope of this patch
is to flatten the node only. Removing it may break existing
implementations.

> 
>>               resets = <&gcc GCC_USB0_BCR>;
>> -            status = "disabled";
>>   
> 
> [...]
> 
>> +        usb_1: usb@8c00000 {
>> +            compatible = "qcom,ipq8074-dwc3", "qcom,snps-dwc3";
>> +            reg = <0x08c00000 0xfc100>;
>>                 clocks = <&gcc GCC_SYS_NOC_USB1_AXI_CLK>,
>> -                <&gcc GCC_USB1_MASTER_CLK>,
>> -                <&gcc GCC_USB1_SLEEP_CLK>,
>> -                <&gcc GCC_USB1_MOCK_UTMI_CLK>;
>> +                 <&gcc GCC_USB1_MASTER_CLK>,
>> +                 <&gcc GCC_USB1_SLEEP_CLK>,
>> +                 <&gcc GCC_USB1_MOCK_UTMI_CLK>;
>>               clock-names = "cfg_noc",
>> -                "core",
>> -                "sleep",
>> -                "mock_utmi";
>> +                      "core",
>> +                      "sleep",
>> +                      "mock_utmi";
>>                 assigned-clocks = <&gcc GCC_SYS_NOC_USB1_AXI_CLK>,
>>                         <&gcc GCC_USB1_MASTER_CLK>,
>>                         <&gcc GCC_USB1_MOCK_UTMI_CLK>;
>>               assigned-clock-rates = <133330000>,
>> -                        <133330000>,
>> -                        <19200000>;
>> +                           <133330000>,
>> +                           <19200000>;
>>   -            interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
>> +            interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
>> +                     <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
>>                        <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
>>                        <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
>> -            interrupt-names = "pwr_event",
>> +            interrupt-names = "dwc_usb3",
>> +                      "pwr_event",
>>                         "qusb2_phy",
>>                         "ss_phy_irq";
>>                 power-domains = <&gcc USB1_GDSC>;
>>   +            phys = <&qusb_phy_1>, <&ssphy_1>;
>> +            phy-names = "usb2-phy", "usb3-phy";
>> +
>> +            snps,parkmode-disable-ss-quirk;
>> +            snps,is-utmi-l1-suspend;
>> +            snps,hird-threshold = /bits/ 8 <0x0>;
>> +            snps,dis_u2_susphy_quirk;
>> +            snps,dis_u3_susphy_quirk;
>> +            dr_mode = "host";
>> +
> 
> Same comment as above.

See above.>
> Regards,
> Krishna,

Best regards,
George

Re: [PATCH 9/9] arm64: dts: qcom: ipq9574: Flatten usb controller node

[George Moussalem]

On 8/29/26 20:44, Krishna Kurapati wrote:
> 
> 
> On 8/25/2026 4:12 PM, George Moussalem via B4 Relay wrote:
>> From: George Moussalem <george.moussalem@outlook.com>
>>
>> Flatten usb controller nodes and update to using latest bindings and
>> flattened driver approach.
>>
>> Add property to the USB node to select UTMI as reference clock for the
>> DWC3 core to calculate the right values for the period and frame length
>> adjustment.
>>
>> Signed-off-by: George Moussalem <george.moussalem@outlook.com>
> 
> [...]
> 
>> @@ -780,32 +777,31 @@ usb3: usb@8af8800 {
>>               assigned-clock-rates = <200000000>,
>>                              <24000000>;
>>   -            interrupts-extended = <&intc GIC_SPI 134
>> IRQ_TYPE_LEVEL_HIGH>,
>> +            interrupts-extended = <&intc GIC_SPI 140
>> IRQ_TYPE_LEVEL_HIGH>,
>> +                          <&intc GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
>>                             <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
>>                             <&intc GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
>>                             <&intc GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
>> -            interrupt-names = "pwr_event",
>> +            interrupt-names = "dwc_usb3",
>> +                      "pwr_event",
>>                         "qusb2_phy",
>>                         "dm_hs_phy_irq",
>>                         "dp_hs_phy_irq";
>>   
> 
> You are adding pwr_event irq here. So please mention that in commit
> message. Or would be better if you can send this interrupt addition as a
> separate patch.

I think you may have misread, I'm not adding the pwr_event irq. It was
already there. I'm simply moving up the dwc_usb3 irq from the dwc node.

> 
> Regards,
> Krishna,

Best regards,
George

Re: [PATCH 1/9] dt-bindings: usb: qcom,snps-dwc3: Add ability to select UTMI as reference clock

[Krzysztof Kozlowski]

On Tue, Aug 25, 2026 at 02:42:26PM +0400, George Moussalem wrote:
> Add ability to select the UTMI clock as reference clock which is passed
> by the glue layer to the DWC3 core to calculate the reference clock
> period and frame length adjustment based on its clock rate.
> 
> In the flattened snsp-dwc3 model, it is currently not possible to pass a
> reference clock that differs from the default since:
> commit 613a2e655d4d ("usb: dwc3: core: Expose core driver as library")
> 
> This prevents moving chipsets such as IPQ5018, IPQ6018, IPQ5332, IPQ5424
> and IPQ9574 with a reference clock rate different from 19.2 MHz from
> moving to the flattened model.
> 
> The Qualcomm takes care of clock and resets management itself and sets
> the ignore_clocks_and_resets flag in dwc3_probe_data to true, so the
> core doesn't acquire the reference clock from the devicetree.
> 
> The existing DT property 'snps,quirk-ref-clk-period-ns' has been
> deprecated.

There is no such property.


> 
> So, add a property to select the UTMI clock used by many (if not all)
> Qualcomm USB controllers as the reference clock.
> 
> Signed-off-by: George Moussalem <george.moussalem@outlook.com>
> ---
>  Documentation/devicetree/bindings/usb/qcom,snps-dwc3.yaml | 9 +++++++++
>  1 file changed, 9 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/usb/qcom,snps-dwc3.yaml b/Documentation/devicetree/bindings/usb/qcom,snps-dwc3.yaml
> index ea60f7220afe..aa263dfd42a1 100644
> --- a/Documentation/devicetree/bindings/usb/qcom,snps-dwc3.yaml
> +++ b/Documentation/devicetree/bindings/usb/qcom,snps-dwc3.yaml
> @@ -155,6 +155,15 @@ properties:
>        HS/FS/LS modes are supported.
>      type: boolean
>  
> +  qcom,select-utmi-as-ref-clk:
> +    description:
> +      If present, pass the UTMI clock as the reference clock to the DWC3 core to
> +      use its clock rate to calculate the reference clock period and frame
> +      length adjustment in GUCTL and GFLADJ registers. This is needed when these
> +      values based on the standard clock rate deviate from the hardware default
> +      values. If not set, the hardware default values are used.

Sashiko comment seems valid. You describe Linux behavior. In your commit
msg you mention that clock cannot be passed since commit 613a2e655d4d,
which is a driver commit. So trivial answer would be: if issue was
caused by driver commit, then fix is within driver, not bindings.

Maybe there is different issue which is not purely-driver specific, but
I did not get that from description.

For example, if given SoC has different rates, then the SoC-specific DWC
compatible defines which clock to use and you do not need such property.

Best regards,
Krzysztof

Re: [PATCH 2/9] usb: dwc3: core: Allow glue layer to pass reference clock

[Krzysztof Kozlowski]

On Tue, Aug 25, 2026 at 02:42:27PM +0400, George Moussalem wrote:
> Add ability to pass a reference clock from the glue layer to the DWC3
> core driver. The core calculates the reference clock period and frame
> length adjustment based on the reference clock rate.
> 
> In the flattened snsp-dwc3 model, it is currently not possible to pass a
> reference clock that differs from the default since:
> commit 613a2e655d4d ("usb: dwc3: core: Expose core driver as library")
> 
> The new glue layers (incl. Qualcomm's) set the ignore_clocks_and_resets
> flag in dwc3_probe_data to true, which disables the core driver's clock
> management, thus it also doesn't acquire the reference clock from the
> devicetree needed in dwc3_ref_clk_period.
> 
> There's an existing DT property 'snps,quirk-ref-clk-period-ns', but

Where? git grep gave me zero results.

Best regards,
Krzysztof

Re: [PATCH 1/9] dt-bindings: usb: qcom,snps-dwc3: Add ability to select UTMI as reference clock

[George Moussalem]

On 8/30/26 13:41, Krzysztof Kozlowski wrote:
> On Tue, Aug 25, 2026 at 02:42:26PM +0400, George Moussalem wrote:
>> Add ability to select the UTMI clock as reference clock which is passed
>> by the glue layer to the DWC3 core to calculate the reference clock
>> period and frame length adjustment based on its clock rate.
>>
>> In the flattened snsp-dwc3 model, it is currently not possible to pass a
>> reference clock that differs from the default since:
>> commit 613a2e655d4d ("usb: dwc3: core: Expose core driver as library")
>>
>> This prevents moving chipsets such as IPQ5018, IPQ6018, IPQ5332, IPQ5424
>> and IPQ9574 with a reference clock rate different from 19.2 MHz from
>> moving to the flattened model.
>>
>> The Qualcomm takes care of clock and resets management itself and sets
>> the ignore_clocks_and_resets flag in dwc3_probe_data to true, so the
>> core doesn't acquire the reference clock from the devicetree.
>>
>> The existing DT property 'snps,quirk-ref-clk-period-ns' has been
>> deprecated.
> 
> There is no such property.
> 
> 
>>
>> So, add a property to select the UTMI clock used by many (if not all)
>> Qualcomm USB controllers as the reference clock.
>>
>> Signed-off-by: George Moussalem <george.moussalem@outlook.com>
>> ---
>>  Documentation/devicetree/bindings/usb/qcom,snps-dwc3.yaml | 9 +++++++++
>>  1 file changed, 9 insertions(+)
>>
>> diff --git a/Documentation/devicetree/bindings/usb/qcom,snps-dwc3.yaml b/Documentation/devicetree/bindings/usb/qcom,snps-dwc3.yaml
>> index ea60f7220afe..aa263dfd42a1 100644
>> --- a/Documentation/devicetree/bindings/usb/qcom,snps-dwc3.yaml
>> +++ b/Documentation/devicetree/bindings/usb/qcom,snps-dwc3.yaml
>> @@ -155,6 +155,15 @@ properties:
>>        HS/FS/LS modes are supported.
>>      type: boolean
>>  
>> +  qcom,select-utmi-as-ref-clk:
>> +    description:
>> +      If present, pass the UTMI clock as the reference clock to the DWC3 core to
>> +      use its clock rate to calculate the reference clock period and frame
>> +      length adjustment in GUCTL and GFLADJ registers. This is needed when these
>> +      values based on the standard clock rate deviate from the hardware default
>> +      values. If not set, the hardware default values are used.
> 
> Sashiko comment seems valid. You describe Linux behavior. In your commit
> msg you mention that clock cannot be passed since commit 613a2e655d4d,
> which is a driver commit. So trivial answer would be: if issue was
> caused by driver commit, then fix is within driver, not bindings.

The issue stems from collapsing the snps and dwc nodes into one: the
same clock was passed as "mock_utmi" in snps and as "ref" in the dwc
child node. In the flattened model, this causes two issues:
1. the core driver gets the ref clock by name ("ref") but you would
break the binding by changing the clock name from mock_utmi to ref and
perhaps causes backwards compatibility issues.
2. Even if you change the clock name, the new qcom glue layer sets
ignore_clocks_and_resets to true in the probe_data struct which means
the core driver doesn't acquire and manage the clocks/resets.

> 
> Maybe there is different issue which is not purely-driver specific, but
> I did not get that from description.
> 
> For example, if given SoC has different rates, then the SoC-specific DWC
> compatible defines which clock to use and you do not need such property.

That was possible in the 'old' way because it was allowed to pass the
same clock as both the mock_utmi and ref clock, albeit in different
nodes targeting snps and dwc respectively.

To solve it in the driver itself means we'd need to create compatible
specific match data structs which currently aren't in the driver and all
SoCs that require it (at least the ones in this series) wouldn't be able
to just use qcom,snps-dwc as the fallback. This would increase
complexity of the driver (which now is nice and simple) and would
require a change to the bindings too.
In addition, for some SoCs such as IPQ6018, we'd need two compatibles
because it has two USB controllers and only one of them requires setting
the ref clock.

Kindly advise so I can adjust v-next of the series accordingly.

> 
> Best regards,
> Krzysztof
> 
> 

Thanks,
George