[PATCH v2 0/3] ARM: dts: imx6: phycore-som: PMIC and PHY fixes

[PATCH v2 0/3] ARM: dts: imx6: phycore-som: PMIC and PHY fixes

[Primoz Fiser]

A few small fixes for the PHYTEC phyCORE-i.MX6 SOM:

- Pin the DA9062 PMIC watchdog to /dev/watchdog0 (1/4).
- Raise the PMIC's SOC/ARM buck ceiling to 1.5V, needed once the
  1.2GHz OPP tier ([1]] requests 1.3V for VDD_ARM and the anatop
  LDO's 125mV dropout is added on top (2/4).
- Add phy-reset-duration to fec node for more robust reset pulse (3/4)

[1] https://lore.kernel.org/all/20260923070505.494949-1-primoz.fiser@norik.com/

Link to v1: https://lore.kernel.org/all/20260930102532.2262700-1-primoz.fiser@norik.com/

Changes in v2:
- Drop patch #3 from v1 (converting to reset-gpios) due to potential
  backwards compatibility as suggested by Frank
- Convert patch #4 from v1 to patch #3 in v2 (use phy-reset-duration)

Primoz Fiser (3):
  ARM: dts: imx6: phycore-som: Set PMIC watchdog alias as default
  ARM: dts: imx6: phycore-som: Increase PMIC max SOC and ARM voltage
  ARM: dts: imx6: phycore-som: Add phy-reset-duration

 arch/arm/boot/dts/nxp/imx/imx6qdl-phytec-phycore-som.dtsi | 8 +++++---
 1 file changed, 5 insertions(+), 3 deletions(-)

-- 
2.34.1

[PATCH v2 1/3] ARM: dts: imx6: phycore-som: Set PMIC watchdog alias as default

[Primoz Fiser]

Pin the da9062 PMIC watchdog to /dev/watchdog0 via a DT alias, instead
of leaving it to be assigned dynamically by probe order. This SOM
already relies on the PMIC for reset (see commit aa4f48a4e06c ("ARM:
dts: imx6: phycore: Rely on PMIC reboot/reset handler")), so this
makes that the predictable, fixed watchdog device node.

Signed-off-by: Primoz Fiser <primoz.fiser@norik.com>
---
Changes in v2:
- no changes

 arch/arm/boot/dts/nxp/imx/imx6qdl-phytec-phycore-som.dtsi | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-phytec-phycore-som.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-phytec-phycore-som.dtsi
index ddbfecd591f5..205467fd223e 100644
--- a/arch/arm/boot/dts/nxp/imx/imx6qdl-phytec-phycore-som.dtsi
+++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-phytec-phycore-som.dtsi
@@ -11,6 +11,7 @@ / {
 	aliases {
 		rtc1 = &da9062_rtc;
 		rtc2 = &snvs_rtc;
+		watchdog0 = &da9062_wdog;
 	};
 
 	/*
@@ -112,7 +113,7 @@ da9062_onkey: onkey {
 			compatible = "dlg,da9062-onkey";
 		};
 
-		watchdog {
+		da9062_wdog: watchdog {
 			compatible = "dlg,da9062-watchdog";
 			dlg,use-sw-pm;
 			dlg,wdt-sd = <1>;
-- 
2.34.1

[PATCH v2 2/3] ARM: dts: imx6: phycore-som: Increase PMIC max SOC and ARM voltage

[Primoz Fiser]

The i.MX 6Quad with 1.2 GHz needs 1.4-1.5 V supply voltage for the 1.2
GHz operating point. Therefore this patch increases the maximum output
voltage of the PMIC's SOC and ARM core supply regulators to 1.5 V.
Otherwise transition to 1.2 GHz OPP fails (with the 125 mV anatop LDO
dropout taken into account).

Signed-off-by: Primoz Fiser <primoz.fiser@norik.com>
---
Changes in v2:
- no changes

 arch/arm/boot/dts/nxp/imx/imx6qdl-phytec-phycore-som.dtsi | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-phytec-phycore-som.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-phytec-phycore-som.dtsi
index 205467fd223e..9070388eecb0 100644
--- a/arch/arm/boot/dts/nxp/imx/imx6qdl-phytec-phycore-som.dtsi
+++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-phytec-phycore-som.dtsi
@@ -133,7 +133,7 @@ regulators {
 			vdd_arm: buck1 {
 				regulator-name = "vdd_arm";
 				regulator-min-microvolt = <925000>;
-				regulator-max-microvolt = <1380000>;
+				regulator-max-microvolt = <1500000>;
 				regulator-initial-mode = <DA9063_BUCK_MODE_SYNC>;
 				regulator-always-on;
 			};
@@ -141,7 +141,7 @@ vdd_arm: buck1 {
 			vdd_soc: buck2 {
 				regulator-name = "vdd_soc";
 				regulator-min-microvolt = <1150000>;
-				regulator-max-microvolt = <1380000>;
+				regulator-max-microvolt = <1500000>;
 				regulator-initial-mode = <DA9063_BUCK_MODE_SYNC>;
 				regulator-always-on;
 			};
-- 
2.34.1

[PATCH v2 3/3] ARM: dts: imx6: phycore-som: Add phy-reset-duration

[Primoz Fiser]

Without an explicit phy-reset-duration, fec_reset_phy() defaults the
phy-reset-gpios assertion to 1 ms. Extend it to 10 ms for a more robust
PHY reset pulse as otherwise Ethernet PHY probing occasionally fails.

Signed-off-by: Primoz Fiser <primoz.fiser@norik.com>
---
Changes in v2:
- drop patch #3 from v1
- convert patch #4 from v1 to phy-reset-duration instead

 arch/arm/boot/dts/nxp/imx/imx6qdl-phytec-phycore-som.dtsi | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-phytec-phycore-som.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-phytec-phycore-som.dtsi
index 9070388eecb0..977cf7825e78 100644
--- a/arch/arm/boot/dts/nxp/imx/imx6qdl-phytec-phycore-som.dtsi
+++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-phytec-phycore-som.dtsi
@@ -57,6 +57,7 @@ &fec {
 	phy-mode = "rgmii";
 	phy-supply = <&vdd_eth_io>;
 	phy-reset-gpios = <&gpio1 14 GPIO_ACTIVE_LOW>;
+	phy-reset-duration = <10>; /* in msecs */
 	status = "disabled";
 
 	mdio {
-- 
2.34.1

Re: [PATCH v2 0/3] ARM: dts: imx6: phycore-som: PMIC and PHY fixes

[Frank Li]

On Thu, Oct 01, 2026 at 09:09:44AM +0200, Primoz Fiser wrote:
> A few small fixes for the PHYTEC phyCORE-i.MX6 SOM:
>
> - Pin the DA9062 PMIC watchdog to /dev/watchdog0 (1/4).
> - Raise the PMIC's SOC/ARM buck ceiling to 1.5V, needed once the
>   1.2GHz OPP tier ([1]] requests 1.3V for VDD_ARM and the anatop
>   LDO's 125mV dropout is added on top (2/4).
> - Add phy-reset-duration to fec node for more robust reset pulse (3/4)
>
> [1] https://lore.kernel.org/all/20260923070505.494949-1-primoz.fiser@norik.com/
>
> Link to v1: https://lore.kernel.org/all/20260930102532.2262700-1-primoz.fiser@norik.com/
>
> Changes in v2:
> - Drop patch #3 from v1 (converting to reset-gpios) due to potential
>   backwards compatibility as suggested by Frank
> - Convert patch #4 from v1 to patch #3 in v2 (use phy-reset-duration)

What branch do you work on? I can't apply.

Frank

>
> Primoz Fiser (3):
>   ARM: dts: imx6: phycore-som: Set PMIC watchdog alias as default
>   ARM: dts: imx6: phycore-som: Increase PMIC max SOC and ARM voltage
>   ARM: dts: imx6: phycore-som: Add phy-reset-duration
>
>  arch/arm/boot/dts/nxp/imx/imx6qdl-phytec-phycore-som.dtsi | 8 +++++---
>  1 file changed, 5 insertions(+), 3 deletions(-)
>
> --
> 2.34.1
>
>

Re: [PATCH v2 0/3] ARM: dts: imx6: phycore-som: PMIC and PHY fixes

[Primoz Fiser]

Hi Frank,

On 10/1/26 16:49, Frank Li wrote:
> On Thu, Oct 01, 2026 at 09:09:44AM +0200, Primoz Fiser wrote:
>> A few small fixes for the PHYTEC phyCORE-i.MX6 SOM:
>>
>> - Pin the DA9062 PMIC watchdog to /dev/watchdog0 (1/4).
>> - Raise the PMIC's SOC/ARM buck ceiling to 1.5V, needed once the
>>   1.2GHz OPP tier ([1]] requests 1.3V for VDD_ARM and the anatop
>>   LDO's 125mV dropout is added on top (2/4).
>> - Add phy-reset-duration to fec node for more robust reset pulse (3/4)
>>
>> [1] https://lore.kernel.org/all/20260923070505.494949-1-primoz.fiser@norik.com/
>>
>> Link to v1: https://lore.kernel.org/all/20260930102532.2262700-1-primoz.fiser@norik.com/
>>
>> Changes in v2:
>> - Drop patch #3 from v1 (converting to reset-gpios) due to potential
>>   backwards compatibility as suggested by Frank
>> - Convert patch #4 from v1 to patch #3 in v2 (use phy-reset-duration)
> 
> What branch do you work on? I can't apply.

This series depends on series [1] patch #4.

BR,
Primoz

[1]
https://lore.kernel.org/all/20260924065044.368341-1-primoz.fiser@norik.com/



> 
> Frank
> 
>>
>> Primoz Fiser (3):
>>   ARM: dts: imx6: phycore-som: Set PMIC watchdog alias as default
>>   ARM: dts: imx6: phycore-som: Increase PMIC max SOC and ARM voltage
>>   ARM: dts: imx6: phycore-som: Add phy-reset-duration
>>
>>  arch/arm/boot/dts/nxp/imx/imx6qdl-phytec-phycore-som.dtsi | 8 +++++---
>>  1 file changed, 5 insertions(+), 3 deletions(-)
>>
>> --
>> 2.34.1
>>
>>

-- 
Primoz Fiser
phone: +386-41-390-545
email: primoz.fiser@norik.com
--
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