From: Lizhi Hou <lizhi.hou@amd.com>
To: David Zhang <yidong.zhang@amd.com>, <quic_jhugo@quicinc.com>,
<karol.wachowski@linux.intel.com>, <max.zhen@amd.com>,
<ogabbay@kernel.org>, <dri-devel@lists.freedesktop.org>,
<linux-kernel@vger.kernel.org>
Cc: <sonal.santan@amd.com>, <mario.limonciello@amd.com>,
Nishad Saraf <nishads@amd.com>
Subject: Re: [PATCH V4 09/19] accel/amdxdna: Add context switch hysteresis with debugfs control
Date: Tue, 13 Oct 2026 11:29:08 -0700 [thread overview]
Message-ID: <cea51f11-b341-6f26-17f1-0ac248d6642d@amd.com> (raw)
In-Reply-To: <20261009225343.3079074-10-yidong.zhang@amd.com>
On 10/9/26 15:53, David Zhang wrote:
> Add aie4_set_ctx_hysteresis() to configure the AIE4 context switch
> hysteresis timeout via the SET_RUNTIME_CONFIG message, applied at hw
> start (PF and classic paths) with a default of 1000 us.
>
> Expose a debugfs node 'ctx_switch_hysteresis_us' to change the timeout
> at runtime (0 disables hysteresis). The stored value is re-applied on
> every hw start so it survives runtime suspend/resume.
>
> Co-developed-by: Nishad Saraf <nishads@amd.com>
> Signed-off-by: Nishad Saraf <nishads@amd.com>
> Signed-off-by: David Zhang <yidong.zhang@amd.com>
> ---
> drivers/accel/amdxdna/aie4_message.c | 43 +++++++++++++
> drivers/accel/amdxdna/aie4_msg_priv.h | 24 +++++++
> drivers/accel/amdxdna/aie4_pci.c | 83 ++++++++++++++++++++++++-
> drivers/accel/amdxdna/aie4_pci.h | 9 +++
> drivers/accel/amdxdna/amdxdna_debugfs.c | 3 +
> drivers/accel/amdxdna/amdxdna_pci_drv.h | 1 +
> 6 files changed, 161 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/accel/amdxdna/aie4_message.c b/drivers/accel/amdxdna/aie4_message.c
> index 263e23aff69f..2820cfb6f9ed 100644
> --- a/drivers/accel/amdxdna/aie4_message.c
> +++ b/drivers/accel/amdxdna/aie4_message.c
> @@ -263,3 +263,46 @@ int aie4_msg_set_power_mode(struct amdxdna_dev_hdl *ndev, u8 power_mode)
>
> return ret;
> }
> +
> +int aie4_set_runtime_cfg(struct amdxdna_dev_hdl *ndev, u32 type,
> + const void *data, size_t size)
> +{
> + DECLARE_AIE_MSG(aie4_msg_set_runtime_cfg, AIE4_MSG_OP_SET_RUNTIME_CONFIG);
> + u8 buf[sizeof(req.type) + AIE4_RUNTIME_CFG_MAX_DATA_SIZE] __aligned(4) = { 0 };
> + int ret;
> +
> + if (size > AIE4_RUNTIME_CFG_MAX_DATA_SIZE)
> + return -EINVAL;
> +
> + /* Stage runtime config type and payload for firmware mailbox message. */
> + req.type = type;
> + memcpy(buf, &req.type, sizeof(req.type));
> + memcpy(buf + sizeof(req.type), data, size);
> +
> + msg.send_data = buf;
> + msg.send_size = sizeof(req.type) + size;
> +
> + ret = aie_send_mgmt_msg_wait(&ndev->aie, &msg);
> + if (ret)
> + XDNA_ERR(ndev->aie.xdna, "Failed to set runtime cfg %u: %d", type, ret);
> + return ret;
> +}
> +
> +int aie4_set_ctx_hysteresis(struct amdxdna_dev_hdl *ndev, u32 timeout_us)
> +{
> + struct aie4_msg_runtime_config_ctx_switch_hysteresis cfg = {
> + .timeout_us = timeout_us,
> + };
> + int ret;
> +
> + ret = aie4_set_runtime_cfg(ndev, AIE4_RUNTIME_CONFIG_CTX_SWITCH_HYSTERESIS,
> + &cfg, sizeof(cfg));
> + if (ret)
> + XDNA_WARN(ndev->aie.xdna,
> + "Failed to set ctx switch hysteresis to %u us (%d), using fw default",
> + timeout_us, ret);
> + else
> + XDNA_DBG(ndev->aie.xdna, "Context switch hysteresis set to %u us", timeout_us);
> +
> + return ret;
> +}
> diff --git a/drivers/accel/amdxdna/aie4_msg_priv.h b/drivers/accel/amdxdna/aie4_msg_priv.h
> index fe78df9e23c8..636bf8d04c76 100644
> --- a/drivers/accel/amdxdna/aie4_msg_priv.h
> +++ b/drivers/accel/amdxdna/aie4_msg_priv.h
> @@ -12,6 +12,7 @@
> enum aie4_msg_opcode {
> AIE4_MSG_OP_IDENTIFY = 0x10002,
> AIE4_MSG_OP_SUSPEND = 0x10003,
> + AIE4_MSG_OP_SET_RUNTIME_CONFIG = 0x10007,
> AIE4_MSG_OP_QUERY_CERT_FIRMWARE_VERSION = 0x1000F,
>
> AIE4_MSG_OP_CREATE_VFS = 0x20001,
> @@ -65,6 +66,29 @@ struct aie4_msg_suspend_resp {
> enum aie4_msg_status status;
> } __packed;
>
> +/* Type selector for AIE4_MSG_OP_SET_RUNTIME_CONFIG. */
> +enum aie4_msg_runtime_config_type {
> + AIE4_RUNTIME_CONFIG_CTX_SWITCH_HYSTERESIS = 0xD,
> + AIE4_MAX_RUNTIME_CONFIG
> +};
> +
> +struct aie4_msg_set_runtime_cfg_req {
> + __u32 type;
> + __u8 data[4];
> +} __packed;
> +
> +struct aie4_msg_set_runtime_cfg_resp {
> + enum aie4_msg_status status;
> +} __packed;
> +
> +/* Maximum payload for runtime config firmware message. */
> +#define AIE4_RUNTIME_CFG_MAX_DATA_SIZE 16
> +
> +/* Context switch hysteresis timeout in microseconds (0 disables). */
> +struct aie4_msg_runtime_config_ctx_switch_hysteresis {
> + __u32 timeout_us;
> +} __packed;
> +
> struct aie4_msg_create_vfs_req {
> __u32 vf_cnt;
> } __packed;
> diff --git a/drivers/accel/amdxdna/aie4_pci.c b/drivers/accel/amdxdna/aie4_pci.c
> index 5593dfb6c7ed..446ab2f47c7d 100644
> --- a/drivers/accel/amdxdna/aie4_pci.c
> +++ b/drivers/accel/amdxdna/aie4_pci.c
> @@ -5,8 +5,10 @@
>
> #include <drm/amdxdna_accel.h>
> #include <drm/drm_drv.h>
> +#include <drm/drm_file.h>
> #include <drm/drm_managed.h>
> #include <drm/drm_print.h>
> +#include <linux/debugfs.h>
> #include <linux/firmware.h>
> #include <linux/sizes.h>
>
> @@ -322,6 +324,22 @@ int aie4_restore_power_mode(struct amdxdna_dev_hdl *ndev)
> return aie4_msg_set_power_mode(ndev, ndev->pw_mode);
> }
>
> +static int aie4_config_fw(struct amdxdna_dev_hdl *ndev)
> +{
> + int ret;
> +
> + ret = aie4_attach_work_buffer(ndev);
> + if (ret)
> + return ret;
> +
> + /* Best-effort tuning knob; failure is warned inside and does not fail hw start */
> + ret = aie4_set_ctx_hysteresis(ndev, ndev->ctx_switch_hysteresis_us);
> + if (ret == -ETIME)
> + return ret;
> +
> + return 0;
> +}
> +
> static int aie4_pf_hw_start(struct amdxdna_dev_hdl *ndev)
> {
> int ret;
> @@ -334,7 +352,7 @@ static int aie4_pf_hw_start(struct amdxdna_dev_hdl *ndev)
> if (ret)
> goto stop_fw;
>
> - ret = aie4_attach_work_buffer(ndev);
> + ret = aie4_config_fw(ndev);
> if (ret)
> goto mbox_fini;
>
> @@ -418,7 +436,7 @@ static int aie4_classic_hw_start(struct amdxdna_dev_hdl *ndev)
> if (ret)
> goto mailbox_fini;
>
> - ret = aie4_attach_work_buffer(ndev);
> + ret = aie4_config_fw(ndev);
> if (ret)
> goto mailbox_fini;
>
> @@ -573,6 +591,7 @@ static int aie4m_pcidev_init(struct amdxdna_dev *xdna)
>
> ndev->priv = xdna->dev_info->dev_priv;
> ndev->aie.xdna = xdna;
> + ndev->ctx_switch_hysteresis_us = AIE4_CTX_HYSTERESIS_US;
> ndev->pw_mode = POWER_MODE_DEFAULT;
> xdna->dev_handle = ndev;
>
> @@ -918,15 +937,74 @@ static void aie4_classic_fini(struct amdxdna_dev *xdna)
> aie4_free_work_buffer(xdna->dev_handle);
> }
>
> +static int aie4_ctx_hysteresis_get(void *data, u64 *val)
> +{
> + struct amdxdna_dev_hdl *ndev = data;
> + struct amdxdna_dev *xdna = ndev->aie.xdna;
> +
> + guard(mutex)(&xdna->dev_lock);
> + *val = ndev->ctx_switch_hysteresis_us;
> +
> + return 0;
> +}
> +
> +static int aie4_ctx_hysteresis_set(void *data, u64 val)
> +{
> + struct amdxdna_dev_hdl *ndev = data;
> + struct amdxdna_dev *xdna = ndev->aie.xdna;
> + int ret, idx;
> +
> + if (val > U32_MAX)
> + return -EINVAL;
> +
> + if (!drm_dev_enter(&xdna->ddev, &idx))
> + return -ENODEV;
> +
> + mutex_lock(&xdna->dev_lock);
> +
> + ret = amdxdna_pm_resume_get_locked(xdna);
> + if (ret)
> + goto unlock;
> +
> + ret = aie4_set_ctx_hysteresis(ndev, (u32)val);
> + if (!ret)
> + ndev->ctx_switch_hysteresis_us = (u32)val;
> +
> + amdxdna_pm_suspend_put(xdna);
> +
> +unlock:
> + mutex_unlock(&xdna->dev_lock);
> + drm_dev_exit(idx);
> +
> + return ret;
> +}
> +
> +/* Context switch hysteresis timeout in microseconds; 0 disables hysteresis. */
> +DEFINE_DEBUGFS_ATTRIBUTE(aie4_ctx_hysteresis_fops, aie4_ctx_hysteresis_get,
> + aie4_ctx_hysteresis_set, "%llu\n");
> +
> +static void aie4_debugfs_init(struct amdxdna_dev *xdna)
> +{
> + struct amdxdna_dev_hdl *ndev = xdna->dev_handle;
> +
> + /* Context switch hysteresis is only supported on PF and classic devices. */
> + if (!to_pci_dev(xdna->ddev.dev)->is_virtfn)
> + debugfs_create_file_unsafe("ctx_switch_hysteresis_us", 0600,
> + xdna->ddev.accel->debugfs_root, ndev,
> + &aie4_ctx_hysteresis_fops);
> +}
> +
> const struct amdxdna_dev_ops aie4_pf_ops = {
> .init = aie4_pf_init,
> .fini = aie4_pf_fini,
> + .debugfs_init = aie4_debugfs_init,
> .sriov_configure = aie4_sriov_configure,
> };
>
> const struct amdxdna_dev_ops aie4_vf_ops = {
> .init = aie4_vf_init,
> .fini = aie4_vf_fini,
> + .debugfs_init = aie4_debugfs_init,
> .hwctx_init = aie4_hwctx_init,
> .hwctx_fini = aie4_hwctx_fini,
> .cmd_wait = aie4_cmd_wait,
> @@ -937,6 +1015,7 @@ const struct amdxdna_dev_ops aie4_vf_ops = {
> const struct amdxdna_dev_ops aie4_classic_ops = {
> .init = aie4_classic_init,
> .fini = aie4_classic_fini,
> + .debugfs_init = aie4_debugfs_init,
> .hwctx_init = aie4_hwctx_init,
> .hwctx_fini = aie4_hwctx_fini,
> .cmd_wait = aie4_cmd_wait,
> diff --git a/drivers/accel/amdxdna/aie4_pci.h b/drivers/accel/amdxdna/aie4_pci.h
> index 6e9e7f874a44..959ef3695813 100644
> --- a/drivers/accel/amdxdna/aie4_pci.h
> +++ b/drivers/accel/amdxdna/aie4_pci.h
> @@ -14,6 +14,9 @@
> #include "aie4_msg_priv.h"
> #include "amdxdna_mailbox.h"
>
> +/* Default context switch hysteresis timeout in microseconds. */
> +#define AIE4_CTX_HYSTERESIS_US 1000
> +
> struct cert_comp {
> struct amdxdna_dev_hdl *ndev;
> u32 msix_idx;
> @@ -69,6 +72,9 @@ struct amdxdna_dev_hdl {
>
> u8 pw_mode;
>
> + /* Context switch hysteresis timeout in microseconds. */
> + u32 ctx_switch_hysteresis_us;
> +
> struct amdxdna_drm_query_firmware_version cert_version;
> };
>
> @@ -92,6 +98,9 @@ int aie4_init_dpm_freq_table(struct amdxdna_dev_hdl *ndev);
> int aie4_query_dpm_level(struct amdxdna_dev_hdl *ndev,
> u32 *aieclk_dpm_level, u32 *npuhclk_dpm_level);
> int aie4_msg_set_power_mode(struct amdxdna_dev_hdl *ndev, u8 power_mode);
> +int aie4_set_runtime_cfg(struct amdxdna_dev_hdl *ndev, u32 type,
> + const void *data, size_t size);
> +int aie4_set_ctx_hysteresis(struct amdxdna_dev_hdl *ndev, u32 timeout_us);
> u32 aie4_msg_pasid(struct amdxdna_client *client);
>
> /* aie4_ctx.c */
> diff --git a/drivers/accel/amdxdna/amdxdna_debugfs.c b/drivers/accel/amdxdna/amdxdna_debugfs.c
> index a6ec17c63629..1f63cc91b168 100644
> --- a/drivers/accel/amdxdna/amdxdna_debugfs.c
> +++ b/drivers/accel/amdxdna/amdxdna_debugfs.c
> @@ -126,4 +126,7 @@ void amdxdna_debugfs_init(struct amdxdna_dev *xdna)
> xdna,
> amdxdna_dbgfs_files[i].fops);
> }
> +
> + if (xdna->dev_info->ops->debugfs_init)
> + xdna->dev_info->ops->debugfs_init(xdna);
> }
> diff --git a/drivers/accel/amdxdna/amdxdna_pci_drv.h b/drivers/accel/amdxdna/amdxdna_pci_drv.h
> index 953bf783b3f7..11f46ec738d7 100644
> --- a/drivers/accel/amdxdna/amdxdna_pci_drv.h
> +++ b/drivers/accel/amdxdna/amdxdna_pci_drv.h
> @@ -54,6 +54,7 @@ struct amdxdna_sched_job;
> struct amdxdna_dev_ops {
> int (*init)(struct amdxdna_dev *xdna);
> void (*fini)(struct amdxdna_dev *xdna);
> + void (*debugfs_init)(struct amdxdna_dev *xdna);
Reviewed-by: Lizhi Hou <lizhi.hou@amd.com>
> int (*resume)(struct amdxdna_dev *xdna);
> int (*suspend)(struct amdxdna_dev *xdna);
> int (*sriov_configure)(struct amdxdna_dev *xdna, int num_vfs);
next prev parent reply other threads:[~2026-10-13 18:29 UTC|newest]
Thread overview: 33+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-10-09 22:53 [PATCH V4 00/19] accel/amdxdna: Kernel submission and PM for AIE4 David Zhang
2026-10-09 22:53 ` [PATCH V4 01/19] accel/amdxdna: Rename NPU3 firmware files David Zhang
2026-10-09 22:53 ` [PATCH V4 02/19] accel/amdxdna: Remove mmap for doorbell David Zhang
2026-10-12 20:37 ` Lizhi Hou
2026-10-09 22:53 ` [PATCH V4 03/19] accel/amdxdna: Add CERT firmware version support David Zhang
2026-10-12 20:39 ` Lizhi Hou
2026-10-09 22:53 ` [PATCH V4 04/19] accel/amdxdna: Support firmware 6.0 David Zhang
2026-10-12 20:41 ` Lizhi Hou
2026-10-09 22:53 ` [PATCH V4 05/19] accel/amdxdna: Add NPU3 classic device support David Zhang
2026-10-12 20:41 ` Lizhi Hou
2026-10-09 22:53 ` [PATCH V4 06/19] accel/amdxdna: Add AIE version query to aie4_get_info David Zhang
2026-10-12 20:55 ` Lizhi Hou
2026-10-09 22:53 ` [PATCH V4 07/19] accel/amdxdna: Add get and set power_mode for AIE4 David Zhang
2026-10-12 21:29 ` Lizhi Hou
2026-10-09 22:53 ` [PATCH V4 08/19] accel/amdxdna: Add clock, DPM frequency, and resource info queries " David Zhang
2026-10-12 22:58 ` Lizhi Hou
2026-10-09 22:53 ` [PATCH V4 09/19] accel/amdxdna: Add context switch hysteresis with debugfs control David Zhang
2026-10-13 18:29 ` Lizhi Hou [this message]
2026-10-09 22:53 ` [PATCH V4 10/19] accel/amdxdna: Refactor AIE4 hardware initialization sequence David Zhang
2026-10-13 18:33 ` Lizhi Hou
2026-10-09 22:53 ` [PATCH V4 11/19] accel/amdxdna: Decouple AIE4 doorbell and MSI-X notify transport hooks David Zhang
2026-10-13 18:38 ` Lizhi Hou
2026-10-09 22:53 ` [PATCH V4 12/19] accel/amdxdna: Implement AIE4 kernel queue lifecycle and memory layout David Zhang
2026-10-13 18:41 ` Lizhi Hou
2026-10-09 22:53 ` [PATCH V4 13/19] accel/amdxdna: Prepare for AIE4 command submission David Zhang
2026-10-13 18:42 ` Lizhi Hou
2026-10-09 22:53 ` [PATCH V4 14/19] accel/amdxdna: Move HMM invalidate wait into common GEM code David Zhang
2026-10-13 18:45 ` Lizhi Hou
2026-10-09 22:53 ` [PATCH V4 15/19] accel/amdxdna: Make populate_range common for AIE2 and AIE4 David Zhang
2026-10-09 22:53 ` [PATCH V4 16/19] accel/amdxdna: Implement AIE4 command packet building and submission David Zhang
2026-10-09 22:53 ` [PATCH V4 17/19] accel/amdxdna: Enable AIE4 firmware logging to DRAM David Zhang
2026-10-09 22:53 ` [PATCH V4 18/19] accel/amdxdna: Implement AIE4 suspend and resume David Zhang
2026-10-09 22:53 ` [PATCH V4 19/19] accel/amdxdna: Implement runtime suspend and resume support David Zhang
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