* [PATCH v4 01/13] iio: adc: ad4134: Adjust register map range
2026-10-06 18:15 [PATCH v4 00/13] iio: adc: ad4134: Enable greater sample rate data capture Marcelo Schmitt
@ 2026-10-06 18:16 ` Marcelo Schmitt
2026-10-06 18:16 ` [PATCH v4 02/13] iio: adc: ad4134: Sign extend sample data Marcelo Schmitt
` (11 subsequent siblings)
12 siblings, 0 replies; 14+ messages in thread
From: Marcelo Schmitt @ 2026-10-06 18:16 UTC (permalink / raw)
To: linux-iio, devicetree, linux-kernel, linux
Cc: jic23, nuno.sa, dlechner, andy, Michael.Hennerich, robh, krzk+dt,
conor+dt, corbet, skhan, marcelo.schmitt1
Due to a off-by-one mistake, privileged users would be able to read from an
unsupported register address when reading device registers through a debug
interface. Correct the off-by-one mistake at the high register map range to
prevent access of unsupported addresses.
Fixes: e0bc6d7e2584 ("iio: adc: Initial support for AD4134")
Signed-off-by: Marcelo Schmitt <marcelo.schmitt@analog.com>
---
No changes in v4.
drivers/iio/adc/ad4134.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/iio/adc/ad4134.c b/drivers/iio/adc/ad4134.c
index 70f80bf1825f..e53c10b9a44a 100644
--- a/drivers/iio/adc/ad4134.c
+++ b/drivers/iio/adc/ad4134.c
@@ -111,7 +111,7 @@ static const struct regmap_range ad4134_regmap_rd_range[] = {
regmap_reg_range(AD4134_IFACE_CONFIG_A_REG, AD4134_SILICON_REV_REG),
regmap_reg_range(AD4134_SCRATCH_PAD_REG, AD4134_PW_DOWN_CTRL_REG),
regmap_reg_range(AD4134_DEVICE_STATUS_REG, AD4134_AIN_OR_ERROR_REG),
- regmap_reg_range(AD4134_CH_VREG(0), AD4134_CH_VREG(AD4134_NUM_CHANNELS)),
+ regmap_reg_range(AD4134_CH_VREG(0), AD4134_CH_VREG(AD4134_NUM_CHANNELS - 1)),
};
static const struct regmap_range ad4134_regmap_wr_range[] = {
@@ -244,7 +244,7 @@ static const struct regmap_config ad4134_regmap_config = {
.reg_write = ad4134_reg_write,
.rd_table = &ad4134_regmap_rd_table,
.wr_table = &ad4134_regmap_wr_table,
- .max_register = AD4134_CH_VREG(ARRAY_SIZE(ad4134_chan_set)),
+ .max_register = AD4134_CH_VREG(ARRAY_SIZE(ad4134_chan_set) - 1),
};
static int ad4134_read_raw(struct iio_dev *indio_dev,
--
2.53.0
^ permalink raw reply [flat|nested] 14+ messages in thread* [PATCH v4 02/13] iio: adc: ad4134: Sign extend sample data
2026-10-06 18:15 [PATCH v4 00/13] iio: adc: ad4134: Enable greater sample rate data capture Marcelo Schmitt
2026-10-06 18:16 ` [PATCH v4 01/13] iio: adc: ad4134: Adjust register map range Marcelo Schmitt
@ 2026-10-06 18:16 ` Marcelo Schmitt
2026-10-06 18:16 ` [PATCH v4 03/13] iio: adc: ad4134: Update include list to comply with IWYU principles Marcelo Schmitt
` (10 subsequent siblings)
12 siblings, 0 replies; 14+ messages in thread
From: Marcelo Schmitt @ 2026-10-06 18:16 UTC (permalink / raw)
To: linux-iio, devicetree, linux-kernel, linux
Cc: jic23, nuno.sa, dlechner, andy, Michael.Hennerich, robh, krzk+dt,
conor+dt, corbet, skhan, marcelo.schmitt1, Joshua Crofts
Sign extend ADC sample data for correct delivery of negative ADC input
difference.
Reviewed-by: Joshua Crofts <joshua.crofts1@gmail.com>
Fixes: e0bc6d7e2584 ("iio: adc: Initial support for AD4134")
Signed-off-by: Marcelo Schmitt <marcelo.schmitt@analog.com>
---
No changes in v4.
drivers/iio/adc/ad4134.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/iio/adc/ad4134.c b/drivers/iio/adc/ad4134.c
index e53c10b9a44a..6fdeb27d7a42 100644
--- a/drivers/iio/adc/ad4134.c
+++ b/drivers/iio/adc/ad4134.c
@@ -172,6 +172,7 @@ static int ad4134_data_read(struct ad4134_state *st, unsigned int reg,
unsigned int *val)
{
unsigned int i;
+ u32 sample;
int ret;
/*
@@ -196,8 +197,9 @@ static int ad4134_data_read(struct ad4134_state *st, unsigned int reg,
* Clock out data from all channels to avoid that.
*/
if (i == AD4134_VREG_CH(reg))
- *val = get_unaligned_be24(st->rx_buf);
+ sample = get_unaligned_be24(st->rx_buf);
}
+ *val = sign_extend32(sample, AD4134_CHAN_PRECISION_BITS - 1);
return 0;
}
--
2.53.0
^ permalink raw reply [flat|nested] 14+ messages in thread* [PATCH v4 03/13] iio: adc: ad4134: Update include list to comply with IWYU principles
2026-10-06 18:15 [PATCH v4 00/13] iio: adc: ad4134: Enable greater sample rate data capture Marcelo Schmitt
2026-10-06 18:16 ` [PATCH v4 01/13] iio: adc: ad4134: Adjust register map range Marcelo Schmitt
2026-10-06 18:16 ` [PATCH v4 02/13] iio: adc: ad4134: Sign extend sample data Marcelo Schmitt
@ 2026-10-06 18:16 ` Marcelo Schmitt
2026-10-06 18:17 ` [PATCH v4 04/13] iio: adc: ad4134: Serialize single-read operations Marcelo Schmitt
` (9 subsequent siblings)
12 siblings, 0 replies; 14+ messages in thread
From: Marcelo Schmitt @ 2026-10-06 18:16 UTC (permalink / raw)
To: linux-iio, devicetree, linux-kernel, linux
Cc: jic23, nuno.sa, dlechner, andy, Michael.Hennerich, robh, krzk+dt,
conor+dt, corbet, skhan, marcelo.schmitt1, Andy Shevchenko
Add includes that were missing (according to include-what-you-use tool)
to comply with include what is used principles. Namely, add time64.h for
USEC_PER_SEC.
Remove time.h which is covered by time64.h and iio/types.h which is
covered by iio/iio.h.
While updating the list, organize it to follow current IIO include list
convention.
Reviewed-by: Andy Shevchenko <andriy.shevchenko@intel.com>
Signed-off-by: Marcelo Schmitt <marcelo.schmitt@analog.com>
---
No changes in v4.
drivers/iio/adc/ad4134.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/iio/adc/ad4134.c b/drivers/iio/adc/ad4134.c
index 6fdeb27d7a42..4c8adb8efe4e 100644
--- a/drivers/iio/adc/ad4134.c
+++ b/drivers/iio/adc/ad4134.c
@@ -14,18 +14,18 @@
#include <linux/err.h>
#include <linux/export.h>
#include <linux/gpio/consumer.h>
-#include <linux/iio/iio.h>
-#include <linux/iio/types.h>
#include <linux/module.h>
#include <linux/regmap.h>
#include <linux/regulator/consumer.h>
#include <linux/reset.h>
#include <linux/spi/spi.h>
-#include <linux/time.h>
+#include <linux/time64.h>
#include <linux/types.h>
#include <linux/unaligned.h>
#include <linux/units.h>
+#include <linux/iio/iio.h>
+
#define AD4134_RESET_TIME_US (10 * USEC_PER_SEC)
#define AD4134_REG_READ_MASK BIT(7)
--
2.53.0
^ permalink raw reply [flat|nested] 14+ messages in thread* [PATCH v4 04/13] iio: adc: ad4134: Serialize single-read operations
2026-10-06 18:15 [PATCH v4 00/13] iio: adc: ad4134: Enable greater sample rate data capture Marcelo Schmitt
` (2 preceding siblings ...)
2026-10-06 18:16 ` [PATCH v4 03/13] iio: adc: ad4134: Update include list to comply with IWYU principles Marcelo Schmitt
@ 2026-10-06 18:17 ` Marcelo Schmitt
2026-10-06 18:17 ` [PATCH v4 05/13] iio: adc: ad4134: Run shorter transfers when CRC is disabled Marcelo Schmitt
` (8 subsequent siblings)
12 siblings, 0 replies; 14+ messages in thread
From: Marcelo Schmitt @ 2026-10-06 18:17 UTC (permalink / raw)
To: linux-iio, devicetree, linux-kernel, linux
Cc: jic23, nuno.sa, dlechner, andy, Michael.Hennerich, robh, krzk+dt,
conor+dt, corbet, skhan, marcelo.schmitt1, Andy Shevchenko
Protect single-sample read operations from going wrong if two or more of
them run concurrently. Serialize the data read operation so to avoid
single-sample read requests disrupting each other.
Reviewed-by: Andy Shevchenko <andriy.shevchenko@intel.com>
Signed-off-by: Marcelo Schmitt <marcelo.schmitt@analog.com>
---
Change log v3 -> v4:
- Fixed typo in code comment.
drivers/iio/adc/ad4134.c | 16 +++++++++++++++-
1 file changed, 15 insertions(+), 1 deletion(-)
diff --git a/drivers/iio/adc/ad4134.c b/drivers/iio/adc/ad4134.c
index 4c8adb8efe4e..a0113fff4b71 100644
--- a/drivers/iio/adc/ad4134.c
+++ b/drivers/iio/adc/ad4134.c
@@ -7,6 +7,7 @@
#include <linux/array_size.h>
#include <linux/bitfield.h>
#include <linux/bitops.h>
+#include <linux/cleanup.h>
#include <linux/clk.h>
#include <linux/crc8.h>
#include <linux/delay.h>
@@ -15,6 +16,7 @@
#include <linux/export.h>
#include <linux/gpio/consumer.h>
#include <linux/module.h>
+#include <linux/mutex.h>
#include <linux/regmap.h>
#include <linux/regulator/consumer.h>
#include <linux/reset.h>
@@ -98,6 +100,11 @@ struct ad4134_state {
struct regmap *regmap;
unsigned long sys_clk_hz;
struct gpio_desc *odr_gpio;
+ /*
+ * Synchronize access to device state fields and ensure atomicity of
+ * consecutive register access operations.
+ */
+ struct mutex sync_lock;
int refin_mv;
/*
* DMA (thus cache coherency maintenance) requires the transfer buffers
@@ -257,7 +264,9 @@ static int ad4134_read_raw(struct iio_dev *indio_dev,
int ret;
switch (info) {
- case IIO_CHAN_INFO_RAW:
+ case IIO_CHAN_INFO_RAW: {
+ guard(mutex)(&st->sync_lock);
+
gpiod_set_value_cansleep(st->odr_gpio, 1);
/*
* For slave mode gated DCLK (data sheet page 11), the minimum
@@ -276,6 +285,7 @@ static int ad4134_read_raw(struct iio_dev *indio_dev,
return ret;
return IIO_VAL_INT;
+ }
case IIO_CHAN_INFO_SCALE:
*val = st->refin_mv;
*val2 = AD4134_CHAN_PRECISION_BITS - 1;
@@ -444,6 +454,10 @@ static int ad4134_probe(struct spi_device *spi)
crc8_populate_msb(ad4134_spi_crc_table, AD4134_SPI_CRC_POLYNOM);
+ ret = devm_mutex_init(dev, &st->sync_lock);
+ if (ret)
+ return ret;
+
st->regmap = devm_regmap_init(dev, NULL, st, &ad4134_regmap_config);
if (IS_ERR(st->regmap))
return dev_err_probe(dev, PTR_ERR(st->regmap),
--
2.53.0
^ permalink raw reply [flat|nested] 14+ messages in thread* [PATCH v4 05/13] iio: adc: ad4134: Run shorter transfers when CRC is disabled
2026-10-06 18:15 [PATCH v4 00/13] iio: adc: ad4134: Enable greater sample rate data capture Marcelo Schmitt
` (3 preceding siblings ...)
2026-10-06 18:17 ` [PATCH v4 04/13] iio: adc: ad4134: Serialize single-read operations Marcelo Schmitt
@ 2026-10-06 18:17 ` Marcelo Schmitt
2026-10-06 18:17 ` [PATCH v4 06/13] iio: adc: ad4134: Add support for digital filter type selection Marcelo Schmitt
` (7 subsequent siblings)
12 siblings, 0 replies; 14+ messages in thread
From: Marcelo Schmitt @ 2026-10-06 18:17 UTC (permalink / raw)
To: linux-iio, devicetree, linux-kernel, linux
Cc: jic23, nuno.sa, dlechner, andy, Michael.Hennerich, robh, krzk+dt,
conor+dt, corbet, skhan, marcelo.schmitt1
When AD4134 has its SPI CRC feature enabled, one extra byte (the CRC code)
is sent through SPI for both ends to verify the integrity of data
transfers. Though, when CRC is not enabled, SPI transfers can be shorter.
Signed-off-by: Marcelo Schmitt <marcelo.schmitt@analog.com>
---
drivers/iio/adc/ad4134.c | 10 ++++++----
1 file changed, 6 insertions(+), 4 deletions(-)
diff --git a/drivers/iio/adc/ad4134.c b/drivers/iio/adc/ad4134.c
index a0113fff4b71..85fa16321d74 100644
--- a/drivers/iio/adc/ad4134.c
+++ b/drivers/iio/adc/ad4134.c
@@ -106,6 +106,7 @@ struct ad4134_state {
*/
struct mutex sync_lock;
int refin_mv;
+ bool crc_en;
/*
* DMA (thus cache coherency maintenance) requires the transfer buffers
* to live in their own cache lines.
@@ -159,7 +160,7 @@ static int ad4134_reg_write(void *context, unsigned int reg, unsigned int val)
struct spi_transfer xfer = {
.tx_buf = st->tx_buf,
.rx_buf = st->rx_buf,
- .len = AD4134_SPI_MAX_XFER_LEN,
+ .len = st->crc_en ? AD4134_SPI_MAX_XFER_LEN : 2,
};
int ret;
@@ -169,7 +170,7 @@ static int ad4134_reg_write(void *context, unsigned int reg, unsigned int val)
if (ret)
return ret;
- if (st->rx_buf[2] != st->tx_buf[2])
+ if (st->crc_en && st->rx_buf[2] != st->tx_buf[2])
dev_dbg(&st->spi->dev, "reg write CRC check failed\n");
return 0;
@@ -217,7 +218,7 @@ static int ad4134_register_read(struct ad4134_state *st, unsigned int reg,
struct spi_transfer xfer = {
.tx_buf = st->tx_buf,
.rx_buf = st->rx_buf,
- .len = AD4134_SPI_MAX_XFER_LEN,
+ .len = st->crc_en ? AD4134_SPI_MAX_XFER_LEN : 2,
};
unsigned int inst;
int ret;
@@ -232,7 +233,7 @@ static int ad4134_register_read(struct ad4134_state *st, unsigned int reg,
*val = st->rx_buf[1];
/* Check CRC */
- if (st->rx_buf[2] != st->tx_buf[2])
+ if (st->crc_en && st->rx_buf[2] != st->tx_buf[2])
dev_dbg(&st->spi->dev, "reg read CRC check failed\n");
return 0;
@@ -313,6 +314,7 @@ static int ad4134_min_io_mode_setup(struct ad4134_state *st)
struct device *dev = &st->spi->dev;
int ret;
+ st->crc_en = true; /* In minimum I/O mode CRC cannot be disabled */
st->odr_gpio = devm_gpiod_get(dev, "odr", GPIOD_OUT_LOW);
if (IS_ERR(st->odr_gpio))
return dev_err_probe(dev, PTR_ERR(st->odr_gpio),
--
2.53.0
^ permalink raw reply [flat|nested] 14+ messages in thread* [PATCH v4 06/13] iio: adc: ad4134: Add support for digital filter type selection
2026-10-06 18:15 [PATCH v4 00/13] iio: adc: ad4134: Enable greater sample rate data capture Marcelo Schmitt
` (4 preceding siblings ...)
2026-10-06 18:17 ` [PATCH v4 05/13] iio: adc: ad4134: Run shorter transfers when CRC is disabled Marcelo Schmitt
@ 2026-10-06 18:17 ` Marcelo Schmitt
2026-10-06 18:17 ` [PATCH v4 07/13] iio: adc: ad4134: Support buffered data read Marcelo Schmitt
` (6 subsequent siblings)
12 siblings, 0 replies; 14+ messages in thread
From: Marcelo Schmitt @ 2026-10-06 18:17 UTC (permalink / raw)
To: linux-iio, devicetree, linux-kernel, linux
Cc: jic23, nuno.sa, dlechner, andy, Michael.Hennerich, robh, krzk+dt,
conor+dt, corbet, skhan, marcelo.schmitt1
AD4134 supports four types of programmable digital filters that allow users
to choose between different output data rates and input bandwidths. Enable
basic digital filter configuration by providing a way to select which
filter type is activated for each channel.
Signed-off-by: Marcelo Schmitt <marcelo.schmitt@analog.com>
---
No changes in v4.
drivers/iio/adc/ad4134.c | 76 ++++++++++++++++++++++++++++++++++++++++
1 file changed, 76 insertions(+)
diff --git a/drivers/iio/adc/ad4134.c b/drivers/iio/adc/ad4134.c
index 85fa16321d74..3048e61a3cb1 100644
--- a/drivers/iio/adc/ad4134.c
+++ b/drivers/iio/adc/ad4134.c
@@ -63,6 +63,9 @@
#define AD4134_PW_DOWN_CTRL_REG 0x13
#define AD4134_DEVICE_STATUS_REG 0x15
#define AD4134_ODR_VAL_INT_LSB_REG 0x16
+#define AD4134_CHAN_DIG_FILTER_SEL_REG 0x1E
+#define AD4134_CHAN_DIG_FILTER_SEL_CH_MASK(ch) (GENMASK(1, 0) << 2 * (ch))
+
#define AD4134_CH3_OFFSET_MSB_REG 0x3E
#define AD4134_AIN_OR_ERROR_REG 0x48
@@ -80,12 +83,47 @@
#define AD4134_SPI_CRC_INIT_VALUE 0xA5
static unsigned char ad4134_spi_crc_table[CRC8_TABLE_SIZE];
+enum ad4134_filter_type {
+ AD4134_WIDEBAND,
+ AD4134_SINC6,
+ AD4134_SINC3,
+ AD4134_SINC3_REJ60,
+};
+
+static const char * const ad4134_filt_names[] = {
+ [AD4134_WIDEBAND] = "wideband",
+ [AD4134_SINC6] = "sinc6",
+ [AD4134_SINC3] = "sinc3",
+ [AD4134_SINC3_REJ60] = "sinc3+rej60",
+};
+
+static int ad4134_get_filter_type(struct iio_dev *indio_dev,
+ struct iio_chan_spec const *chan);
+
+static int ad4134_set_filter_type(struct iio_dev *indio_dev,
+ struct iio_chan_spec const *chan,
+ unsigned int val);
+
+static const struct iio_enum ad4134_filter_type_enum = {
+ .items = ad4134_filt_names,
+ .num_items = ARRAY_SIZE(ad4134_filt_names),
+ .get = ad4134_get_filter_type,
+ .set = ad4134_set_filter_type,
+};
+
+static const struct iio_chan_spec_ext_info ad4134_filter_type_ext_info[] = {
+ IIO_ENUM("filter_type", IIO_SEPARATE, &ad4134_filter_type_enum),
+ IIO_ENUM_AVAILABLE("filter_type", IIO_SEPARATE, &ad4134_filter_type_enum),
+ { }
+};
+
#define AD4134_CHANNEL(_index) { \
.type = IIO_VOLTAGE, \
.indexed = 1, \
.channel = (_index), \
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
.info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \
+ .ext_info = ad4134_filter_type_ext_info, \
}
static const struct iio_chan_spec ad4134_chan_set[] = {
@@ -115,6 +153,44 @@ struct ad4134_state {
u8 tx_buf[AD4134_SPI_MAX_XFER_LEN];
};
+static int ad4134_set_filter_type(struct iio_dev *indio_dev,
+ struct iio_chan_spec const *chan,
+ unsigned int val)
+{
+ struct ad4134_state *st = iio_priv(indio_dev);
+ unsigned int mask, reg_val;
+
+ IIO_DEV_ACQUIRE_DIRECT_MODE(indio_dev, claim);
+ if (IIO_DEV_ACQUIRE_FAILED(claim))
+ return -EBUSY;
+
+ guard(mutex)(&st->sync_lock);
+
+ mask = AD4134_CHAN_DIG_FILTER_SEL_CH_MASK(chan->channel);
+ reg_val = field_prep(mask, val);
+ return regmap_update_bits(st->regmap, AD4134_CHAN_DIG_FILTER_SEL_REG,
+ mask, reg_val);
+}
+
+static int ad4134_get_filter_type(struct iio_dev *indio_dev,
+ struct iio_chan_spec const *chan)
+{
+ struct ad4134_state *st = iio_priv(indio_dev);
+ unsigned int mask, reg_val;
+ int ret;
+
+ IIO_DEV_ACQUIRE_DIRECT_MODE(indio_dev, claim);
+ if (IIO_DEV_ACQUIRE_FAILED(claim))
+ return -EBUSY;
+
+ ret = regmap_read(st->regmap, AD4134_CHAN_DIG_FILTER_SEL_REG, ®_val);
+ if (ret)
+ return ret;
+
+ mask = AD4134_CHAN_DIG_FILTER_SEL_CH_MASK(chan->channel);
+ return field_get(mask, reg_val);
+}
+
static const struct regmap_range ad4134_regmap_rd_range[] = {
regmap_reg_range(AD4134_IFACE_CONFIG_A_REG, AD4134_SILICON_REV_REG),
regmap_reg_range(AD4134_SCRATCH_PAD_REG, AD4134_PW_DOWN_CTRL_REG),
--
2.53.0
^ permalink raw reply [flat|nested] 14+ messages in thread* [PATCH v4 07/13] iio: adc: ad4134: Support buffered data read
2026-10-06 18:15 [PATCH v4 00/13] iio: adc: ad4134: Enable greater sample rate data capture Marcelo Schmitt
` (5 preceding siblings ...)
2026-10-06 18:17 ` [PATCH v4 06/13] iio: adc: ad4134: Add support for digital filter type selection Marcelo Schmitt
@ 2026-10-06 18:17 ` Marcelo Schmitt
2026-10-06 18:18 ` [PATCH v4 08/13] dt-bindings: iio: adc: adi,ad4134: Document SPI connection mode Marcelo Schmitt
` (5 subsequent siblings)
12 siblings, 0 replies; 14+ messages in thread
From: Marcelo Schmitt @ 2026-10-06 18:17 UTC (permalink / raw)
To: linux-iio, devicetree, linux-kernel, linux
Cc: jic23, nuno.sa, dlechner, andy, Michael.Hennerich, robh, krzk+dt,
conor+dt, corbet, skhan, marcelo.schmitt1
Enable users to run buffered data captures triggered by IIO trigger device.
Add an IIO timestamp channel so each data scan is provided with measurement
time information. Require single-read operations to be in IIO device direct
access mode to prevent buffered and single-shot data captures to disrupt
each other.
Signed-off-by: Marcelo Schmitt <marcelo.schmitt@analog.com>
---
Change log v3 -> v4:
- Now grabbing the whole data scan with a single SPI transfer.
drivers/iio/adc/Kconfig | 2 ++
drivers/iio/adc/ad4134.c | 64 ++++++++++++++++++++++++++++++++++++++--
2 files changed, 64 insertions(+), 2 deletions(-)
diff --git a/drivers/iio/adc/Kconfig b/drivers/iio/adc/Kconfig
index a802d8ee4dd9..fc7de0bb400a 100644
--- a/drivers/iio/adc/Kconfig
+++ b/drivers/iio/adc/Kconfig
@@ -125,6 +125,8 @@ config AD4134
depends on SPI
select REGMAP_SPI
select CRC8
+ select IIO_BUFFER
+ select IIO_TRIGGERED_BUFFER
help
Say yes here to build support for Analog Devices AD4134 SPI analog to
digital converters (ADC).
diff --git a/drivers/iio/adc/ad4134.c b/drivers/iio/adc/ad4134.c
index 3048e61a3cb1..b5207f16054e 100644
--- a/drivers/iio/adc/ad4134.c
+++ b/drivers/iio/adc/ad4134.c
@@ -26,7 +26,10 @@
#include <linux/unaligned.h>
#include <linux/units.h>
+#include <linux/iio/buffer.h>
#include <linux/iio/iio.h>
+#include <linux/iio/triggered_buffer.h>
+#include <linux/iio/trigger_consumer.h>
#define AD4134_RESET_TIME_US (10 * USEC_PER_SEC)
@@ -124,6 +127,13 @@ static const struct iio_chan_spec_ext_info ad4134_filter_type_ext_info[] = {
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
.info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \
.ext_info = ad4134_filter_type_ext_info, \
+ .scan_index = (_index), \
+ .scan_type = { \
+ .format = IIO_SCAN_FORMAT_SIGNED_INT, \
+ .realbits = AD4134_CHAN_PRECISION_BITS, \
+ .storagebits = 32, \
+ .endianness = IIO_CPU, \
+ }, \
}
static const struct iio_chan_spec ad4134_chan_set[] = {
@@ -131,6 +141,7 @@ static const struct iio_chan_spec ad4134_chan_set[] = {
AD4134_CHANNEL(1),
AD4134_CHANNEL(2),
AD4134_CHANNEL(3),
+ IIO_CHAN_SOFT_TIMESTAMP(4),
};
struct ad4134_state {
@@ -149,7 +160,7 @@ struct ad4134_state {
* DMA (thus cache coherency maintenance) requires the transfer buffers
* to live in their own cache lines.
*/
- u8 rx_buf[AD4134_SPI_MAX_XFER_LEN] __aligned(IIO_DMA_MINALIGN);
+ u8 rx_buf[AD4134_SPI_MAX_XFER_LEN * AD4134_NUM_CHANNELS] __aligned(IIO_DMA_MINALIGN);
u8 tx_buf[AD4134_SPI_MAX_XFER_LEN];
};
@@ -269,7 +280,7 @@ static int ad4134_data_read(struct ad4134_state *st, unsigned int reg,
* interface. Now we read data from all channels but keep only the bits
* from the requested one.
*/
- for (i = 0; i < ARRAY_SIZE(ad4134_chan_set); i++) {
+ for (i = 0; i < AD4134_NUM_CHANNELS; i++) {
ret = spi_write_then_read(st->spi, NULL, 0, st->rx_buf,
BITS_TO_BYTES(AD4134_CHAN_PRECISION_BITS));
if (ret)
@@ -333,6 +344,44 @@ static const struct regmap_config ad4134_regmap_config = {
.max_register = AD4134_CH_VREG(ARRAY_SIZE(ad4134_chan_set) - 1),
};
+static irqreturn_t ad4134_trigger_handler(int irq, void *p)
+{
+ IIO_DECLARE_BUFFER_WITH_TS(u32, channels, AD4134_NUM_CHANNELS) = { };
+ unsigned int chan_bytes = BITS_TO_BYTES(AD4134_CHAN_PRECISION_BITS);
+ struct iio_poll_func *pf = p;
+ struct iio_dev *indio_dev = pf->indio_dev;
+ struct ad4134_state *st = iio_priv(indio_dev);
+ struct spi_transfer xfer = {
+ .rx_buf = st->rx_buf,
+ .cs_off = true,
+ .len = chan_bytes * AD4134_NUM_CHANNELS,
+ };
+ int ret;
+
+ gpiod_set_value_cansleep(st->odr_gpio, 1);
+ fsleep(1);
+ gpiod_set_value_cansleep(st->odr_gpio, 0);
+
+ /* Run enough DCLK cycles to match the data frame length. */
+ ret = spi_sync_transfer(st->spi, &xfer, 1);
+ if (ret)
+ goto out;
+
+ for (int ch = 0, i = 0; ch < AD4134_NUM_CHANNELS; ch++) {
+ if (!test_bit(ch, indio_dev->active_scan_mask))
+ continue;
+
+ channels[i++] = get_unaligned_be24(&st->rx_buf[ch * chan_bytes]);
+ }
+
+ iio_push_to_buffers_with_ts(indio_dev, channels, sizeof(channels),
+ pf->timestamp);
+
+out:
+ iio_trigger_notify_done(indio_dev->trig);
+ return IRQ_HANDLED;
+}
+
static int ad4134_read_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan,
int *val, int *val2, long info)
@@ -342,6 +391,10 @@ static int ad4134_read_raw(struct iio_dev *indio_dev,
switch (info) {
case IIO_CHAN_INFO_RAW: {
+ IIO_DEV_ACQUIRE_DIRECT_MODE(indio_dev, claim);
+ if (IIO_DEV_ACQUIRE_FAILED(claim))
+ return -EBUSY;
+
guard(mutex)(&st->sync_lock);
gpiod_set_value_cansleep(st->odr_gpio, 1);
@@ -546,6 +599,13 @@ static int ad4134_probe(struct spi_device *spi)
return dev_err_probe(dev, ret,
"failed to setup minimum I/O mode\n");
+ ret = devm_iio_triggered_buffer_setup(dev, indio_dev,
+ iio_pollfunc_store_time,
+ ad4134_trigger_handler,
+ NULL);
+ if (ret)
+ return ret;
+
/* Bump precision to 24-bit */
ret = regmap_update_bits(st->regmap, AD4134_DATA_PACKET_CONFIG_REG,
AD4134_DATA_PACKET_CONFIG_FRAME_MASK,
--
2.53.0
^ permalink raw reply [flat|nested] 14+ messages in thread* [PATCH v4 08/13] dt-bindings: iio: adc: adi,ad4134: Document SPI connection mode
2026-10-06 18:15 [PATCH v4 00/13] iio: adc: ad4134: Enable greater sample rate data capture Marcelo Schmitt
` (6 preceding siblings ...)
2026-10-06 18:17 ` [PATCH v4 07/13] iio: adc: ad4134: Support buffered data read Marcelo Schmitt
@ 2026-10-06 18:18 ` Marcelo Schmitt
2026-10-06 18:18 ` [PATCH v4 09/13] dt-bindings: iio: adc: adi,ad4134: Document external multiplexer usage Marcelo Schmitt
` (4 subsequent siblings)
12 siblings, 0 replies; 14+ messages in thread
From: Marcelo Schmitt @ 2026-10-06 18:18 UTC (permalink / raw)
To: linux-iio, devicetree, linux-kernel, linux
Cc: jic23, nuno.sa, dlechner, andy, Michael.Hennerich, robh, krzk+dt,
conor+dt, corbet, skhan, marcelo.schmitt1
Document how AD4134 chips are connected to the host SPI controller
according to different wiring configurations.
Signed-off-by: Marcelo Schmitt <marcelo.schmitt@analog.com>
---
Change log v3 -> v4:
- Properly specified vendor custom property, avoiding 'too few spaces after comma' warn.
- Correctly restrained the value/number of spi-rx-bus-width lanes for
two-channel-chain use case.
- Improved the constraint to also prevent specifying one-channel-chain or
two-channel-chain without #daisy-chained-devices.
.../bindings/iio/adc/adi,ad4134.yaml | 57 ++++++++++++++++---
1 file changed, 50 insertions(+), 7 deletions(-)
diff --git a/Documentation/devicetree/bindings/iio/adc/adi,ad4134.yaml b/Documentation/devicetree/bindings/iio/adc/adi,ad4134.yaml
index ea6d7e026419..970e7adb2405 100644
--- a/Documentation/devicetree/bindings/iio/adc/adi,ad4134.yaml
+++ b/Documentation/devicetree/bindings/iio/adc/adi,ad4134.yaml
@@ -131,6 +131,26 @@ properties:
enum: [ free-running, gated ]
default: gated
+ adi,spi-mode:
+ $ref: /schemas/types.yaml#/definitions/string
+ enum: [ no-cs, 4-wire, one-channel-chain, two-channel-chain ]
+ default: no-cs
+ description: |
+ This property indicates the SPI wiring configuration.
+ * no-cs: The datasheet calls this "minimum I/O mode". In this mode, the CS
+ line is not used (tied to GND).
+ * 4-wire: Specifies a conventional SPI wiring configuration.
+ * one-channel-chain: In this mode, the DOUT0 line of one chip is connected
+ to DOUT2 of the next chip upstream in the chain. Only the data interface
+ of the upmost device in the stream is in direct connection with the
+ digital host.
+ * two-channel-chain: In this mode, the DOUT0 and DOUT1 lines of one chip
+ are respectively connected to DOUT2 and DOUT3 of the next chip upstream
+ in the chain. Only the data interface of the upmost device in the stream
+ is in direct connection with the digital host.
+
+ '#daisy-chained-devices': true
+
required:
- compatible
- reg
@@ -141,13 +161,36 @@ required:
- clocks
- clock-names
-oneOf:
- - required:
- - ldoin-supply
- - required:
- - avdd1v8-supply
- - dvdd1v8-supply
- - clkvdd-supply
+allOf:
+ - oneOf:
+ - required:
+ - ldoin-supply
+ - required:
+ - avdd1v8-supply
+ - dvdd1v8-supply
+ - clkvdd-supply
+
+ - oneOf:
+ - required: ['adi,spi-mode', '#daisy-chained-devices']
+ properties:
+ adi,spi-mode:
+ const: one-channel-chain
+ spi-rx-bus-width:
+ const: 1
+ - required: ['adi,spi-mode', '#daisy-chained-devices']
+ properties:
+ adi,spi-mode:
+ const: two-channel-chain
+ spi-rx-bus-width:
+ items:
+ - const: 1
+ - const: 1
+ - properties:
+ '#daisy-chained-devices': false
+ adi,spi-mode:
+ enum:
+ - no-cs
+ - 4-wire
unevaluatedProperties: false
--
2.53.0
^ permalink raw reply [flat|nested] 14+ messages in thread* [PATCH v4 09/13] dt-bindings: iio: adc: adi,ad4134: Document external multiplexer usage
2026-10-06 18:15 [PATCH v4 00/13] iio: adc: ad4134: Enable greater sample rate data capture Marcelo Schmitt
` (7 preceding siblings ...)
2026-10-06 18:18 ` [PATCH v4 08/13] dt-bindings: iio: adc: adi,ad4134: Document SPI connection mode Marcelo Schmitt
@ 2026-10-06 18:18 ` Marcelo Schmitt
2026-10-06 18:19 ` [PATCH v4 10/13] iio: adc: ad4134: Support SPI 4-wire mode Marcelo Schmitt
` (3 subsequent siblings)
12 siblings, 0 replies; 14+ messages in thread
From: Marcelo Schmitt @ 2026-10-06 18:18 UTC (permalink / raw)
To: linux-iio, devicetree, linux-kernel, linux
Cc: jic23, nuno.sa, dlechner, andy, Michael.Hennerich, robh, krzk+dt,
conor+dt, corbet, skhan, marcelo.schmitt1
The AD4134 design has two data interfaces. One interface allows register
access for device configuration while the other (separate interface)
provides ADC sample data. One way of handling both peripheral interfaces is
to merge them into a single SPI interface by switching between register
access and sample access according to device user requests. Though, such
solution requires extra hardware, external to the ADC chip. The access mode
switch can be done with an external multiplexer selecting either AD4134 SDO
or AD4134 DOUT0 to connect to the controller. The external multiplexer
becomes part of hardware requested for AD4134 device operation and thus
must be provided for operating the peripheral in such merged interface
schema. Still, there are alternative ways of handling the two AD4134 data
interfaces so the multiplexer is not always required.
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Marcelo Schmitt <marcelo.schmitt@analog.com>
---
No changes in v4.
Detailed reasoning for the external multiplexer usage.
Before coming to the current solution, the following configuration was tried.
+-----------------------+ +-----------------+
| AD4134 | | SPI Controller |
| | | |
| SPI interface SCLK |<--------------------------| SCLK |
| for register CS |<--------------------------| CS |
| access SDI |<--------------------------| SDO |
| SDO |---+ | |
| | | | |
| Data interface DOUT0 |---+---------------------->| SDI0 |
| for ADC sample DOUT1 |-------------------------->| SDI1 |
| data read DOUT2 |-------------------------->| SDI2 |
| DOUT3 |-------------------------->| SDI3 |
| DCLK |<--------------------------| DCLK
| ODR |<------------------+ +->| Offload Trigger |
+-----------------------+ | | +-----------------+
| +--| PWM1 |
+-------| PWM0 |
+-----------------+
Though, because DOUT0 never goes high-Z, the DOUT0 pin keeps driving the data
line, causing register reads to fail.
Alternatively, we could have something like
+-----------------------+ +-----------------+
| AD4134 | | SPI Controller |
| | | |
| SPI interface SCLK |<--------------------------| SCLK |
| for register CS |<--------------------------| CS |
| access SDI |<--------------------------| SDO |
| SDO |-------------------------->| SDI0 |
| | | |
| Data interface DOUT0 |-------------------------->| SDI1 |
| for ADC sample DOUT1 |-------------------------->| SDI2 |
| data read DOUT2 |-------------------------->| SDI3 |
| DOUT3 |-------------------------->| SDI4 |
| DCLK |<--------------------------| DCLK
| ODR |<------------------+ +->| Offload Trigger |
+-----------------------+ | | +-----------------+
| +--| PWM1 |
+-------| PWM0 |
+-----------------+
The downside of the above is the peripheral would need fine-grained config of
controller SDI lines to only read SDI0 for register access, and only read SDI1,
SDI2, SDI3, SDI4 for ADC sample data (currently available
SPI_MULTI_LANE_MODE_STRIPE reads from all SDI lines).
The currently proposed solution looks like the following
+-----------------------+ +-----------------+
| AD4134 | | SPI Controller |
| | | |
| SPI interface SCLK |<------------------------| SCLK |
| for register CS |<------------------------| CS |
| access SDI |<------------------------| SDO |
| SDO |------->|¯¯¯¯\ | |
| | |MUX >--------->| SDI0 |
| Data interface DOUT0 |------->|____/ | |
| for ADC sample | ^ | |
| data read DOUT1 |------------------------>| SDI1 |
| DOUT2 |------------------------>| SDI2 |
| DOUT3 |------------------------>| SDI3 |
| DCLK |<------------------------| DCLK |
| ODR |<----------------+ +->| Offload Trigger |
+-----------------------+ | | | +-----------------+
| | +--| PWM1 |
| +-------| PWM0 |
+--------------| GPIO |
+-----------------+
By being able to mux between AD4134 SDO and AD4134 DOUT0, the peripheral can be
connected to a single bus such that controllers able to read from multiple lines
will be able to gather ADC sample data from all SDI lines (SPI_MULTI_LANE_MODE_STRIPE).
With that, AD4134 maximum data throughput can be supported with what is already
available from the SPI core. See additional details on the AD4134 IIO
documentation (patch 15).
Yet another possibility would be to have the peripheral sitting in two buses.
+-----------------------+ +-----------------+
| AD4134 | | SPI Controller A|
| | | |
| SPI interface SCLK |<--------------------------| SCLK |
| for register CS |<--------------------------| CS |
| access SDI |<--------------------------| SDO |
| SDO |-------------------------->| SDI |
| | +-----------------+
| | | SPI Controller B|
| | | |
| Data interface DOUT0 |-------------------------->| SDI0 |
| for ADC sample DOUT1 |-------------------------->| SDI1 |
| data read DOUT2 |-------------------------->| SDI2 |
| DOUT3 |-------------------------->| SDI3 |
| DCLK |<--------------------------| DCLK |
| ODR |<------------------+ +->| Offload Trigger |
+-----------------------+ | | +-----------------+
| +--| PWM1 |
+-------| PWM0 |
+-----------------+
That may be a fallback option if what's currently being proposed fails to comply
to Linux code standards.
.../bindings/iio/adc/adi,ad4134.yaml | 47 +++++++++++++++++++
1 file changed, 47 insertions(+)
diff --git a/Documentation/devicetree/bindings/iio/adc/adi,ad4134.yaml b/Documentation/devicetree/bindings/iio/adc/adi,ad4134.yaml
index 970e7adb2405..c70b9113cd67 100644
--- a/Documentation/devicetree/bindings/iio/adc/adi,ad4134.yaml
+++ b/Documentation/devicetree/bindings/iio/adc/adi,ad4134.yaml
@@ -104,6 +104,20 @@ properties:
GPIO connected to ODR pin. Used to sample ADC data in minimum I/O mode.
maxItems: 1
+ mux-states:
+ description:
+ mux controller node to route SDO and DOUT0 signals from peripheral to
+ controller.
+ maxItems: 2
+
+ mux-state-names:
+ description:
+ mux state names for routing SDO and DOUT0 signals from peripheral to
+ controller.
+ items:
+ - const: data_read
+ - const: reg_access
+
adi,asrc-mode:
$ref: /schemas/types.yaml#/definitions/string
description:
@@ -231,4 +245,37 @@ examples:
};
};
+ - |
+ #include <dt-bindings/gpio/gpio.h>
+
+ spi {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ adc@0 {
+ compatible = "adi,ad4134";
+ reg = <0>;
+
+ spi-max-frequency = <1000000>;
+
+ reset-gpios = <&gpio0 86 GPIO_ACTIVE_LOW>;
+ powerdown-gpios = <&gpio0 88 GPIO_ACTIVE_LOW>;
+
+ clocks = <&sys_clk>;
+ clock-names = "clkin";
+
+ avdd5-supply = <&avdd5>;
+ dvdd5-supply = <&dvdd5>;
+ iovdd-supply = <&iovdd>;
+ refin-supply = <&refin>;
+ avdd1v8-supply = <&avdd1v8>;
+ dvdd1v8-supply = <&dvdd1v8>;
+ clkvdd-supply = <&clkvdd>;
+
+ mux-states = <&ad4134_sdo_dout0_mux 0>, <&ad4134_sdo_dout0_mux 1>;
+ mux-state-names = "data_read", "reg_access";
+
+ adi,spi-mode = "4-wire";
+ };
+ };
...
--
2.53.0
^ permalink raw reply [flat|nested] 14+ messages in thread* [PATCH v4 10/13] iio: adc: ad4134: Support SPI 4-wire mode
2026-10-06 18:15 [PATCH v4 00/13] iio: adc: ad4134: Enable greater sample rate data capture Marcelo Schmitt
` (8 preceding siblings ...)
2026-10-06 18:18 ` [PATCH v4 09/13] dt-bindings: iio: adc: adi,ad4134: Document external multiplexer usage Marcelo Schmitt
@ 2026-10-06 18:19 ` Marcelo Schmitt
2026-10-06 18:19 ` [PATCH v4 11/13] dt-bindings: iio: adc: adi,ad4134: Document PWM usage Marcelo Schmitt
` (2 subsequent siblings)
12 siblings, 0 replies; 14+ messages in thread
From: Marcelo Schmitt @ 2026-10-06 18:19 UTC (permalink / raw)
To: linux-iio, devicetree, linux-kernel, linux
Cc: jic23, nuno.sa, dlechner, andy, Michael.Hennerich, robh, krzk+dt,
conor+dt, corbet, skhan, marcelo.schmitt1
AD4134 devices can be wired in a few different ways. So far, only minimum
I/O mode was supported. While minimum I/O mode allows interfacing with
AD4134 with a reduced number of wires, that wiring configuration is not
suitable for high-throughput data acquisition.
Extend AD4134 support to enable interfacing in SPI 4-wire configuration.
Signed-off-by: Marcelo Schmitt <marcelo.schmitt@analog.com>
---
Change log v3 -> v4:
- Also request ODR GPIO for 4-wire mode when offload is not available.
- Dropped second driver state mutex (access_lock). Triggered buffer handler is
already protected by IIO device mode lock.
Detailed reasoning for the external multiplexer usage.
Before coming to the current solution, the following configuration was tried.
+-----------------------+ +-----------------+
| AD4134 | | SPI Controller |
| | | |
| SPI interface SCLK |<--------------------------| SCLK |
| for register CS |<--------------------------| CS |
| access SDI |<--------------------------| SDO |
| SDO |---+ | |
| | | | |
| Data interface DOUT0 |---+---------------------->| SDI0 |
| for ADC sample DOUT1 |-------------------------->| SDI1 |
| data read DOUT2 |-------------------------->| SDI2 |
| DOUT3 |-------------------------->| SDI3 |
| DCLK |<--------------------------| DCLK
| ODR |<------------------+ +->| Offload Trigger |
+-----------------------+ | | +-----------------+
| +--| PWM1 |
+-------| PWM0 |
+-----------------+
Though, because DOUT0 never goes high-Z, the DOUT0 pin keeps driving the data
line, causing register reads to fail.
Alternatively, we could have something like
+-----------------------+ +-----------------+
| AD4134 | | SPI Controller |
| | | |
| SPI interface SCLK |<--------------------------| SCLK |
| for register CS |<--------------------------| CS |
| access SDI |<--------------------------| SDO |
| SDO |-------------------------->| SDI0 |
| | | |
| Data interface DOUT0 |-------------------------->| SDI1 |
| for ADC sample DOUT1 |-------------------------->| SDI2 |
| data read DOUT2 |-------------------------->| SDI3 |
| DOUT3 |-------------------------->| SDI4 |
| DCLK |<--------------------------| DCLK
| ODR |<------------------+ +->| Offload Trigger |
+-----------------------+ | | +-----------------+
| +--| PWM1 |
+-------| PWM0 |
+-----------------+
The downside of the above is the peripheral would need fine-grained config of
controller SDI lines to only read SDI0 for register access, and only read SDI1,
SDI2, SDI3, SDI4 for ADC sample data (currently available
SPI_MULTI_LANE_MODE_STRIPE reads from all SDI lines).
The currently proposed solution looks like the following
+-----------------------+ +-----------------+
| AD4134 | | SPI Controller |
| | | |
| SPI interface SCLK |<------------------------| SCLK |
| for register CS |<------------------------| CS |
| access SDI |<------------------------| SDO |
| SDO |------->|¯¯¯¯\ | |
| | |MUX >--------->| SDI0 |
| Data interface DOUT0 |------->|____/ | |
| for ADC sample | ^ | |
| data read DOUT1 |------------------------>| SDI1 |
| DOUT2 |------------------------>| SDI2 |
| DOUT3 |------------------------>| SDI3 |
| DCLK |<------------------------| DCLK |
| ODR |<----------------+ +->| Offload Trigger |
+-----------------------+ | | | +-----------------+
| | +--| PWM1 |
| +-------| PWM0 |
+--------------| GPIO |
+-----------------+
By being able to mux between AD4134 SDO and AD4134 DOUT0, the peripheral can be
connected to a single bus such that controllers able to read from multiple lines
will be able to gather ADC sample data from all SDI lines (SPI_MULTI_LANE_MODE_STRIPE).
With that, AD4134 maximum data throughput can be supported with what is already
available from the SPI core. See additional details on the AD4134 IIO
documentation (patch 15).
Yet another possibility would be to have the peripheral sitting in two buses.
+-----------------------+ +-----------------+
| AD4134 | | SPI Controller A|
| | | |
| SPI interface SCLK |<--------------------------| SCLK |
| for register CS |<--------------------------| CS |
| access SDI |<--------------------------| SDO |
| SDO |-------------------------->| SDI |
| | +-----------------+
| | | SPI Controller B|
| | | |
| Data interface DOUT0 |-------------------------->| SDI0 |
| for ADC sample DOUT1 |-------------------------->| SDI1 |
| data read DOUT2 |-------------------------->| SDI2 |
| DOUT3 |-------------------------->| SDI3 |
| DCLK |<--------------------------| DCLK |
| ODR |<------------------+ +->| Offload Trigger |
+-----------------------+ | | +-----------------+
| +--| PWM1 |
+-------| PWM0 |
+-----------------+
That may be a fallback option if what's currently being proposed fails to comply
to Linux code standards.
drivers/iio/adc/Kconfig | 1 +
drivers/iio/adc/ad4134.c | 222 ++++++++++++++++++++++++++++++++++++---
2 files changed, 206 insertions(+), 17 deletions(-)
diff --git a/drivers/iio/adc/Kconfig b/drivers/iio/adc/Kconfig
index fc7de0bb400a..21bb16f66bc9 100644
--- a/drivers/iio/adc/Kconfig
+++ b/drivers/iio/adc/Kconfig
@@ -127,6 +127,7 @@ config AD4134
select CRC8
select IIO_BUFFER
select IIO_TRIGGERED_BUFFER
+ select MULTIPLEXER
help
Say yes here to build support for Analog Devices AD4134 SPI analog to
digital converters (ADC).
diff --git a/drivers/iio/adc/ad4134.c b/drivers/iio/adc/ad4134.c
index b5207f16054e..debc2ff02705 100644
--- a/drivers/iio/adc/ad4134.c
+++ b/drivers/iio/adc/ad4134.c
@@ -17,6 +17,8 @@
#include <linux/gpio/consumer.h>
#include <linux/module.h>
#include <linux/mutex.h>
+#include <linux/mux/consumer.h>
+#include <linux/property.h>
#include <linux/regmap.h>
#include <linux/regulator/consumer.h>
#include <linux/reset.h>
@@ -72,6 +74,9 @@
#define AD4134_CH3_OFFSET_MSB_REG 0x3E
#define AD4134_AIN_OR_ERROR_REG 0x48
+#define AD4134_SDO_INPUT 0
+#define AD4134_DOUT0_INPUT 1
+
/*
* AD4134 register map ends at address 0x48 and there is no register for
* retrieving ADC sample data. Though, to make use of Linux regmap API both
@@ -86,6 +91,17 @@
#define AD4134_SPI_CRC_INIT_VALUE 0xA5
static unsigned char ad4134_spi_crc_table[CRC8_TABLE_SIZE];
+enum ad4134_spi_mode {
+ AD4134_SPI_MODE_NO_CS, /* datasheet calls this "minimum I/O mode" */
+ AD4134_SPI_MODE_4_WIRE,
+};
+
+/* maps adi,spi-mode property value to enum */
+static const char * const ad4134_spi_modes[] = {
+ [AD4134_SPI_MODE_NO_CS] = "no-cs",
+ [AD4134_SPI_MODE_4_WIRE] = "4-wire",
+};
+
enum ad4134_filter_type {
AD4134_WIDEBAND,
AD4134_SINC6,
@@ -154,6 +170,8 @@ struct ad4134_state {
* consecutive register access operations.
*/
struct mutex sync_lock;
+ struct mux_state *mux_st[2]; /* For external multiplexer control */
+ enum ad4134_spi_mode spi_mode;
int refin_mv;
bool crc_en;
/*
@@ -226,6 +244,85 @@ static const struct regmap_access_table ad4134_regmap_wr_table = {
.n_yes_ranges = ARRAY_SIZE(ad4134_regmap_wr_range),
};
+/*
+ * When operating in modes other than minimum I/O mode, AD4134 register data on
+ * the SDO line is sampled on SCLK rising edge (SPI mode 0). In addition to
+ * that, when AD4134 SDO and DOUT0 pins are multiplexed by hardware OUTSIDE
+ * AD4134 SILICON, the multiplexer state must be set to route SDO to the SPI
+ * controller. With both SPI mode and multiplexer state properly set, register
+ * access runs as usual. Successful calls to this function must be balanced with
+ * calls to ad4134_release_reg_access() so to release the mux state lock. See
+ * AD4134 IIO documentation for details.
+ */
+static int ad4134_claim_reg_access(struct ad4134_state *st)
+{
+ unsigned int cur_mode = st->spi->mode & SPI_MODE_X_MASK;
+ int ret;
+
+ if (st->spi_mode != AD4134_SPI_MODE_NO_CS && cur_mode != SPI_MODE_0) {
+ st->spi->mode &= ~SPI_MODE_X_MASK;
+ st->spi->mode |= SPI_MODE_0;
+ ret = spi_setup(st->spi);
+ if (ret)
+ return ret;
+ }
+
+ if (st->mux_st[AD4134_SDO_INPUT])
+ return mux_state_select(st->mux_st[AD4134_SDO_INPUT]);
+
+ return 0;
+}
+
+/*
+ * Must be balanced with successful calls to ad4134_claim_reg_access().
+ */
+static int ad4134_release_reg_access(struct ad4134_state *st)
+{
+ if (st->mux_st[AD4134_SDO_INPUT])
+ return mux_state_deselect(st->mux_st[AD4134_SDO_INPUT]);
+
+ return 0;
+}
+
+/*
+ * When operating in modes other than minimum I/O mode, AD4134 ADC sample data
+ * on the DOUT lines is sampled on SCLK falling edge (SPI mode 1). In addition
+ * to that, when AD4134 SDO and DOUT0 pins are multiplexed by hardware OUTSIDE
+ * AD4134 SILICON, the multiplexer state must be set to route DOUT0 to the SPI
+ * controller. With both SPI mode and multiplexer state properly set, ADC
+ * samples can be read normally. Successful call to this function must be paired
+ * with a call to ad4134_release_sample_access().
+ */
+static int ad4134_claim_sample_access(struct ad4134_state *st)
+{
+ unsigned int cur_mode = st->spi->mode & SPI_MODE_X_MASK;
+ int ret;
+
+ if (st->spi_mode != AD4134_SPI_MODE_NO_CS && cur_mode != SPI_MODE_1) {
+ st->spi->mode &= ~SPI_MODE_X_MASK;
+ st->spi->mode |= SPI_MODE_1;
+ ret = spi_setup(st->spi);
+ if (ret)
+ return ret;
+ }
+
+ if (st->mux_st[AD4134_DOUT0_INPUT])
+ return mux_state_select(st->mux_st[AD4134_DOUT0_INPUT]);
+
+ return 0;
+}
+
+/*
+ * Must be balanced with successful calls to ad4134_claim_sample_access().
+ */
+static int ad4134_release_sample_access(struct ad4134_state *st)
+{
+ if (st->mux_st[AD4134_DOUT0_INPUT])
+ return mux_state_deselect(st->mux_st[AD4134_DOUT0_INPUT]);
+
+ return 0;
+}
+
static int ad4134_calc_spi_crc(u8 inst, u8 data)
{
u8 buf[] = { inst, data };
@@ -249,18 +346,27 @@ static int ad4134_reg_write(void *context, unsigned int reg, unsigned int val)
.rx_buf = st->rx_buf,
.len = st->crc_en ? AD4134_SPI_MAX_XFER_LEN : 2,
};
- int ret;
+ int access_ret, ret;
+
+ ret = ad4134_claim_reg_access(st);
+ if (ret)
+ return ret;
ad4134_prepare_spi_tx_buf(reg, val, st->tx_buf);
ret = spi_sync_transfer(st->spi, &xfer, 1);
if (ret)
- return ret;
+ goto out_write_release;
if (st->crc_en && st->rx_buf[2] != st->tx_buf[2])
dev_dbg(&st->spi->dev, "reg write CRC check failed\n");
- return 0;
+out_write_release:
+ access_ret = ad4134_release_reg_access(st);
+ if (access_ret)
+ dev_err(&st->spi->dev, "error on access release: %d\n", access_ret);
+
+ return ret;
}
static int ad4134_data_read(struct ad4134_state *st, unsigned int reg,
@@ -268,7 +374,11 @@ static int ad4134_data_read(struct ad4134_state *st, unsigned int reg,
{
unsigned int i;
u32 sample;
- int ret;
+ int access_ret, ret;
+
+ ret = ad4134_claim_sample_access(st);
+ if (ret)
+ return ret;
/*
* To be able to read data from all 4 channels through a single line, we
@@ -284,7 +394,7 @@ static int ad4134_data_read(struct ad4134_state *st, unsigned int reg,
ret = spi_write_then_read(st->spi, NULL, 0, st->rx_buf,
BITS_TO_BYTES(AD4134_CHAN_PRECISION_BITS));
if (ret)
- return ret;
+ goto out_data_read_release;
/*
* AD4134 has a built-in feature that flags when data transfers
@@ -296,7 +406,12 @@ static int ad4134_data_read(struct ad4134_state *st, unsigned int reg,
}
*val = sign_extend32(sample, AD4134_CHAN_PRECISION_BITS - 1);
- return 0;
+out_data_read_release:
+ access_ret = ad4134_release_sample_access(st);
+ if (access_ret)
+ dev_err(&st->spi->dev, "error on access release: %d\n", access_ret);
+
+ return ret;
}
static int ad4134_register_read(struct ad4134_state *st, unsigned int reg,
@@ -308,14 +423,18 @@ static int ad4134_register_read(struct ad4134_state *st, unsigned int reg,
.len = st->crc_en ? AD4134_SPI_MAX_XFER_LEN : 2,
};
unsigned int inst;
- int ret;
+ int access_ret, ret;
+
+ ret = ad4134_claim_reg_access(st);
+ if (ret)
+ return ret;
inst = AD4134_REG_READ_MASK | reg;
ad4134_prepare_spi_tx_buf(inst, 0, st->tx_buf);
ret = spi_sync_transfer(st->spi, &xfer, 1);
if (ret)
- return ret;
+ goto out_read_release;
*val = st->rx_buf[1];
@@ -323,7 +442,12 @@ static int ad4134_register_read(struct ad4134_state *st, unsigned int reg,
if (st->crc_en && st->rx_buf[2] != st->tx_buf[2])
dev_dbg(&st->spi->dev, "reg read CRC check failed\n");
- return 0;
+out_read_release:
+ access_ret = ad4134_release_reg_access(st);
+ if (access_ret)
+ dev_err(&st->spi->dev, "error on access release: %d\n", access_ret);
+
+ return ret;
}
static int ad4134_reg_read(void *context, unsigned int reg, unsigned int *val)
@@ -382,6 +506,21 @@ static irqreturn_t ad4134_trigger_handler(int irq, void *p)
return IRQ_HANDLED;
}
+static int ad4134_buffer_postenable(struct iio_dev *indio_dev)
+{
+ return ad4134_claim_sample_access(iio_priv(indio_dev));
+}
+
+static int ad4134_buffer_predisable(struct iio_dev *indio_dev)
+{
+ return ad4134_release_sample_access(iio_priv(indio_dev));
+}
+
+static const struct iio_buffer_setup_ops ad4134_buffer_setup_ops = {
+ .postenable = &ad4134_buffer_postenable,
+ .predisable = &ad4134_buffer_predisable,
+};
+
static int ad4134_read_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan,
int *val, int *val2, long info)
@@ -444,11 +583,6 @@ static int ad4134_min_io_mode_setup(struct ad4134_state *st)
int ret;
st->crc_en = true; /* In minimum I/O mode CRC cannot be disabled */
- st->odr_gpio = devm_gpiod_get(dev, "odr", GPIOD_OUT_LOW);
- if (IS_ERR(st->odr_gpio))
- return dev_err_probe(dev, PTR_ERR(st->odr_gpio),
- "failed to get ODR GPIO\n");
-
ret = regmap_update_bits(st->regmap, AD4134_DIG_IF_CFG_REG,
AD4134_DIF_IF_CFG_FORMAT_MASK,
FIELD_PREP(AD4134_DIF_IF_CFG_FORMAT_MASK,
@@ -594,10 +728,64 @@ static int ad4134_probe(struct spi_device *spi)
return dev_err_probe(dev, PTR_ERR(st->regmap),
"failed to initialize regmap");
- ret = ad4134_min_io_mode_setup(st);
- if (ret)
+ ret = device_property_match_property_string(dev, "adi,spi-mode",
+ ad4134_spi_modes,
+ ARRAY_SIZE(ad4134_spi_modes));
+ if (ret == -EINVAL) {
+ /* Default to no-cs mode if adi,spi-mode is not specified */
+ if (!device_property_present(dev, "adi,spi-mode"))
+ st->spi_mode = AD4134_SPI_MODE_NO_CS;
+ else
+ return dev_err_probe(dev, ret,
+ "unsupported adi,spi-mode\n");
+ } else if (ret < 0) {
return dev_err_probe(dev, ret,
- "failed to setup minimum I/O mode\n");
+ "getting adi,spi-mode property failed\n");
+ } else {
+ st->spi_mode = ret;
+ }
+
+ if (st->spi_mode == AD4134_SPI_MODE_NO_CS) {
+ /*
+ * The support hardware for AD4134 may have a multiplexer for
+ * selecting between AD4134 SDO and AD4134 DOUT0. If that mux
+ * is set but the user still wants to run AD4134 in minimum I/O
+ * mode, then DOUT0 is not used and the multiplexer OUTSIDE OF
+ * AD4134 SILICON must be set to select AD4134 SDO. See AD4134
+ * IIO documentation for details.
+ */
+ st->mux_st[AD4134_SDO_INPUT] =
+ devm_mux_state_get_optional_selected(dev, "reg_access");
+ if (IS_ERR(st->mux_st[AD4134_SDO_INPUT]))
+ return dev_err_probe(dev, PTR_ERR(st->mux_st[AD4134_SDO_INPUT]),
+ "failed to get reg_access mux-state\n");
+
+ ret = ad4134_min_io_mode_setup(st);
+ if (ret)
+ return dev_err_probe(dev, ret,
+ "failed to setup minimum I/O mode\n");
+ } else {
+ /*
+ * This controls a multiplexer OUTSIDE OF AD4134 SILICON.
+ * See AD4134 IIO documentation for details.
+ */
+ st->mux_st[AD4134_SDO_INPUT] = devm_mux_state_get(dev, "reg_access");
+ if (IS_ERR(st->mux_st[AD4134_SDO_INPUT]))
+ return dev_err_probe(dev, PTR_ERR(st->mux_st[AD4134_SDO_INPUT]),
+ "failed to get reg_access mux-state\n");
+
+ st->mux_st[AD4134_DOUT0_INPUT] = devm_mux_state_get(dev, "data_read");
+ if (IS_ERR(st->mux_st[AD4134_DOUT0_INPUT]))
+ return dev_err_probe(dev, PTR_ERR(st->mux_st[AD4134_DOUT0_INPUT]),
+ "failed to get data_read mux-state\n");
+
+ indio_dev->setup_ops = &ad4134_buffer_setup_ops;
+ }
+
+ st->odr_gpio = devm_gpiod_get(dev, "odr", GPIOD_OUT_LOW);
+ if (IS_ERR(st->odr_gpio))
+ return dev_err_probe(dev, PTR_ERR(st->odr_gpio),
+ "failed to get ODR GPIO\n");
ret = devm_iio_triggered_buffer_setup(dev, indio_dev,
iio_pollfunc_store_time,
--
2.53.0
^ permalink raw reply [flat|nested] 14+ messages in thread* [PATCH v4 11/13] dt-bindings: iio: adc: adi,ad4134: Document PWM usage
2026-10-06 18:15 [PATCH v4 00/13] iio: adc: ad4134: Enable greater sample rate data capture Marcelo Schmitt
` (9 preceding siblings ...)
2026-10-06 18:19 ` [PATCH v4 10/13] iio: adc: ad4134: Support SPI 4-wire mode Marcelo Schmitt
@ 2026-10-06 18:19 ` Marcelo Schmitt
2026-10-06 18:19 ` [PATCH v4 12/13] iio: adc: ad4134: Support high-speed data capture Marcelo Schmitt
2026-10-06 18:19 ` [PATCH v4 13/13] Docs: iio: Add AD4134 Marcelo Schmitt
12 siblings, 0 replies; 14+ messages in thread
From: Marcelo Schmitt @ 2026-10-06 18:19 UTC (permalink / raw)
To: linux-iio, devicetree, linux-kernel, linux
Cc: jic23, nuno.sa, dlechner, andy, Michael.Hennerich, robh, krzk+dt,
conor+dt, corbet, skhan, marcelo.schmitt1, Conor Dooley
Advanced setups may connect a PWM signal to AD4134 ODR pin for faster
output data rates.
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Marcelo Schmitt <marcelo.schmitt@analog.com>
---
No changes in v4.
Documentation/devicetree/bindings/iio/adc/adi,ad4134.yaml | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/Documentation/devicetree/bindings/iio/adc/adi,ad4134.yaml b/Documentation/devicetree/bindings/iio/adc/adi,ad4134.yaml
index c70b9113cd67..6a190b7a9311 100644
--- a/Documentation/devicetree/bindings/iio/adc/adi,ad4134.yaml
+++ b/Documentation/devicetree/bindings/iio/adc/adi,ad4134.yaml
@@ -104,6 +104,10 @@ properties:
GPIO connected to ODR pin. Used to sample ADC data in minimum I/O mode.
maxItems: 1
+ pwms:
+ description: PWM signal connected to the ODR pin.
+ maxItems: 1
+
mux-states:
description:
mux controller node to route SDO and DOUT0 signals from peripheral to
@@ -257,9 +261,11 @@ examples:
reg = <0>;
spi-max-frequency = <1000000>;
+ spi-rx-bus-width = <1>, <1>, <1>, <1>; /* 4 lanes of 1 bit each */
reset-gpios = <&gpio0 86 GPIO_ACTIVE_LOW>;
powerdown-gpios = <&gpio0 88 GPIO_ACTIVE_LOW>;
+ pwms = <&ad4134_odr_generator 1 1000000 0>;
clocks = <&sys_clk>;
clock-names = "clkin";
--
2.53.0
^ permalink raw reply [flat|nested] 14+ messages in thread* [PATCH v4 12/13] iio: adc: ad4134: Support high-speed data capture
2026-10-06 18:15 [PATCH v4 00/13] iio: adc: ad4134: Enable greater sample rate data capture Marcelo Schmitt
` (10 preceding siblings ...)
2026-10-06 18:19 ` [PATCH v4 11/13] dt-bindings: iio: adc: adi,ad4134: Document PWM usage Marcelo Schmitt
@ 2026-10-06 18:19 ` Marcelo Schmitt
2026-10-06 18:19 ` [PATCH v4 13/13] Docs: iio: Add AD4134 Marcelo Schmitt
12 siblings, 0 replies; 14+ messages in thread
From: Marcelo Schmitt @ 2026-10-06 18:19 UTC (permalink / raw)
To: linux-iio, devicetree, linux-kernel, linux
Cc: jic23, nuno.sa, dlechner, andy, Michael.Hennerich, robh, krzk+dt,
conor+dt, corbet, skhan, marcelo.schmitt1
Make use of SPI transfer offloading to speed up data capture, enabling data
acquisition at faster sample rates (up to 1.496 MSPS).
Signed-off-by: Marcelo Schmitt <marcelo.schmitt@analog.com>
---
Change log v3 -> v4:
- Adjusted PWM approximation loop counter decrement.
- No longer providing IIO channel separate INFO_RAW on offload setup.
- Adjusted in_range() check to not error on maximum sample rate.
drivers/iio/adc/Kconfig | 5 +
drivers/iio/adc/ad4134.c | 391 +++++++++++++++++++++++++++++++++++++--
2 files changed, 383 insertions(+), 13 deletions(-)
diff --git a/drivers/iio/adc/Kconfig b/drivers/iio/adc/Kconfig
index 21bb16f66bc9..c5b321b5f4d8 100644
--- a/drivers/iio/adc/Kconfig
+++ b/drivers/iio/adc/Kconfig
@@ -123,9 +123,14 @@ config AD4130
config AD4134
tristate "Analog Devices AD4134 ADC Driver"
depends on SPI
+ depends on PWM
select REGMAP_SPI
+ select SPI_OFFLOAD
+ select SPI_OFFLOAD_TRIGGER_PWM
select CRC8
select IIO_BUFFER
+ select IIO_BUFFER_DMA
+ select IIO_BUFFER_DMAENGINE
select IIO_TRIGGERED_BUFFER
select MULTIPLEXER
help
diff --git a/drivers/iio/adc/ad4134.c b/drivers/iio/adc/ad4134.c
index debc2ff02705..aa8abe5715c4 100644
--- a/drivers/iio/adc/ad4134.c
+++ b/drivers/iio/adc/ad4134.c
@@ -12,6 +12,7 @@
#include <linux/crc8.h>
#include <linux/delay.h>
#include <linux/dev_printk.h>
+#include <linux/dmaengine.h>
#include <linux/err.h>
#include <linux/export.h>
#include <linux/gpio/consumer.h>
@@ -19,9 +20,12 @@
#include <linux/mutex.h>
#include <linux/mux/consumer.h>
#include <linux/property.h>
+#include <linux/pwm.h>
#include <linux/regmap.h>
#include <linux/regulator/consumer.h>
#include <linux/reset.h>
+#include <linux/spi/offload/consumer.h>
+#include <linux/spi/offload/types.h>
#include <linux/spi/spi.h>
#include <linux/time64.h>
#include <linux/types.h>
@@ -29,11 +33,16 @@
#include <linux/units.h>
#include <linux/iio/buffer.h>
+#include <linux/iio/buffer-dma.h>
+#include <linux/iio/buffer-dmaengine.h>
#include <linux/iio/iio.h>
#include <linux/iio/triggered_buffer.h>
#include <linux/iio/trigger_consumer.h>
#define AD4134_RESET_TIME_US (10 * USEC_PER_SEC)
+#define AD4134_DCLK_RISING_OFFSET_NS 8
+#define AD4134_MIN_ODR_FREQ_HZ 10
+#define AD4134_MAX_ODR_FREQ_HZ (1496 * HZ_PER_KHZ)
#define AD4134_REG_READ_MASK BIT(7)
#define AD4134_SPI_MAX_XFER_LEN 3
@@ -64,6 +73,7 @@
#define AD4134_DIG_IF_CFG_REG 0x12
#define AD4134_DIF_IF_CFG_FORMAT_MASK GENMASK(1, 0)
#define AD4134_DATA_FORMAT_SINGLE_CH_MODE 0x0
+#define AD4134_DATA_FORMAT_QUAD_CH_PARALLEL 0x2
#define AD4134_PW_DOWN_CTRL_REG 0x13
#define AD4134_DEVICE_STATUS_REG 0x15
@@ -116,6 +126,10 @@ static const char * const ad4134_filt_names[] = {
[AD4134_SINC3_REJ60] = "sinc3+rej60",
};
+static const int ad4134_max_samp_freq_range_Hz[3] = {
+ AD4134_MIN_ODR_FREQ_HZ, 1, AD4134_MAX_ODR_FREQ_HZ,
+};
+
static int ad4134_get_filter_type(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan);
@@ -160,6 +174,38 @@ static const struct iio_chan_spec ad4134_chan_set[] = {
IIO_CHAN_SOFT_TIMESTAMP(4),
};
+/*
+ * Hardcoded 32-bit storagebits and CPU endianness because the currently
+ * available HDL only supports that configuration.
+ */
+#define AD4134_OFFLOAD_CHANNEL(_index) { \
+ .type = IIO_VOLTAGE, \
+ .indexed = 1, \
+ .channel = (_index), \
+ .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) | \
+ BIT(IIO_CHAN_INFO_SAMP_FREQ), \
+ .info_mask_shared_by_type_available = BIT(IIO_CHAN_INFO_SAMP_FREQ), \
+ .ext_info = ad4134_filter_type_ext_info, \
+ .scan_index = (_index), \
+ .scan_type = { \
+ .format = IIO_SCAN_FORMAT_SIGNED_INT, \
+ .realbits = AD4134_CHAN_PRECISION_BITS, \
+ .storagebits = 32, \
+ .endianness = IIO_CPU, \
+ }, \
+}
+
+/*
+ * It's not possible for software to record when offloaded SPI transfers run so
+ * no additional timestamp channel is added.
+ */
+static const struct iio_chan_spec ad4134_offload_chan_set[] = {
+ AD4134_OFFLOAD_CHANNEL(0),
+ AD4134_OFFLOAD_CHANNEL(1),
+ AD4134_OFFLOAD_CHANNEL(2),
+ AD4134_OFFLOAD_CHANNEL(3),
+};
+
struct ad4134_state {
struct spi_device *spi;
struct regmap *regmap;
@@ -173,6 +219,14 @@ struct ad4134_state {
struct mux_state *mux_st[2]; /* For external multiplexer control */
enum ad4134_spi_mode spi_mode;
int refin_mv;
+ struct spi_message msg;
+ struct spi_transfer xfers;
+ struct spi_offload_trigger_config offload_trigger_config;
+ struct spi_offload_trigger *offload_trigger;
+ struct spi_offload *offload;
+ struct pwm_waveform odr_wf;
+ struct pwm_device *odr_pwm;
+ unsigned int odr_hz;
bool crc_en;
/*
* DMA (thus cache coherency maintenance) requires the transfer buffers
@@ -468,6 +522,92 @@ static const struct regmap_config ad4134_regmap_config = {
.max_register = AD4134_CH_VREG(ARRAY_SIZE(ad4134_chan_set) - 1),
};
+static int ad4134_update_conversion_rate(struct ad4134_state *st,
+ unsigned int freq_Hz)
+{
+ struct spi_offload_trigger_config config = st->offload_trigger_config;
+ struct pwm_waveform odr_wf = { };
+ u64 offload_period_ns;
+ u64 offload_offset_ns;
+ u64 odr_high_time_ns;
+ unsigned int count;
+ u64 target_ns;
+ int ret;
+
+ if (!in_range(freq_Hz, AD4134_MIN_ODR_FREQ_HZ,
+ AD4134_MAX_ODR_FREQ_HZ - AD4134_MIN_ODR_FREQ_HZ + 1))
+ return -ERANGE;
+
+ odr_wf.period_length_ns = DIV_ROUND_UP_ULL(NSEC_PER_SEC, freq_Hz);
+ /*
+ * Set the PWM duty cycle to keep ODR high for at least minimum required
+ * time. If the rounded PWM's value is less than the minimum required,
+ * increase the target value by 10 and attempt to round the waveform
+ * again, until the minimum (or try count limit) is reached.
+ */
+ odr_high_time_ns = div64_ul(6ULL * NSEC_PER_SEC, st->sys_clk_hz);
+ target_ns = 0;
+ count = 100;
+ do {
+ target_ns += 10; /* Increment by PWM duty cycle period */
+ odr_wf.duty_length_ns = target_ns;
+ ret = pwm_round_waveform_might_sleep(st->odr_pwm, &odr_wf);
+ if (ret)
+ return ret;
+ } while (--count && odr_wf.duty_length_ns < odr_high_time_ns);
+
+ /* Check the minimum ODR high time is met */
+ if (odr_wf.duty_length_ns < odr_high_time_ns)
+ return -EDOM;
+
+ if (odr_wf.period_length_ns < 2 * odr_high_time_ns)
+ return -EDOM;
+
+ /*
+ * Configure SPI offload PWM trigger.
+ * For gated DCLK, the minimum required time between ODR rising edge
+ * and DCLK rising edge is the sum of ODR high time and ODR falling
+ * edge to DCLK rising edge time. Delay the offload trigger for at least
+ * that amount of time so the ADC sample data will be available when the
+ * SPI transfer begin.
+ *
+ * Use the same period as ODR PWM to avoid timing issues.
+ * Convert back from period to frequency for the SPI offload API.
+ */
+ offload_period_ns = odr_wf.period_length_ns;
+ config.periodic.frequency_hz = DIV_ROUND_UP_ULL(HZ_PER_GHZ, offload_period_ns);
+ offload_offset_ns = odr_high_time_ns + AD4134_DCLK_RISING_OFFSET_NS;
+ count = 100;
+ do {
+ config.periodic.offset_ns = offload_offset_ns;
+ ret = spi_offload_trigger_validate(st->offload_trigger, &config);
+ if (ret)
+ return ret;
+
+ offload_offset_ns += 10;
+ } while (--count && config.periodic.offset_ns < odr_high_time_ns +
+ AD4134_DCLK_RISING_OFFSET_NS);
+
+ /* Check the minimum ODR to DCLK delay is met */
+ if (config.periodic.offset_ns < odr_high_time_ns + AD4134_DCLK_RISING_OFFSET_NS)
+ return -EDOM;
+
+ /* Check the PWM periods remain the same */
+ offload_period_ns = DIV_ROUND_UP_ULL(HZ_PER_GHZ, config.periodic.frequency_hz);
+ if (odr_wf.period_length_ns != offload_period_ns)
+ return -EDOM;
+
+ ret = pwm_set_waveform_might_sleep(st->odr_pwm, &odr_wf, false);
+ if (ret)
+ return ret;
+
+ st->offload_trigger_config = config;
+ st->odr_wf = odr_wf;
+ st->odr_hz = DIV_ROUND_UP_ULL(NSEC_PER_SEC, odr_wf.period_length_ns);
+
+ return 0;
+}
+
static irqreturn_t ad4134_trigger_handler(int irq, void *p)
{
IIO_DECLARE_BUFFER_WITH_TS(u32, channels, AD4134_NUM_CHANNELS) = { };
@@ -530,6 +670,9 @@ static int ad4134_read_raw(struct iio_dev *indio_dev,
switch (info) {
case IIO_CHAN_INFO_RAW: {
+ if (!IS_ERR_OR_NULL(st->offload))
+ return -EPROTONOSUPPORT;
+
IIO_DEV_ACQUIRE_DIRECT_MODE(indio_dev, claim);
if (IIO_DEV_ACQUIRE_FAILED(claim))
return -EBUSY;
@@ -560,6 +703,44 @@ static int ad4134_read_raw(struct iio_dev *indio_dev,
*val2 = AD4134_CHAN_PRECISION_BITS - 1;
return IIO_VAL_FRACTIONAL_LOG2;
+ case IIO_CHAN_INFO_SAMP_FREQ:
+ *val = st->odr_hz;
+ return IIO_VAL_INT;
+ default:
+ return -EINVAL;
+ }
+}
+
+static int ad4134_read_avail(struct iio_dev *indio_dev,
+ struct iio_chan_spec const *chan,
+ const int **vals, int *type, int *length,
+ long info)
+{
+ switch (info) {
+ case IIO_CHAN_INFO_SAMP_FREQ:
+ *vals = (int *)ad4134_max_samp_freq_range_Hz;
+ *type = IIO_VAL_INT;
+ return IIO_AVAIL_RANGE;
+ default:
+ return -EINVAL;
+ }
+}
+
+static int ad4134_write_raw(struct iio_dev *indio_dev,
+ struct iio_chan_spec const *chan,
+ int val, int val2, long mask)
+{
+ struct ad4134_state *st = iio_priv(indio_dev);
+
+ IIO_DEV_ACQUIRE_DIRECT_MODE(indio_dev, claim);
+ if (IIO_DEV_ACQUIRE_FAILED(claim))
+ return -EBUSY;
+
+ guard(mutex)(&st->sync_lock);
+
+ switch (mask) {
+ case IIO_CHAN_INFO_SAMP_FREQ:
+ return ad4134_update_conversion_rate(st, val);
default:
return -EINVAL;
}
@@ -606,6 +787,166 @@ static const struct iio_info ad4134_info = {
.debugfs_reg_access = ad4134_debugfs_reg_access,
};
+static const struct iio_info ad4134_offload_info = {
+ .read_raw = ad4134_read_raw,
+ .read_avail = ad4134_read_avail,
+ .write_raw = ad4134_write_raw,
+ .debugfs_reg_access = ad4134_debugfs_reg_access,
+};
+
+static void ad4134_prepare_offload_msg(struct iio_dev *indio_dev)
+{
+ struct ad4134_state *st = iio_priv(indio_dev);
+ unsigned int base_len = spi_bpw_to_bytes(AD4134_CHAN_PRECISION_BITS);
+
+ st->xfers.cs_off = 1;
+ st->xfers.bits_per_word = AD4134_CHAN_PRECISION_BITS;
+ st->xfers.len = base_len * AD4134_NUM_CHANNELS;
+ if (st->spi->num_rx_lanes > 1)
+ st->xfers.multi_lane_mode = SPI_MULTI_LANE_MODE_STRIPE;
+
+ st->xfers.offload_flags = SPI_OFFLOAD_XFER_RX_STREAM;
+
+ spi_message_init_with_transfers(&st->msg, &st->xfers, 1);
+}
+
+static int ad4134_offload_buffer_postenable(struct iio_dev *indio_dev)
+{
+ struct ad4134_state *st = iio_priv(indio_dev);
+ int ret, access_ret;
+
+ ret = ad4134_claim_sample_access(st);
+ if (ret)
+ return ret;
+
+ ad4134_prepare_offload_msg(indio_dev);
+ st->msg.offload = st->offload;
+ ret = spi_optimize_message(st->spi, &st->msg);
+ if (ret)
+ goto out_offload_release;
+
+ ret = spi_offload_trigger_enable(st->offload, st->offload_trigger,
+ &st->offload_trigger_config);
+ if (ret)
+ goto out_unoptimize;
+
+ return 0;
+
+out_unoptimize:
+ spi_unoptimize_message(&st->msg);
+
+out_offload_release:
+ access_ret = ad4134_release_sample_access(st);
+ if (access_ret)
+ dev_err(&st->spi->dev, "reg input select error: %d\n", access_ret);
+
+ return ret;
+}
+
+static int ad4134_offload_buffer_predisable(struct iio_dev *indio_dev)
+{
+ struct ad4134_state *st = iio_priv(indio_dev);
+
+ spi_offload_trigger_disable(st->offload, st->offload_trigger);
+ spi_unoptimize_message(&st->msg);
+
+ return ad4134_release_sample_access(st);
+}
+
+static const struct iio_buffer_setup_ops ad4134_offload_buffer_setup_ops = {
+ .postenable = &ad4134_offload_buffer_postenable,
+ .predisable = &ad4134_offload_buffer_predisable,
+};
+
+static int ad4134_pwm_get(struct ad4134_state *st)
+{
+ struct device *dev = &st->spi->dev;
+
+ st->odr_pwm = devm_pwm_get(dev, NULL);
+ if (IS_ERR(st->odr_pwm))
+ return dev_err_probe(dev, PTR_ERR(st->odr_pwm),
+ "failed to get ODR PWM\n");
+
+ return 0;
+}
+
+static const struct spi_offload_config ad4134_offload_config = {
+ .capability_flags = SPI_OFFLOAD_CAP_TRIGGER |
+ SPI_OFFLOAD_CAP_RX_STREAM_DMA,
+};
+
+static int ad4134_offload_buffer_setup(struct iio_dev *indio_dev, struct spi_device *spi)
+{
+ struct ad4134_state *st = iio_priv(indio_dev);
+ struct device *dev = &spi->dev;
+ struct dma_chan *rx_dma;
+
+ st->offload_trigger = devm_spi_offload_trigger_get(dev, st->offload,
+ SPI_OFFLOAD_TRIGGER_PERIODIC);
+ if (IS_ERR(st->offload_trigger))
+ return dev_err_probe(dev, PTR_ERR(st->offload_trigger),
+ "failed to get offload trigger\n");
+
+ st->offload_trigger_config.type = SPI_OFFLOAD_TRIGGER_PERIODIC;
+
+ rx_dma = devm_spi_offload_rx_stream_request_dma_chan(dev, st->offload);
+ if (IS_ERR(rx_dma))
+ return dev_err_probe(dev, PTR_ERR(rx_dma),
+ "failed to get offload RX DMA\n");
+
+ return devm_iio_dmaengine_buffer_setup_with_handle(dev, indio_dev, rx_dma,
+ IIO_BUFFER_DIRECTION_IN);
+}
+
+/* The chip converts and outputs all 4 channels on each sample request */
+static const unsigned long ad4134_scan_masks[] = {
+ BIT(3) | BIT(2) | BIT(1) | BIT(0),
+ 0
+};
+
+static int ad4134_offload_setup(struct iio_dev *indio_dev, struct ad4134_state *st)
+{
+ struct device *dev = &st->spi->dev;
+ int ret;
+
+ ret = ad4134_pwm_get(st);
+ if (ret)
+ return ret;
+
+ ret = ad4134_offload_buffer_setup(indio_dev, st->spi);
+ if (ret)
+ return ret;
+
+ /*
+ * Start with a sampling rate slower than 374 kSPS because that is the
+ * maximum rate supported with wideband filter (default on power up).
+ */
+ st->odr_hz = 250 * HZ_PER_KHZ;
+ ret = ad4134_update_conversion_rate(st, st->odr_hz);
+ if (ret)
+ return dev_err_probe(dev, ret, "failed to set sampling freq\n");
+
+ indio_dev->setup_ops = &ad4134_offload_buffer_setup_ops;
+ indio_dev->available_scan_masks = ad4134_scan_masks;
+
+ switch (st->spi->num_rx_lanes) {
+ case 1:
+ return regmap_update_bits(st->regmap, AD4134_DIG_IF_CFG_REG,
+ AD4134_DIF_IF_CFG_FORMAT_MASK,
+ FIELD_PREP(AD4134_DIF_IF_CFG_FORMAT_MASK,
+ AD4134_DATA_FORMAT_SINGLE_CH_MODE));
+ case 4:
+ return regmap_update_bits(st->regmap, AD4134_DIG_IF_CFG_REG,
+ AD4134_DIF_IF_CFG_FORMAT_MASK,
+ FIELD_PREP(AD4134_DIF_IF_CFG_FORMAT_MASK,
+ AD4134_DATA_FORMAT_QUAD_CH_PARALLEL));
+ default:
+ return dev_err_probe(dev, -EINVAL,
+ "unsupported number of spi-rx-bus-width elements: %d\n",
+ st->spi->num_rx_lanes);
+ }
+}
+
static const char * const ad4143_required_regulators[] = {
"avdd5", "dvdd5", "iovdd",
};
@@ -680,6 +1021,9 @@ static int ad4134_clock_select(struct ad4134_state *st)
dev_warn(dev, "invalid external clock frequency %lu\n",
st->sys_clk_hz);
+ if (!st->sys_clk_hz)
+ return dev_err_probe(dev, -EINVAL, "0 Hz external clock\n");
+
return 0;
}
@@ -699,10 +1043,7 @@ static int ad4134_probe(struct spi_device *spi)
st->spi = spi;
indio_dev->name = "ad4134";
- indio_dev->channels = ad4134_chan_set;
- indio_dev->num_channels = ARRAY_SIZE(ad4134_chan_set);
indio_dev->modes = INDIO_DIRECT_MODE;
- indio_dev->info = &ad4134_info;
ret = ad4134_regulator_setup(st);
if (ret)
@@ -782,17 +1123,40 @@ static int ad4134_probe(struct spi_device *spi)
indio_dev->setup_ops = &ad4134_buffer_setup_ops;
}
- st->odr_gpio = devm_gpiod_get(dev, "odr", GPIOD_OUT_LOW);
- if (IS_ERR(st->odr_gpio))
- return dev_err_probe(dev, PTR_ERR(st->odr_gpio),
- "failed to get ODR GPIO\n");
+ st->offload = devm_spi_offload_get(dev, spi, &ad4134_offload_config);
+ ret = PTR_ERR_OR_ZERO(st->offload);
+ /* Fall back to low speed usage when no SPI offload is available. */
+ if (ret == -ENODEV) {
+ st->odr_gpio = devm_gpiod_get(dev, "odr", GPIOD_OUT_LOW);
+ if (IS_ERR(st->odr_gpio))
+ return dev_err_probe(dev, PTR_ERR(st->odr_gpio),
+ "failed to get ODR GPIO\n");
- ret = devm_iio_triggered_buffer_setup(dev, indio_dev,
- iio_pollfunc_store_time,
- ad4134_trigger_handler,
- NULL);
- if (ret)
- return ret;
+ indio_dev->info = &ad4134_info;
+ indio_dev->channels = ad4134_chan_set;
+ indio_dev->num_channels = ARRAY_SIZE(ad4134_chan_set);
+ ret = devm_iio_triggered_buffer_setup(dev, indio_dev,
+ iio_pollfunc_store_time,
+ ad4134_trigger_handler,
+ st->spi_mode != AD4134_SPI_MODE_NO_CS ?
+ &ad4134_buffer_setup_ops : NULL);
+ if (ret)
+ return ret;
+ } else if (ret) {
+ return dev_err_probe(dev, ret, "failed to get offload\n");
+ } else {
+ if (st->spi_mode == AD4134_SPI_MODE_NO_CS)
+ return dev_err_probe(dev, -EPROTONOSUPPORT,
+ "Unsupported min I/O + offload config\n");
+
+ indio_dev->info = &ad4134_offload_info;
+ indio_dev->channels = ad4134_offload_chan_set;
+ indio_dev->num_channels = ARRAY_SIZE(ad4134_offload_chan_set);
+ ret = ad4134_offload_setup(indio_dev, st);
+ if (ret)
+ return dev_err_probe(dev, ret,
+ "failed to setup SPI offload\n");
+ }
/* Bump precision to 24-bit */
ret = regmap_update_bits(st->regmap, AD4134_DATA_PACKET_CONFIG_REG,
@@ -838,3 +1202,4 @@ module_spi_driver(ad4134_driver);
MODULE_AUTHOR("Marcelo Schmitt <marcelo.schmitt@analog.com>");
MODULE_DESCRIPTION("Analog Devices AD4134 SPI driver");
MODULE_LICENSE("GPL");
+MODULE_IMPORT_NS("IIO_DMAENGINE_BUFFER");
--
2.53.0
^ permalink raw reply [flat|nested] 14+ messages in thread* [PATCH v4 13/13] Docs: iio: Add AD4134
2026-10-06 18:15 [PATCH v4 00/13] iio: adc: ad4134: Enable greater sample rate data capture Marcelo Schmitt
` (11 preceding siblings ...)
2026-10-06 18:19 ` [PATCH v4 12/13] iio: adc: ad4134: Support high-speed data capture Marcelo Schmitt
@ 2026-10-06 18:19 ` Marcelo Schmitt
12 siblings, 0 replies; 14+ messages in thread
From: Marcelo Schmitt @ 2026-10-06 18:19 UTC (permalink / raw)
To: linux-iio, devicetree, linux-kernel, linux
Cc: jic23, nuno.sa, dlechner, andy, Michael.Hennerich, robh, krzk+dt,
conor+dt, corbet, skhan, marcelo.schmitt1
Add initial documentation for the ad4134 IIO driver.
Signed-off-by: Marcelo Schmitt <marcelo.schmitt@analog.com>
---
Change log v3 -> v4:
- Minor adjust to AD4134 IIO Doc that made the doc 1 line shorter.
Documentation/iio/ad4134.rst | 127 +++++++++++++++++++++++++++++++++++
Documentation/iio/index.rst | 1 +
MAINTAINERS | 1 +
3 files changed, 129 insertions(+)
create mode 100644 Documentation/iio/ad4134.rst
diff --git a/Documentation/iio/ad4134.rst b/Documentation/iio/ad4134.rst
new file mode 100644
index 000000000000..c0889a21cd77
--- /dev/null
+++ b/Documentation/iio/ad4134.rst
@@ -0,0 +1,127 @@
+.. SPDX-License-Identifier: GPL-2.0-only
+
+=============
+AD4134 driver
+=============
+
+Device driver for Analog Devices Inc. AD4134 and similar ADCs.
+
+Supported devices
+=================
+
+* `AD4134 <https://www.analog.com/AD4134>`_
+* `AD7134 <https://www.analog.com/AD7134>`_
+
+Wiring connections
+------------------
+
+AD4134 and similar ADCs can operate in a few different wiring configurations.
+Because AD4134 also supports control modes other than through SPI protocol,
+the following pins must be statically set for all of the wiring modes described
+below.
+
++----------------------------+----------------------+--------------------+
+| Pin Function | Level | Description |
++============================+======================+====================+
+| PIN/SPI | High | SPI control mode |
++----------------------------+----------------------+--------------------+
+| MODE | Low | ASRC slave mode |
++----------------------------+----------------------+--------------------+
+| DEC0/DCLKI | Low | DCLK input |
++----------------------------+----------------------+--------------------+
+| DEC1/DCLKMODE | Low | Gated DCLK |
++----------------------------+----------------------+--------------------+
+
+Minimum I/O mode
+^^^^^^^^^^^^^^^^
+
+The minimum I/O mode wiring allows AD4134 register and data access with the
+conventional set of SPI bus lines. In this mode, the peripheral CS pin must be
+tied to GND. A possible connection schema that sets AD4134 digital interface for
+minimum I/O mode is::
+
+ +------------+ +-------------+
+ | AD4134 | | SPI |
+ | | | Controller |
+ | DCLK |<--+ | |
+ | SCLK |<--+---- | SCLK |
+ | SDI |<--------| SDO |
+ | SDO |-------->| SDI |
+ | ODR |<--------| GPIO |
+ | CS |----+ | |
+ +------------+ | +-------------+
+ V
+ GND
+
+Set ``adi,spi-mode = "no-cs"`` in device tree to indicate the device is
+connected in minimum I/O wiring configuration.
+
+SPI 4-wire mode - single lane
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+
+The conventional SPI 4-wire configuration except a multiplexer is used to
+select between SDO (for register data) and DOUT0 (for ADC sample data).::
+
+ +-----------------------+ +-----------------+
+ | AD4134 | | SPI Controller |
+ | | | |
+ | SPI interface SCLK |<------------------------| SCLK |
+ | for register CS |<------------------------| CS |
+ | access SDI |<------------------------| SDO |
+ | SDO |------->|¯¯¯¯\ | |
+ | | |MUX >--------->| SDI |
+ | Data interface DOUT0 |------->|____/ | |
+ | for ADC sample | ^ | |
+ | data read | | | |
+ | DCLK |<------------------------| DCLK |
+ | ODR |<----------------+ +->| Offload Trigger |
+ +-----------------------+ | | | +-----------------+
+ | | +--| PWM1 |
+ | +-------| PWM0 |
+ +--------------| GPIO |
+ +-----------------+
+
+Set ``adi,spi-mode = "4-wire"`` in device tree to indicate the device is
+connected in SPI 4-wire configuration.
+
+For SPI offload operation, a PWM is connected to the ADC ODR pin. The ``pwms``
+firmware property specifies the PWM that is connected to the ADC. The SPI
+offload will have a ``trigger-sources`` property to indicate the SPI offload
+(PWM) trigger source.
+
+To achieve high sample rates while meeting ADC timing requirements, an offset
+must be added between the rising edges of PWM0 and PWM1 to delay the SPI
+transfer until ADC sample data is available. This requires a specialized PWM
+controller that can provide such an offset. The `AD4134-FMC HDL project`_, for
+example, can be configured to sample AD4134 at high speed sample rates.
+
+.. _AD4134-FMC HDL project: https://analogdevicesinc.github.io/hdl/projects/ad4134_fmc/index.html
+
+SPI 4-wire mode - multi-lane
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+
+Maximum throughput rate can be achieved by reading 4 input lines simultaneously.::
+
+ +-----------------------+ +-----------------+
+ | AD4134 | | SPI Controller |
+ | | | |
+ | SPI interface SCLK |<------------------------| SCLK |
+ | for register CS |<------------------------| CS |
+ | access SDI |<------------------------| SDO |
+ | SDO |------->|¯¯¯¯\ | |
+ | | |MUX >--------->| SDI0 |
+ | Data interface DOUT0 |------->|____/ | |
+ | for ADC sample | ^ | |
+ | data read DOUT1 |------------------------>| SDI1 |
+ | DOUT2 |------------------------>| SDI2 |
+ | DOUT3 |------------------------>| SDI3 |
+ | DCLK |<------------------------| DCLK |
+ | ODR |<----------------+ +->| Offload Trigger |
+ +-----------------------+ | | | +-----------------+
+ | | +--| PWM1 |
+ | +-------| PWM0 |
+ +--------------| GPIO |
+ +-----------------+
+
+Each of SDI0 to SDI3 connect to a different SPI controller deserializer
+(``spi-rx-bus-width = <1>, <1>, <1>, <1>``).
diff --git a/Documentation/iio/index.rst b/Documentation/iio/index.rst
index d0fb32f4b80f..3a49e08a2366 100644
--- a/Documentation/iio/index.rst
+++ b/Documentation/iio/index.rst
@@ -23,6 +23,7 @@ Industrial I/O Kernel Drivers
ad4000
ad4030
ad4062
+ ad4134
ad4691
ad4695
ad7191
diff --git a/MAINTAINERS b/MAINTAINERS
index 3a2dfd1a4fd8..82a810ac788e 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1533,6 +1533,7 @@ L: linux-iio@vger.kernel.org
S: Supported
W: https://ez.analog.com/linux-software-drivers
F: Documentation/devicetree/bindings/iio/adc/adi,ad4134.yaml
+F: Documentation/iio/ad4134.rst
F: drivers/iio/adc/ad4134.c
ANALOG DEVICES INC AD4170-4 DRIVER
--
2.53.0
^ permalink raw reply [flat|nested] 14+ messages in thread