Re: [PATCH] clk: qcom: dispcc-sc8280xp: remove CLK_SET_RATE_PARENT from byte_div_clk_src dividers

[Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>]

On 3/3/26 12:55 PM, Pengyu Luo wrote:
> From: White Lewis <liu224806@gmail.com>
> 
> The four byte_div_clk_src dividers (disp{0,1}_cc_mdss_byte{0,1}_div_clk_src)
> had CLK_SET_RATE_PARENT set. When the DSI driver calls clk_set_rate() on
> byte_intf_clk, the rate-change propagates through the divider up to the
> parent PLL (byte_clk_src), halving the byte clock rate.
> 
> A simiar issue had been also encountered on SM8750.
> b8501febdc51 ("clk: qcom: dispcc-sm8750: Drop incorrect CLK_SET_RATE_PARENT on byte intf parent").
> 
> Likewise, remove CLK_SET_RATE_PARENT from all four byte divider clocks
> so that clk_set_rate() on the divider adjusts only the divider ratio,
> leaving the parent PLL untouched.
> 
> Fixes: 4a66e76fdb6d ("clk: qcom: Add SC8280XP display clock controller")
> Signed-off-by: White Lewis <liu224806@gmail.com>
> [pengyu: reword]
> Signed-off-by: Pengyu Luo <mitltlatltl@gmail.com>
> ---

Looks like more platforms have this issue.. thanks for fixing this

Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>

Konrad