[PATCH 1/4] arm64: dts: qcom: hawi: Sort IPCC client IDs

[PATCH 1/4] arm64: dts: qcom: hawi: Sort IPCC client IDs

[Mukesh Ojha]

The IPCC client ID macros within each group in hawi-ipcc.h are not
ordered by their numeric values, making it harder to cross-check
against hardware documentation and spot missing IDs at a glance.

Sort the defines in the IPCC_MPROC, IPCC_COMPUTE_L0, IPCC_COMPUTE_L1,
and IPCC_FENCE groups by ascending value.

Signed-off-by: Mukesh Ojha <mukesh.ojha@oss.qualcomm.com>
---
 arch/arm64/boot/dts/qcom/hawi-ipcc.h | 16 ++++++++--------
 1 file changed, 8 insertions(+), 8 deletions(-)

diff --git a/arch/arm64/boot/dts/qcom/hawi-ipcc.h b/arch/arm64/boot/dts/qcom/hawi-ipcc.h
index 67f228e1aa0e..7659357691c1 100644
--- a/arch/arm64/boot/dts/qcom/hawi-ipcc.h
+++ b/arch/arm64/boot/dts/qcom/hawi-ipcc.h
@@ -14,11 +14,11 @@
 #define IPCC_MPROC_SDC			4
 #define IPCC_MPROC_CDSP			5
 #define IPCC_MPROC_APSS			6
-#define IPCC_MPROC_SPSS			15
-#define IPCC_MPROC_TME			16
 #define IPCC_MPROC_SOCCP		12
 #define IPCC_MPROC_DCP			13
 #define IPCC_MPROC_QECP			14
+#define IPCC_MPROC_SPSS			15
+#define IPCC_MPROC_TME			16
 
 #define IPCC_COMPUTE_L0_LPASS		1
 #define IPCC_COMPUTE_L0_CDSP		2
@@ -26,10 +26,10 @@
 #define IPCC_COMPUTE_L0_GPU		4
 #define IPCC_COMPUTE_L0_CVP		8
 #define IPCC_COMPUTE_L0_CAM		9
-#define IPCC_COMPUTE_L0_VPU		12
-#define IPCC_COMPUTE_L0_SOCCP		16
 #define IPCC_COMPUTE_L0_CAM1		10
 #define IPCC_COMPUTE_L0_DCP		11
+#define IPCC_COMPUTE_L0_VPU		12
+#define IPCC_COMPUTE_L0_SOCCP		16
 
 #define IPCC_COMPUTE_L1_LPASS		1
 #define IPCC_COMPUTE_L1_CDSP		2
@@ -37,10 +37,10 @@
 #define IPCC_COMPUTE_L1_GPU		4
 #define IPCC_COMPUTE_L1_CVP		8
 #define IPCC_COMPUTE_L1_CAM		9
-#define IPCC_COMPUTE_L1_VPU		12
-#define IPCC_COMPUTE_L1_SOCCP		16
 #define IPCC_COMPUTE_L1_CAM1		10
 #define IPCC_COMPUTE_L1_DCP		11
+#define IPCC_COMPUTE_L1_VPU		12
+#define IPCC_COMPUTE_L1_SOCCP		16
 
 #define IPCC_PERIPH_CDSP		2
 #define IPCC_PERIPH_APSS		3
@@ -53,9 +53,9 @@
 #define IPCC_FENCE_GPU			4
 #define IPCC_FENCE_CVP			8
 #define IPCC_FENCE_CAM			9
-#define IPCC_FENCE_VPU			20
-#define IPCC_FENCE_SOCCP		24
 #define IPCC_FENCE_CAM1			10
 #define IPCC_FENCE_DCP			11
+#define IPCC_FENCE_VPU			20
+#define IPCC_FENCE_SOCCP		24
 
 #endif
-- 
2.55.0

[PATCH 2/4] arm64: dts: qcom: hawi: Fix PCIe IOMMU maps

[Mukesh Ojha]

apps_smmu defines #iommu-cells = <2>, requiring five cells per
iommu-map tuple: rid-base, phandle, sid-base, sid-mask, and length.
The pcie0 and pcie1 nodes specify only four cells and were omitting
the mask field.

Add the missing 0x0 mask cell to both tuples in each PCIe node.

Signed-off-by: Mukesh Ojha <mukesh.ojha@oss.qualcomm.com>
---
 arch/arm64/boot/dts/qcom/hawi.dtsi | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/arch/arm64/boot/dts/qcom/hawi.dtsi b/arch/arm64/boot/dts/qcom/hawi.dtsi
index c7ae8133b9cd..89bf0f59304d 100644
--- a/arch/arm64/boot/dts/qcom/hawi.dtsi
+++ b/arch/arm64/boot/dts/qcom/hawi.dtsi
@@ -2958,8 +2958,8 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
 
 			operating-points-v2 = <&pcie0_opp_table>;
 
-			iommu-map = <0 &apps_smmu 0x1000 0x1>,
-				    <0x100 &apps_smmu 0x1001 0x1>;
+			iommu-map = <0 &apps_smmu 0x1000 0x0 0x1>,
+				    <0x100 &apps_smmu 0x1001 0x0 0x1>;
 
 			interrupt-map = <0 0 0 1 &intc 0 0 GIC_ESPI 213 IRQ_TYPE_LEVEL_HIGH>,
 					<0 0 0 2 &intc 0 0 GIC_ESPI 214 IRQ_TYPE_LEVEL_HIGH>,
@@ -3140,8 +3140,8 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
 
 			operating-points-v2 = <&pcie1_opp_table>;
 
-			iommu-map = <0 &apps_smmu 0x1080 0x1>,
-				    <0x100 &apps_smmu 0x1081 0x1>;
+			iommu-map = <0 &apps_smmu 0x1080 0x0 0x1>,
+				    <0x100 &apps_smmu 0x1081 0x0 0x1>;
 
 			interrupt-map = <0 0 0 1 &intc 0 0 GIC_ESPI 106 IRQ_TYPE_LEVEL_HIGH>,
 					<0 0 0 2 &intc 0 0 GIC_ESPI 107 IRQ_TYPE_LEVEL_HIGH>,
-- 
2.55.0

Re: [PATCH 2/4] arm64: dts: qcom: hawi: Fix PCIe IOMMU maps

[Konrad Dybcio]

On 9/25/26 12:13 PM, Mukesh Ojha wrote:
> apps_smmu defines #iommu-cells = <2>, requiring five cells per
> iommu-map tuple: rid-base, phandle, sid-base, sid-mask, and length.
> The pcie0 and pcie1 nodes specify only four cells and were omitting
> the mask field.
> 
> Add the missing 0x0 mask cell to both tuples in each PCIe node.
> 
> Signed-off-by: Mukesh Ojha <mukesh.ojha@oss.qualcomm.com>
> ---

Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>

Konrad

[PATCH 3/4] arm64: dts: qcom: hawi: Enable SoCCP by default

[Mukesh Ojha]

SoCCP remoteproc is marked disabled in the hawi dtsi and enabled in
hawi-mtp.dts, but that is not the right approach, as it should be enabled
by default. For Hawi, like a few other targets such as Kaanapali and
Glymur, SoCCP boots up in early stages of the boot chain before the OS
takes over. So, it is default on.

Signed-off-by: Mukesh Ojha <mukesh.ojha@oss.qualcomm.com>
---
 arch/arm64/boot/dts/qcom/hawi-mtp.dts | 2 --
 arch/arm64/boot/dts/qcom/hawi.dtsi    | 2 --
 2 files changed, 4 deletions(-)

diff --git a/arch/arm64/boot/dts/qcom/hawi-mtp.dts b/arch/arm64/boot/dts/qcom/hawi-mtp.dts
index 7709582491f9..88e0afa791b3 100644
--- a/arch/arm64/boot/dts/qcom/hawi-mtp.dts
+++ b/arch/arm64/boot/dts/qcom/hawi-mtp.dts
@@ -910,8 +910,6 @@ &remoteproc_mpss {
 &remoteproc_soccp {
 	firmware-name = "qcom/hawi/soccp.mbn",
 			"qcom/hawi/soccp_dtb.mbn";
-
-	status = "okay";
 };
 
 &sdhc_2 {
diff --git a/arch/arm64/boot/dts/qcom/hawi.dtsi b/arch/arm64/boot/dts/qcom/hawi.dtsi
index 89bf0f59304d..d47440791479 100644
--- a/arch/arm64/boot/dts/qcom/hawi.dtsi
+++ b/arch/arm64/boot/dts/qcom/hawi.dtsi
@@ -1859,8 +1859,6 @@ remoteproc_soccp: remoteproc@d00000 {
 			qcom,smem-state-names = "stop",
 						"ping";
 
-			status = "disabled";
-
 			glink-edge {
 				interrupts-extended = <&ipcc IPCC_MPROC_SOCCP
 							     IPCC_MPROC_SIGNAL_GLINK_QMP
-- 
2.55.0

Re: [PATCH 3/4] arm64: dts: qcom: hawi: Enable SoCCP by default

[Konrad Dybcio]

On 9/25/26 12:13 PM, Mukesh Ojha wrote:
> SoCCP remoteproc is marked disabled in the hawi dtsi and enabled in
> hawi-mtp.dts, but that is not the right approach, as it should be enabled
> by default. For Hawi, like a few other targets such as Kaanapali and
> Glymur, SoCCP boots up in early stages of the boot chain before the OS
> takes over. So, it is default on.
> 
> Signed-off-by: Mukesh Ojha <mukesh.ojha@oss.qualcomm.com>
> ---

Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>

Konrad

[PATCH 4/4] arm64: dts: qcom: hawi: Trivial fix

[Mukesh Ojha]

A stray blank line sits between the sdhc2 OPP table closing brace and
the sdhc2 node closing brace in hawi.dtsi, and the pmic_glink_dp_out
endpoint in hawi-mtp.dts carries a commented-out remote-endpoint that
was never wired up, unlike the intentionally empty SBU endpoints for
now.

Signed-off-by: Mukesh Ojha <mukesh.ojha@oss.qualcomm.com>
---
 arch/arm64/boot/dts/qcom/hawi-mtp.dts | 1 -
 arch/arm64/boot/dts/qcom/hawi.dtsi    | 1 -
 2 files changed, 2 deletions(-)

diff --git a/arch/arm64/boot/dts/qcom/hawi-mtp.dts b/arch/arm64/boot/dts/qcom/hawi-mtp.dts
index 88e0afa791b3..c38e5fab7a2c 100644
--- a/arch/arm64/boot/dts/qcom/hawi-mtp.dts
+++ b/arch/arm64/boot/dts/qcom/hawi-mtp.dts
@@ -120,7 +120,6 @@ port@2 {
 					reg = <2>;
 
 					pmic_glink_dp_out: endpoint {
-						//remote-endpoint = <&usb_dp_qmpphy_dp_in>;
 					};
 				};
 			};
diff --git a/arch/arm64/boot/dts/qcom/hawi.dtsi b/arch/arm64/boot/dts/qcom/hawi.dtsi
index d47440791479..6b0a0ff0faa4 100644
--- a/arch/arm64/boot/dts/qcom/hawi.dtsi
+++ b/arch/arm64/boot/dts/qcom/hawi.dtsi
@@ -3295,7 +3295,6 @@ opp-202000000 {
 					required-opps = <&rpmhpd_opp_svs_l1>;
 				};
 			};
-
 		};
 
 		ufs_mem_phy: phy@1d80000 {
-- 
2.55.0