[RFC PATCH 0/2] arm64: qcom: Add BWMON support for SA8775p

[RFC PATCH 0/2] arm64: qcom: Add BWMON support for SA8775p

[Tengfei Fan]

Add CPU and LLCC BWMON nodes and their corresponding OPP tables for
SA8775p SoC.

Signed-off-by: Tengfei Fan <quic_tengfan@quicinc.com>
---

This patch series depends on patch series:
"[PATCH 2/4] soc: qcom: icc-bwmon: Allow for interrupts to be shared across instances"
https://lore.kernel.org/lkml/20240604011157.2358019-3-quic_sibis@quicinc.com/

Tengfei Fan (2):
  dt-bindings: interconnect: qcom-bwmon: Document SA8775p bwmon
    compatibles
  arm64: dts: qcom: sa8775p: Add CPU and LLCC BWMON

 .../interconnect/qcom,msm8998-bwmon.yaml      |   2 +
 arch/arm64/boot/dts/qcom/sa8775p.dtsi         | 115 ++++++++++++++++++
 2 files changed, 117 insertions(+)


base-commit: 6906a84c482f098d31486df8dc98cead21cce2d0
-- 
2.25.1

[RFC PATCH 1/2] dt-bindings: interconnect: qcom-bwmon: Document SA8775p bwmon compatibles

[Tengfei Fan]

Document the compatibles used to describe the bwmons present on the
SA8775p platform.

Signed-off-by: Tengfei Fan <quic_tengfan@quicinc.com>
---
 .../devicetree/bindings/interconnect/qcom,msm8998-bwmon.yaml    | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/Documentation/devicetree/bindings/interconnect/qcom,msm8998-bwmon.yaml b/Documentation/devicetree/bindings/interconnect/qcom,msm8998-bwmon.yaml
index 05067e197abe..0dfed45ab713 100644
--- a/Documentation/devicetree/bindings/interconnect/qcom,msm8998-bwmon.yaml
+++ b/Documentation/devicetree/bindings/interconnect/qcom,msm8998-bwmon.yaml
@@ -26,6 +26,7 @@ properties:
       - items:
           - enum:
               - qcom,qcm2290-cpu-bwmon
+              - qcom,sa8775p-cpu-bwmon
               - qcom,sc7180-cpu-bwmon
               - qcom,sc7280-cpu-bwmon
               - qcom,sc8280xp-cpu-bwmon
@@ -38,6 +39,7 @@ properties:
           - const: qcom,sdm845-bwmon    # BWMON v4, unified register space
       - items:
           - enum:
+              - qcom,sa8775p-llcc-bwmon
               - qcom,sc7180-llcc-bwmon
               - qcom,sc8280xp-llcc-bwmon
               - qcom,sm6350-cpu-bwmon
-- 
2.25.1

[RFC PATCH 2/2] arm64: dts: qcom: sa8775p: Add CPU and LLCC BWMON

[Tengfei Fan]

Add CPU and LLCC BWMON nodes and their corresponding opp tables for
SA8775p SoC.
SA8775p has two cpu clusters, with each cluster having a set of
CPU-to-LLCC BWMON registers. Consequently, there are two sets of
CPU-to-LLCC registers.

Signed-off-by: Tengfei Fan <quic_tengfan@quicinc.com>
---
 arch/arm64/boot/dts/qcom/sa8775p.dtsi | 115 ++++++++++++++++++++++++++
 1 file changed, 115 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi
index 3808fafd6bec..32dd9fc7c532 100644
--- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi
+++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi
@@ -2885,6 +2885,121 @@ serdes1: phy@8902000 {
 			status = "disabled";
 		};
 
+		pmu@9091000 {
+			compatible = "qcom,sa8775p-llcc-bwmon", "qcom,sc7280-llcc-bwmon";
+			reg = <0x0 0x9091000 0x0 0x1000>;
+			interrupts = <GIC_SPI 620 IRQ_TYPE_LEVEL_HIGH>;
+			interconnects = <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY
+					 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>;
+
+			operating-points-v2 = <&llcc_bwmon_opp_table>;
+
+			llcc_bwmon_opp_table: opp-table {
+				compatible = "operating-points-v2";
+
+				opp-0 {
+					opp-peak-kBps = <762000>;
+				};
+
+				opp-1 {
+					opp-peak-kBps = <1720000>;
+				};
+
+				opp-2 {
+					opp-peak-kBps = <2086000>;
+				};
+
+				opp-3 {
+					opp-peak-kBps = <2601000>;
+				};
+
+				opp-4 {
+					opp-peak-kBps = <2929000>;
+				};
+
+				opp-5 {
+					opp-peak-kBps = <5931000>;
+				};
+
+				opp-6 {
+					opp-peak-kBps = <6515000>;
+				};
+
+				opp-7 {
+					opp-peak-kBps = <7984000>;
+				};
+
+				opp-8 {
+					opp-peak-kBps = <10437000>;
+				};
+
+				opp-9 {
+					opp-peak-kBps = <12195000>;
+				};
+			};
+		};
+
+		pmu@90b5400 {
+			compatible = "qcom,sa8775p-cpu-bwmon", "qcom,sdm845-bwmon";
+			reg = <0x0 0x90b5400 0x0 0x600>;
+			interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>;
+			interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+					 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>;
+
+			operating-points-v2 = <&cpu_cluster0_bwmon_opp_table>;
+
+			cpu_cluster0_bwmon_opp_table: opp-table {
+				compatible = "operating-points-v2";
+
+				opp-0 {
+					opp-peak-kBps = <9155000>;
+				};
+
+				opp-1 {
+					opp-peak-kBps = <12298000>;
+				};
+
+				opp-2 {
+					opp-peak-kBps = <14236000>;
+				};
+
+				opp-3 {
+					opp-peak-kBps = <16265000>;
+				};
+			};
+
+		};
+
+		pmu@90b6400 {
+			compatible = "qcom,sa8775p-cpu-bwmon", "qcom,sdm845-bwmon";
+			reg = <0x0 0x90b6400 0x0 0x600>;
+			interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>;
+			interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+					 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>;
+
+			operating-points-v2 = <&cpu_cluster1_bwmon_opp_table>;
+
+			cpu_cluster1_bwmon_opp_table: opp-table {
+				compatible = "operating-points-v2";
+
+				opp-0 {
+					opp-peak-kBps = <9155000>;
+				};
+
+				opp-1 {
+					opp-peak-kBps = <12298000>;
+				};
+
+				opp-2 {
+					opp-peak-kBps = <14236000>;
+				};
+
+				opp-3 {
+					opp-peak-kBps = <16265000>;
+				};
+			};
+		};
+
 		llcc: system-cache-controller@9200000 {
 			compatible = "qcom,sa8775p-llcc";
 			reg = <0x0 0x09200000 0x0 0x80000>,
-- 
2.25.1

Re: [RFC PATCH 0/2] arm64: qcom: Add BWMON support for SA8775p

[Dmitry Baryshkov]

On Mon, Jun 17, 2024 at 05:29:38PM GMT, Tengfei Fan wrote:
> Add CPU and LLCC BWMON nodes and their corresponding OPP tables for
> SA8775p SoC.

This series is marked as RFC, Request For Comments. What kind of
comments are expected for the series?

> 
> Signed-off-by: Tengfei Fan <quic_tengfan@quicinc.com>
> ---
> 
> This patch series depends on patch series:
> "[PATCH 2/4] soc: qcom: icc-bwmon: Allow for interrupts to be shared across instances"
> https://lore.kernel.org/lkml/20240604011157.2358019-3-quic_sibis@quicinc.com/
> 
> Tengfei Fan (2):
>   dt-bindings: interconnect: qcom-bwmon: Document SA8775p bwmon
>     compatibles
>   arm64: dts: qcom: sa8775p: Add CPU and LLCC BWMON
> 
>  .../interconnect/qcom,msm8998-bwmon.yaml      |   2 +
>  arch/arm64/boot/dts/qcom/sa8775p.dtsi         | 115 ++++++++++++++++++
>  2 files changed, 117 insertions(+)
> 
> 
> base-commit: 6906a84c482f098d31486df8dc98cead21cce2d0
> -- 
> 2.25.1
> 

-- 
With best wishes
Dmitry

Re: [RFC PATCH 0/2] arm64: qcom: Add BWMON support for SA8775p

[Tengfei Fan]

On 6/17/2024 5:43 PM, Dmitry Baryshkov wrote:
> On Mon, Jun 17, 2024 at 05:29:38PM GMT, Tengfei Fan wrote:
>> Add CPU and LLCC BWMON nodes and their corresponding OPP tables for
>> SA8775p SoC.
> 
> This series is marked as RFC, Request For Comments. What kind of
> comments are expected for the series?
> 

I found that the BWMON patch for x1e80100[1] is currently under review. 
There are upstream comments suggesting that we reference the same shared 
OPP table from all the BWMONs that share the same OPP table. However, 
there will be some DTBS CHECK warnings[2] if we do reference the same 
shared OPP table.

Therefore, I pushed this patch series to collect some comments on 
whether we can have separate OPP tables for each BWMON, as the OPP table 
of "pmu@90b5400" and "pmu@90b6400" in this patch series.

[1] 
https://lore.kernel.org/lkml/4ef1d9a9-6a0e-4324-b6d5-2ae225855b03@linaro.org/

[2]
arch/arm64/boot/dts/qcom/sa8775p-ride.dtb: pmu@90b5400: 'opp-table' is a 
required property from schema $id:
http://devicetree.org/schemas/interconnect/qcom,msm8998-bwmon.yaml#

>>
>> Signed-off-by: Tengfei Fan <quic_tengfan@quicinc.com>
>> ---
>>
>> This patch series depends on patch series:
>> "[PATCH 2/4] soc: qcom: icc-bwmon: Allow for interrupts to be shared across instances"
>> https://lore.kernel.org/lkml/20240604011157.2358019-3-quic_sibis@quicinc.com/
>>
>> Tengfei Fan (2):
>>    dt-bindings: interconnect: qcom-bwmon: Document SA8775p bwmon
>>      compatibles
>>    arm64: dts: qcom: sa8775p: Add CPU and LLCC BWMON
>>
>>   .../interconnect/qcom,msm8998-bwmon.yaml      |   2 +
>>   arch/arm64/boot/dts/qcom/sa8775p.dtsi         | 115 ++++++++++++++++++
>>   2 files changed, 117 insertions(+)
>>
>>
>> base-commit: 6906a84c482f098d31486df8dc98cead21cce2d0
>> -- 
>> 2.25.1
>>
> 

-- 
Thx and BRs,
Tengfei Fan

Re: [RFC PATCH 0/2] arm64: qcom: Add BWMON support for SA8775p

[Dmitry Baryshkov]

On Mon, Jun 17, 2024 at 06:42:42PM GMT, Tengfei Fan wrote:
> 
> 
> On 6/17/2024 5:43 PM, Dmitry Baryshkov wrote:
> > On Mon, Jun 17, 2024 at 05:29:38PM GMT, Tengfei Fan wrote:
> > > Add CPU and LLCC BWMON nodes and their corresponding OPP tables for
> > > SA8775p SoC.
> > 
> > This series is marked as RFC, Request For Comments. What kind of
> > comments are expected for the series?
> > 
> 
> I found that the BWMON patch for x1e80100[1] is currently under review.
> There are upstream comments suggesting that we reference the same shared OPP
> table from all the BWMONs that share the same OPP table. However, there will
> be some DTBS CHECK warnings[2] if we do reference the same shared OPP table.
> 
> Therefore, I pushed this patch series to collect some comments on whether we
> can have separate OPP tables for each BWMON, as the OPP table of
> "pmu@90b5400" and "pmu@90b6400" in this patch series.

Thank you for the explanation. Now why wasn't this a part of the cover
letter?

> 
> [1]
> https://lore.kernel.org/lkml/4ef1d9a9-6a0e-4324-b6d5-2ae225855b03@linaro.org/
> 
> [2]
> arch/arm64/boot/dts/qcom/sa8775p-ride.dtb: pmu@90b5400: 'opp-table' is a
> required property from schema $id:
> http://devicetree.org/schemas/interconnect/qcom,msm8998-bwmon.yaml#
> 
> > > 
> > > Signed-off-by: Tengfei Fan <quic_tengfan@quicinc.com>
> > > ---
> > > 
> > > This patch series depends on patch series:
> > > "[PATCH 2/4] soc: qcom: icc-bwmon: Allow for interrupts to be shared across instances"
> > > https://lore.kernel.org/lkml/20240604011157.2358019-3-quic_sibis@quicinc.com/
> > > 
> > > Tengfei Fan (2):
> > >    dt-bindings: interconnect: qcom-bwmon: Document SA8775p bwmon
> > >      compatibles
> > >    arm64: dts: qcom: sa8775p: Add CPU and LLCC BWMON
> > > 
> > >   .../interconnect/qcom,msm8998-bwmon.yaml      |   2 +
> > >   arch/arm64/boot/dts/qcom/sa8775p.dtsi         | 115 ++++++++++++++++++
> > >   2 files changed, 117 insertions(+)
> > > 
> > > 
> > > base-commit: 6906a84c482f098d31486df8dc98cead21cce2d0
> > > -- 
> > > 2.25.1
> > > 
> > 
> 
> -- 
> Thx and BRs,
> Tengfei Fan

-- 
With best wishes
Dmitry

Re: [RFC PATCH 0/2] arm64: qcom: Add BWMON support for SA8775p

[Tengfei Fan]

On 6/17/2024 7:00 PM, Dmitry Baryshkov wrote:
> On Mon, Jun 17, 2024 at 06:42:42PM GMT, Tengfei Fan wrote:
>>
>>
>> On 6/17/2024 5:43 PM, Dmitry Baryshkov wrote:
>>> On Mon, Jun 17, 2024 at 05:29:38PM GMT, Tengfei Fan wrote:
>>>> Add CPU and LLCC BWMON nodes and their corresponding OPP tables for
>>>> SA8775p SoC.
>>>
>>> This series is marked as RFC, Request For Comments. What kind of
>>> comments are expected for the series?
>>>
>>
>> I found that the BWMON patch for x1e80100[1] is currently under review.
>> There are upstream comments suggesting that we reference the same shared OPP
>> table from all the BWMONs that share the same OPP table. However, there will
>> be some DTBS CHECK warnings[2] if we do reference the same shared OPP table.
>>
>> Therefore, I pushed this patch series to collect some comments on whether we
>> can have separate OPP tables for each BWMON, as the OPP table of
>> "pmu@90b5400" and "pmu@90b6400" in this patch series.
> 
> Thank you for the explanation. Now why wasn't this a part of the cover
> letter?

I think I previously had some misunderstandings about the cover letter. 
I mistakenly thought that certain information should not be included in 
the cover letter. In the future, I will make an effort to include 
complete information in cover letter.

> 
>>
>> [1]
>> https://lore.kernel.org/lkml/4ef1d9a9-6a0e-4324-b6d5-2ae225855b03@linaro.org/
>>
>> [2]
>> arch/arm64/boot/dts/qcom/sa8775p-ride.dtb: pmu@90b5400: 'opp-table' is a
>> required property from schema $id:
>> http://devicetree.org/schemas/interconnect/qcom,msm8998-bwmon.yaml#
>>
>>>>
>>>> Signed-off-by: Tengfei Fan <quic_tengfan@quicinc.com>
>>>> ---
>>>>
>>>> This patch series depends on patch series:
>>>> "[PATCH 2/4] soc: qcom: icc-bwmon: Allow for interrupts to be shared across instances"
>>>> https://lore.kernel.org/lkml/20240604011157.2358019-3-quic_sibis@quicinc.com/
>>>>
>>>> Tengfei Fan (2):
>>>>     dt-bindings: interconnect: qcom-bwmon: Document SA8775p bwmon
>>>>       compatibles
>>>>     arm64: dts: qcom: sa8775p: Add CPU and LLCC BWMON
>>>>
>>>>    .../interconnect/qcom,msm8998-bwmon.yaml      |   2 +
>>>>    arch/arm64/boot/dts/qcom/sa8775p.dtsi         | 115 ++++++++++++++++++
>>>>    2 files changed, 117 insertions(+)
>>>>
>>>>
>>>> base-commit: 6906a84c482f098d31486df8dc98cead21cce2d0
>>>> -- 
>>>> 2.25.1
>>>>
>>>
>>
>> -- 
>> Thx and BRs,
>> Tengfei Fan
> 

-- 
Thx and BRs,
Tengfei Fan