* [PATCH v4 0/2] Enable SDHC1 and SDHC2 on QCS615
@ 2024-12-06 2:37 Yuanjie Yang
2024-12-06 2:37 ` [PATCH v4 1/2] arm64: dts: qcom: qcs615: add SDHC1 and SDHC2 Yuanjie Yang
2024-12-06 2:37 ` [PATCH v4 2/2] arm64: dts: qcom: qcs615-ride: enable " Yuanjie Yang
0 siblings, 2 replies; 5+ messages in thread
From: Yuanjie Yang @ 2024-12-06 2:37 UTC (permalink / raw)
To: ulf.hansson, robh, krzk+dt, conor+dt, bhupesh.sharma, andersson,
konradybcio
Cc: linux-mmc, devicetree, linux-kernel, linux-arm-msm,
quic_tingweiz, quic_yuanjiey
Add SDHC1 and SDHC2 support to the QCS615 Ride platform. The
SDHC1 and SDHC2 of QCS615 are derived from SM6115. Include
the configuration of SDHC1-related and SDHC2-related opp,
power, and interconnect settings in the device tree.
Signed-off-by: Yuanjie Yang <quic_yuanjiey@quicinc.com>
---
This patch series depends on below patch series:
https://lore.kernel.org/all/20241104-add_initial_support_for_qcs615-v5-0-9dde8d7b80b0@quicinc.com/
https://lore.kernel.org/all/20241105032107.9552-1-quic_qqzhou@quicinc.com/
Changes in v4:
- Move properties which are not properties of the SoC to board DTS
- Add ice region to SDHC1 Node reg
- Add 50Mhz 200Mhz to SDHC1 opp table, add 50Mhz to SDHC2 opp table
- fix SDHC2 Node compatible space
- Link to v3: https://lore.kernel.org/all/20241122065101.1918470-1-quic_yuanjiey@quicinc.com/
Changes in v3:
- Improve the commit messages and cover letter
- Link to v2: https://lore.kernel.org/all/20241106072343.2070933-1-quic_yuanjiey@quicinc.com/
Changes in v2:
- Improve the commit messages and cover letter
- Remove applied patches 1
- Pad sdhc_1 node and sdhc_2 node register addresses to 8 hex digits
- Adjust sdhc_1 node and sdhc_2 node register addresses to hexadecimal
- Modify sdhc_2 vqmmc-supply incorrect power configuration
- Link to v1: https://lore.kernel.org/all/20241023092708.604195-1-quic_yuanjiey@quicinc.com/
---
Yuanjie Yang (2):
arm64: dts: qcom: qcs615: add SDHC1 and SDHC2
arm64: dts: qcom: qcs615-ride: enable SDHC1 and SDHC2
arch/arm64/boot/dts/qcom/qcs615-ride.dts | 37 ++++
arch/arm64/boot/dts/qcom/qcs615.dtsi | 209 +++++++++++++++++++++++
2 files changed, 246 insertions(+)
--
2.34.1
^ permalink raw reply [flat|nested] 5+ messages in thread
* [PATCH v4 1/2] arm64: dts: qcom: qcs615: add SDHC1 and SDHC2
2024-12-06 2:37 [PATCH v4 0/2] Enable SDHC1 and SDHC2 on QCS615 Yuanjie Yang
@ 2024-12-06 2:37 ` Yuanjie Yang
2024-12-13 12:56 ` Konrad Dybcio
2024-12-06 2:37 ` [PATCH v4 2/2] arm64: dts: qcom: qcs615-ride: enable " Yuanjie Yang
1 sibling, 1 reply; 5+ messages in thread
From: Yuanjie Yang @ 2024-12-06 2:37 UTC (permalink / raw)
To: ulf.hansson, robh, krzk+dt, conor+dt, bhupesh.sharma, andersson,
konradybcio
Cc: linux-mmc, devicetree, linux-kernel, linux-arm-msm,
quic_tingweiz, quic_yuanjiey
Add SDHC1 and SDHC2 support to the QCS615 Ride platform.
Signed-off-by: Yuanjie Yang <quic_yuanjiey@quicinc.com>
---
arch/arm64/boot/dts/qcom/qcs615.dtsi | 209 +++++++++++++++++++++++++++
1 file changed, 209 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/qcs615.dtsi b/arch/arm64/boot/dts/qcom/qcs615.dtsi
index 590beb37f441..e52bf8c77884 100644
--- a/arch/arm64/boot/dts/qcom/qcs615.dtsi
+++ b/arch/arm64/boot/dts/qcom/qcs615.dtsi
@@ -399,6 +399,72 @@ qfprom: efuse@780000 {
#size-cells = <1>;
};
+ sdhc_1: mmc@7c4000 {
+ compatible = "qcom,qcs615-sdhci", "qcom,sdhci-msm-v5";
+ reg = <0x0 0x007c4000 0x0 0x1000>,
+ <0x0 0x007c5000 0x0 0x1000>,
+ <0x0 0x007c8000 0x0 0x8000>;
+ reg-names = "hc",
+ "cqhci",
+ "ice";
+
+ interrupts = <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 644 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "hc_irq",
+ "pwr_irq";
+
+ clocks = <&gcc GCC_SDCC1_AHB_CLK>,
+ <&gcc GCC_SDCC1_APPS_CLK>,
+ <&rpmhcc RPMH_CXO_CLK>,
+ <&gcc GCC_SDCC1_ICE_CORE_CLK>;
+ clock-names = "iface",
+ "core",
+ "xo",
+ "ice";
+
+ resets = <&gcc GCC_SDCC1_BCR>;
+
+ power-domains = <&rpmhpd RPMHPD_CX>;
+ operating-points-v2 = <&sdhc1_opp_table>;
+ iommus = <&apps_smmu 0x02c0 0x0>;
+ interconnects = <&aggre1_noc MASTER_SDCC_1 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &config_noc SLAVE_SDCC_1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "sdhc-ddr",
+ "cpu-sdhc";
+
+ qcom,dll-config = <0x000f642c>;
+ qcom,ddr-config = <0x80040868>;
+ supports-cqe;
+ dma-coherent;
+ status = "disabled";
+
+ sdhc1_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-50000000 {
+ opp-hz = /bits/ 64 <50000000>;
+ required-opps = <&rpmhpd_opp_low_svs>;
+ };
+
+ opp-100000000 {
+ opp-hz = /bits/ 64 <100000000>;
+ required-opps = <&rpmhpd_opp_svs>;
+ };
+
+ opp-200000000 {
+ opp-hz = /bits/ 64 <200000000>;
+ required-opps = <&rpmhpd_opp_svs_l1>;
+ };
+
+ opp-384000000 {
+ opp-hz = /bits/ 64 <384000000>;
+ required-opps = <&rpmhpd_opp_nom>;
+ };
+ };
+ };
+
qupv3_id_0: geniqup@8c0000 {
compatible = "qcom,geni-se-qup";
reg = <0x0 0x008c0000 0x0 0x6000>;
@@ -494,6 +560,149 @@ qup_uart0_rx: qup-uart0-rx-state {
pins = "gpio17";
function = "qup0";
};
+
+ sdc1_state_on: sdc1-on-state {
+ clk-pins {
+ pins = "sdc1_clk";
+ bias-disable;
+ drive-strength = <16>;
+ };
+
+ cmd-pins {
+ pins = "sdc1_cmd";
+ bias-pull-up;
+ drive-strength = <10>;
+ };
+
+ data-pins {
+ pins = "sdc1_data";
+ bias-pull-up;
+ drive-strength = <10>;
+ };
+
+ rclk-pins {
+ pins = "sdc1_rclk";
+ bias-pull-down;
+ };
+ };
+
+ sdc1_state_off: sdc1-off-state {
+ clk-pins {
+ pins = "sdc1_clk";
+ bias-disable;
+ drive-strength = <2>;
+ };
+
+ cmd-pins {
+ pins = "sdc1_cmd";
+ bias-pull-up;
+ drive-strength = <2>;
+ };
+
+ data-pins {
+ pins = "sdc1_data";
+ bias-pull-up;
+ drive-strength = <2>;
+ };
+
+ rclk-pins {
+ pins = "sdc1_rclk";
+ bias-pull-down;
+ };
+ };
+
+ sdc2_state_on: sdc2-on-state {
+ clk-pins {
+ pins = "sdc2_clk";
+ bias-disable;
+ drive-strength = <16>;
+ };
+
+ cmd-pins {
+ pins = "sdc2_cmd";
+ bias-pull-up;
+ drive-strength = <10>;
+ };
+
+ data-pins {
+ pins = "sdc2_data";
+ bias-pull-up;
+ drive-strength = <10>;
+ };
+ };
+
+ sdc2_state_off: sdc2-off-state {
+ clk-pins {
+ pins = "sdc2_clk";
+ bias-disable;
+ drive-strength = <2>;
+ };
+
+ cmd-pins {
+ pins = "sdc2_cmd";
+ bias-pull-up;
+ drive-strength = <2>;
+ };
+
+ data-pins {
+ pins = "sdc2_data";
+ bias-pull-up;
+ drive-strength = <2>;
+ };
+ };
+ };
+
+ sdhc_2: mmc@8804000 {
+ compatible = "qcom,qcs615-sdhci", "qcom,sdhci-msm-v5";
+ reg = <0x0 0x08804000 0x0 0x1000>;
+ reg-names = "hc";
+
+ interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "hc_irq",
+ "pwr_irq";
+
+ clocks = <&gcc GCC_SDCC2_AHB_CLK>,
+ <&gcc GCC_SDCC2_APPS_CLK>,
+ <&rpmhcc RPMH_CXO_CLK>;
+ clock-names = "iface",
+ "core",
+ "xo";
+
+ power-domains = <&rpmhpd RPMHPD_CX>;
+ operating-points-v2 = <&sdhc2_opp_table>;
+ iommus = <&apps_smmu 0x02a0 0x0>;
+ resets = <&gcc GCC_SDCC2_BCR>;
+ interconnects = <&aggre1_noc MASTER_SDCC_2 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &config_noc SLAVE_SDCC_2 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "sdhc-ddr",
+ "cpu-sdhc";
+
+ qcom,dll-config = <0x0007642c>;
+ qcom,ddr-config = <0x80040868>;
+ dma-coherent;
+ status = "disabled";
+
+ sdhc2_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-50000000 {
+ opp-hz = /bits/ 64 <50000000>;
+ required-opps = <&rpmhpd_opp_low_svs>;
+ };
+
+ opp-100000000 {
+ opp-hz = /bits/ 64 <100000000>;
+ required-opps = <&rpmhpd_opp_svs>;
+ };
+
+ opp-202000000 {
+ opp-hz = /bits/ 64 <202000000>;
+ required-opps = <&rpmhpd_opp_nom>;
+ };
+ };
};
dc_noc: interconnect@9160000 {
--
2.34.1
^ permalink raw reply [flat|nested] 5+ messages in thread
* [PATCH v4 2/2] arm64: dts: qcom: qcs615-ride: enable SDHC1 and SDHC2
2024-12-06 2:37 [PATCH v4 0/2] Enable SDHC1 and SDHC2 on QCS615 Yuanjie Yang
2024-12-06 2:37 ` [PATCH v4 1/2] arm64: dts: qcom: qcs615: add SDHC1 and SDHC2 Yuanjie Yang
@ 2024-12-06 2:37 ` Yuanjie Yang
1 sibling, 0 replies; 5+ messages in thread
From: Yuanjie Yang @ 2024-12-06 2:37 UTC (permalink / raw)
To: ulf.hansson, robh, krzk+dt, conor+dt, bhupesh.sharma, andersson,
konradybcio
Cc: linux-mmc, devicetree, linux-kernel, linux-arm-msm,
quic_tingweiz, quic_yuanjiey
Enable SDHC1 and SDHC2 on the Qualcomm QCS615 Ride platform.
Signed-off-by: Yuanjie Yang <quic_yuanjiey@quicinc.com>
---
arch/arm64/boot/dts/qcom/qcs615-ride.dts | 37 ++++++++++++++++++++++++
1 file changed, 37 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/qcs615-ride.dts b/arch/arm64/boot/dts/qcom/qcs615-ride.dts
index ee6cab3924a6..84d63f9298db 100644
--- a/arch/arm64/boot/dts/qcom/qcs615-ride.dts
+++ b/arch/arm64/boot/dts/qcom/qcs615-ride.dts
@@ -5,6 +5,7 @@
/dts-v1/;
#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
+#include <dt-bindings/gpio/gpio.h>
#include "qcs615.dtsi"
/ {
model = "Qualcomm Technologies, Inc. QCS615 Ride";
@@ -12,6 +13,8 @@ / {
chassis-type = "embedded";
aliases {
+ mmc0 = &sdhc_1;
+ mmc1 = &sdhc_2;
serial0 = &uart0;
};
@@ -210,6 +213,40 @@ &rpmhcc {
clocks = <&xo_board_clk>;
};
+&sdhc_1 {
+ pinctrl-0 = <&sdc1_state_on>;
+ pinctrl-1 = <&sdc1_state_off>;
+ pinctrl-names = "default", "sleep";
+
+ bus-width = <8>;
+ mmc-ddr-1_8v;
+ mmc-hs200-1_8v;
+ mmc-hs400-1_8v;
+ mmc-hs400-enhanced-strobe;
+ vmmc-supply = <&vreg_l17a>;
+ vqmmc-supply = <&vreg_s4a>;
+
+ non-removable;
+ no-sd;
+ no-sdio;
+
+ status = "okay";
+};
+
+&sdhc_2 {
+ pinctrl-0 = <&sdc2_state_on>;
+ pinctrl-1 = <&sdc2_state_off>;
+ pinctrl-names = "default", "sleep";
+
+ bus-width = <4>;
+ cd-gpios = <&tlmm 99 GPIO_ACTIVE_LOW>;
+
+ vmmc-supply = <&vreg_l10a>;
+ vqmmc-supply = <&vreg_s4a>;
+
+ status = "okay";
+};
+
&uart0 {
status = "okay";
};
--
2.34.1
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH v4 1/2] arm64: dts: qcom: qcs615: add SDHC1 and SDHC2
2024-12-06 2:37 ` [PATCH v4 1/2] arm64: dts: qcom: qcs615: add SDHC1 and SDHC2 Yuanjie Yang
@ 2024-12-13 12:56 ` Konrad Dybcio
2024-12-16 6:19 ` Yuanjie Yang
0 siblings, 1 reply; 5+ messages in thread
From: Konrad Dybcio @ 2024-12-13 12:56 UTC (permalink / raw)
To: Yuanjie Yang, ulf.hansson, robh, krzk+dt, conor+dt,
bhupesh.sharma, andersson, konradybcio
Cc: linux-mmc, devicetree, linux-kernel, linux-arm-msm, quic_tingweiz
On 6.12.2024 3:37 AM, Yuanjie Yang wrote:
> Add SDHC1 and SDHC2 support to the QCS615 Ride platform.
>
> Signed-off-by: Yuanjie Yang <quic_yuanjiey@quicinc.com>
> ---
> arch/arm64/boot/dts/qcom/qcs615.dtsi | 209 +++++++++++++++++++++++++++
> 1 file changed, 209 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/qcs615.dtsi b/arch/arm64/boot/dts/qcom/qcs615.dtsi
> index 590beb37f441..e52bf8c77884 100644
> --- a/arch/arm64/boot/dts/qcom/qcs615.dtsi
> +++ b/arch/arm64/boot/dts/qcom/qcs615.dtsi
> @@ -399,6 +399,72 @@ qfprom: efuse@780000 {
> #size-cells = <1>;
> };
>
> + sdhc_1: mmc@7c4000 {
> + compatible = "qcom,qcs615-sdhci", "qcom,sdhci-msm-v5";
> + reg = <0x0 0x007c4000 0x0 0x1000>,
> + <0x0 0x007c5000 0x0 0x1000>,
> + <0x0 0x007c8000 0x0 0x8000>;
> + reg-names = "hc",
> + "cqhci",
> + "ice";
> +
> + interrupts = <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 644 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-names = "hc_irq",
> + "pwr_irq";
> +
> + clocks = <&gcc GCC_SDCC1_AHB_CLK>,
> + <&gcc GCC_SDCC1_APPS_CLK>,
> + <&rpmhcc RPMH_CXO_CLK>,
> + <&gcc GCC_SDCC1_ICE_CORE_CLK>;
> + clock-names = "iface",
> + "core",
> + "xo",
> + "ice";
> +
> + resets = <&gcc GCC_SDCC1_BCR>;
> +
> + power-domains = <&rpmhpd RPMHPD_CX>;
> + operating-points-v2 = <&sdhc1_opp_table>;
> + iommus = <&apps_smmu 0x02c0 0x0>;
> + interconnects = <&aggre1_noc MASTER_SDCC_1 QCOM_ICC_TAG_ALWAYS
> + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
> + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
> + &config_noc SLAVE_SDCC_1 QCOM_ICC_TAG_ALWAYS>;
QCOM_ICC_TAG_ACTIVE_ONLY for the CPU path
> + interconnect-names = "sdhc-ddr",
> + "cpu-sdhc";
> +
> + qcom,dll-config = <0x000f642c>;
> + qcom,ddr-config = <0x80040868>;
> + supports-cqe;
> + dma-coherent;
> + status = "disabled";
Nit: please add a newline before status for consistency
(both comments apply to both controllers)
Konrad
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH v4 1/2] arm64: dts: qcom: qcs615: add SDHC1 and SDHC2
2024-12-13 12:56 ` Konrad Dybcio
@ 2024-12-16 6:19 ` Yuanjie Yang
0 siblings, 0 replies; 5+ messages in thread
From: Yuanjie Yang @ 2024-12-16 6:19 UTC (permalink / raw)
To: Konrad Dybcio, ulf.hansson, robh, krzk+dt, conor+dt,
bhupesh.sharma, andersson, konradybcio
Cc: linux-mmc, devicetree, linux-kernel, linux-arm-msm,
quic_tingweiz, quic_yuanjiey
On Fri, Dec 13, 2024 at 01:56:04PM +0100, Konrad Dybcio wrote:
> On 6.12.2024 3:37 AM, Yuanjie Yang wrote:
> > Add SDHC1 and SDHC2 support to the QCS615 Ride platform.
> >
> > Signed-off-by: Yuanjie Yang <quic_yuanjiey@quicinc.com>
> > ---
> > arch/arm64/boot/dts/qcom/qcs615.dtsi | 209 +++++++++++++++++++++++++++
> > 1 file changed, 209 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/qcom/qcs615.dtsi b/arch/arm64/boot/dts/qcom/qcs615.dtsi
> > index 590beb37f441..e52bf8c77884 100644
> > --- a/arch/arm64/boot/dts/qcom/qcs615.dtsi
> > +++ b/arch/arm64/boot/dts/qcom/qcs615.dtsi
> > @@ -399,6 +399,72 @@ qfprom: efuse@780000 {
> > #size-cells = <1>;
> > };
> >
> > + sdhc_1: mmc@7c4000 {
> > + compatible = "qcom,qcs615-sdhci", "qcom,sdhci-msm-v5";
> > + reg = <0x0 0x007c4000 0x0 0x1000>,
> > + <0x0 0x007c5000 0x0 0x1000>,
> > + <0x0 0x007c8000 0x0 0x8000>;
> > + reg-names = "hc",
> > + "cqhci",
> > + "ice";
> > +
> > + interrupts = <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 644 IRQ_TYPE_LEVEL_HIGH>;
> > + interrupt-names = "hc_irq",
> > + "pwr_irq";
> > +
> > + clocks = <&gcc GCC_SDCC1_AHB_CLK>,
> > + <&gcc GCC_SDCC1_APPS_CLK>,
> > + <&rpmhcc RPMH_CXO_CLK>,
> > + <&gcc GCC_SDCC1_ICE_CORE_CLK>;
> > + clock-names = "iface",
> > + "core",
> > + "xo",
> > + "ice";
> > +
> > + resets = <&gcc GCC_SDCC1_BCR>;
> > +
> > + power-domains = <&rpmhpd RPMHPD_CX>;
> > + operating-points-v2 = <&sdhc1_opp_table>;
> > + iommus = <&apps_smmu 0x02c0 0x0>;
> > + interconnects = <&aggre1_noc MASTER_SDCC_1 QCOM_ICC_TAG_ALWAYS
> > + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
> > + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
> > + &config_noc SLAVE_SDCC_1 QCOM_ICC_TAG_ALWAYS>;
>
> QCOM_ICC_TAG_ACTIVE_ONLY for the CPU path
OK, I will fix it in next patch.
> > + interconnect-names = "sdhc-ddr",
> > + "cpu-sdhc";
> > +
> > + qcom,dll-config = <0x000f642c>;
> > + qcom,ddr-config = <0x80040868>;
> > + supports-cqe;
> > + dma-coherent;
> > + status = "disabled";
>
> Nit: please add a newline before status for consistency
I will add a newline before status in next patch.
> (both comments apply to both controllers)
OK I will fix both controllers(SDHC_1 and SDHC_2).
> Konrad
Thanks,
yuanjie
^ permalink raw reply [flat|nested] 5+ messages in thread
end of thread, other threads:[~2024-12-16 6:20 UTC | newest]
Thread overview: 5+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2024-12-06 2:37 [PATCH v4 0/2] Enable SDHC1 and SDHC2 on QCS615 Yuanjie Yang
2024-12-06 2:37 ` [PATCH v4 1/2] arm64: dts: qcom: qcs615: add SDHC1 and SDHC2 Yuanjie Yang
2024-12-13 12:56 ` Konrad Dybcio
2024-12-16 6:19 ` Yuanjie Yang
2024-12-06 2:37 ` [PATCH v4 2/2] arm64: dts: qcom: qcs615-ride: enable " Yuanjie Yang
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