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From: Shawn Lin <shawn.lin@rock-chips.com>
To: FUKAUMI Naoki <naoki@radxa.com>, Niklas Cassel <cassel@kernel.org>
Cc: shawn.lin@rock-chips.com, "Damien Le Moal" <dlemoal@kernel.org>,
	"Anand Moon" <linux.amoon@gmail.com>,
	linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
	linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org,
	"Dragan Simic" <dsimic@manjaro.org>,
	"Lorenzo Pieralisi" <lpieralisi@kernel.org>,
	"Krzysztof Wilczyński" <kw@linux.com>,
	"Rob Herring" <robh@kernel.org>,
	"Bjorn Helgaas" <bhelgaas@google.com>,
	"Heiko Stuebner" <heiko@sntech.de>,
	mani@kernel.org
Subject: Re: [RESEND] Re: [PATCH] PCI: dw-rockchip: Skip waiting for link up
Date: Mon, 10 Nov 2025 18:15:33 +0800	[thread overview]
Message-ID: <dc932773-af5b-4af7-a0d0-8cc72dfbd3c7@rock-chips.com> (raw)
In-Reply-To: <0C31787C387488ED+fd39bfe6-0844-4a87-bf48-675dd6d6a2df@radxa.com>

在 2025/11/10 星期一 15:52, FUKAUMI Naoki 写道:
> Hi Shawn,
> 
> On 11/10/25 16:12, Shawn Lin wrote:
> (snip)> Thanks for testing. I just got a ASM2806 switch as yours and 
> verified it
>> on vanilla v6.18-rc5. After 30 times of cold boot, two NVMes behind
>> ASM2806 work as expected. Nothing special happened when I checked
>> with PA as well. You could help check the log and lspci dump there[1].
>>
>> [1]https://pastebin.com/sAF1fT0g
> 
> Thanks for the info!
> 
> I tried ASM2806 on Radxa ROCK 5B (RK3588).
>   https://gist.github.com/RadxaNaoki/640e47d377add9fe38301de164d4058e
> 
> It doesn't work on PCIe 2.0 (M.2 E Key), but it does work on PCIe 3.0 
> (M.2 M Key).
> 
> Could you try PCIe 2.0 slot on your board?

I did, it doesn't work on PCIe 2.0 slot. From the PA, I could see
the link is still in training during pci_host_probe() is called.
Add some delay before pci_rescan_bus() in pcie-dw-rockchip doesn't
help. But the below change should work as we delayed pci_host_probe().

--- a/drivers/pci/controller/dwc/pcie-dw-rockchip.c
+++ b/drivers/pci/controller/dwc/pcie-dw-rockchip.c
@@ -236,6 +236,8 @@ static int rockchip_pcie_start_link(struct dw_pcie *pci)
         msleep(PCIE_T_PVPERL_MS);
         gpiod_set_value_cansleep(rockchip->rst_gpio, 1);

+       msleep(50);
+
         return 0;

Otherwise we got:

[    0.841518] pci_bus 0003:33: busn_res: can not insert [bus 33-31] 
under [bus 32-31] (conflicts with (null) [bus 32-31])
[    0.842596] pci_bus 0003:33: busn_res: [bus 33-31] end is updated to 33
[    0.843184] pci_bus 0003:33: busn_res: can not insert [bus 33] under 
[bus 32-31] (conflicts with (null) [bus 32-31])
[    0.844120] pci 0003:32:00.0: devices behind bridge are unusable 
because [bus 33] cannot be assigned for them
[    0.845229] pci_bus 0003:34: busn_res: can not insert [bus 34-31] 
under [bus 32-31] (conflicts with (null) [bus 32-31])
[    0.846309] pci_bus 0003:34: busn_res: [bus 34-31] end is updated to 34
[    0.846898] pci_bus 0003:34: busn_res: can not insert [bus 34] under 
[bus 32-31] (conflicts with (null) [bus 32-31])
[    0.847833] pci 0003:32:06.0: devices behind bridge are unusable 
because [bus 34] cannot be assigned for them
[    0.848923] pci_bus 0003:35: busn_res: can not insert [bus 35-31] 
under [bus 32-31] (conflicts with (null) [bus 32-31])
[    0.850014] pci_bus 0003:35: busn_res: [bus 35-31] end is updated to 35
[    0.850605] pci_bus 0003:35: busn_res: can not insert [bus 35] under 
[bus 32-31] (conflicts with (null) [bus 32-31])
[    0.851540] pci 0003:32:0e.0: devices behind bridge are unusable 
because [bus 35] cannot be assigned for them
[    0.852424] pci_bus 0003:32: busn_res: [bus 32-31] end is updated to 35
[    0.853028] pci_bus 0003:32: busn_res: can not insert [bus 32-35] 
under [bus 31] (conflicts with (null) [bus 31])
[    0.853184] hub 3-0:1.0: USB hub found
[    0.853931] pci 0003:31:00.0: devices behind bridge are unusable 
because [bus 32-35] cannot be assigned for them
[    0.854262] hub 3-0:1.0: 1 port detected
[    0.855144] pcieport 0003:30:00.0: bridge has subordinate 31 but max 
busn 35
[    0.855722] hub 4-0:1.0: USB hub found
[    0.856109] pci 0003:32:00.0: PCI bridge to [bus 33]
[    0.856939] pci 0003:32:06.0: PCI bridge to [bus 34]
[    0.857133] hub 4-0:1.0: 1 port detected
[    0.857430] pci 0003:32:0e.0: PCI bridge to [bus 35]
[    0.858236] pci 0003:31:00.0: PCI bridge to [bus 32-35]

> 
> Best regards,
> 
> -- 
> FUKAUMI Naoki
> Radxa Computer (Shenzhen) Co., Ltd.
> 
> 


  reply	other threads:[~2025-11-10 10:15 UTC|newest]

Thread overview: 30+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-01-13 10:59 Niklas Cassel
2025-01-13 19:27 ` Bjorn Helgaas
2025-01-13 21:14   ` Niklas Cassel
2025-01-13 20:22 ` Bjorn Helgaas
2025-10-21  4:26 ` FUKAUMI Naoki
2025-10-21  7:10   ` Shawn Lin
2025-11-08 12:34     ` Niklas Cassel
2025-11-08 13:27       ` Niklas Cassel
2025-11-08 14:21         ` Diederik de Haas
2025-11-09  4:42         ` FUKAUMI Naoki
2025-11-09 12:28           ` Niklas Cassel
2025-11-09 23:16             ` FUKAUMI Naoki
2025-11-09 23:26             ` [RESEND] " FUKAUMI Naoki
2025-11-10  2:30               ` Shawn Lin
2025-11-10  4:56                 ` FUKAUMI Naoki
2025-11-10  7:12                   ` Shawn Lin
2025-11-10  7:52                     ` FUKAUMI Naoki
2025-11-10 10:15                       ` Shawn Lin [this message]
2025-11-10 12:34                         ` Niklas Cassel
2025-11-10 12:41                           ` Niklas Cassel
2025-11-10 15:21                             ` FUKAUMI Naoki
2025-11-10 15:37                               ` Manivannan Sadhasivam
2025-11-10 15:53                           ` Manivannan Sadhasivam
2025-11-10 19:59                             ` Niklas Cassel
2025-11-10 22:14                               ` FUKAUMI Naoki
2025-11-11  2:09                               ` FUKAUMI Naoki
2025-11-11  3:17                                 ` Shawn Lin
2025-11-11 14:00                                   ` Niklas Cassel
2025-11-11  1:11                             ` Shawn Lin
2025-11-10 11:24               ` Manivannan Sadhasivam

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