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From: David Heidelberg <david@ixit.cz>
To: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>,
	Robert Foss <rfoss@kernel.org>, Todor Tomov <todor.too@gmail.com>,
	Bryan O'Donoghue <bryan.odonoghue@linaro.org>,
	Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org>,
	Mauro Carvalho Chehab <mchehab@kernel.org>,
	Luca Weiss <luca.weiss@fairphone.com>,
	Petr Hodina <phodina@protonmail.com>,
	Casey Connolly <casey.connolly@linaro.org>,
	"Dr. Git" <drgitx@gmail.com>
Cc: Joel Selvaraj <foss@joelselvaraj.com>,
	Kieran Bingham <kbingham@kernel.org>,
	Sakari Ailus <sakari.ailus@linux.intel.com>,
	linux-media@vger.kernel.org, linux-arm-msm@vger.kernel.org,
	linux-kernel@vger.kernel.org, phone-devel@vger.kernel.org
Subject: Re: [PATCH WIP v2 3/8] media: qcom: camss: Prepare CSID for C-PHY support
Date: Thu, 11 Dec 2025 16:20:36 +0100	[thread overview]
Message-ID: <df5557e2-a086-48ca-b8e7-972cbdb7745a@ixit.cz> (raw)
In-Reply-To: <9af39b45-581b-4e25-8ab9-19015f00d6bc@oss.qualcomm.com>

On 05/12/2025 10:43, Konrad Dybcio wrote:
> On 12/4/25 5:32 PM, David Heidelberg via B4 Relay wrote:
>> From: David Heidelberg <david@ixit.cz>
>>
>> Inherit C-PHY information from CSIPHY, so we can configure CSID
>> properly.
>>
>> CSI2_RX_CFG0_PHY_TYPE_SEL must be set to 1, when C-PHY mode is used.
>>
>> Signed-off-by: David Heidelberg <david@ixit.cz>
>> ---
>>   drivers/media/platform/qcom/camss/camss-csid-gen2.c | 1 +
>>   drivers/media/platform/qcom/camss/camss-csid.c      | 1 +
>>   drivers/media/platform/qcom/camss/camss-csid.h      | 1 +
>>   3 files changed, 3 insertions(+)
>>
>> diff --git a/drivers/media/platform/qcom/camss/camss-csid-gen2.c b/drivers/media/platform/qcom/camss/camss-csid-gen2.c
>> index 2a1746dcc1c5b..033036ae28a4f 100644
>> --- a/drivers/media/platform/qcom/camss/camss-csid-gen2.c
>> +++ b/drivers/media/platform/qcom/camss/camss-csid-gen2.c
>> @@ -183,6 +183,7 @@ static void __csid_configure_rx(struct csid_device *csid,
>>   	val = (lane_cnt - 1) << CSI2_RX_CFG0_NUM_ACTIVE_LANES;
>>   	val |= phy->lane_assign << CSI2_RX_CFG0_DL0_INPUT_SEL;
>>   	val |= phy->csiphy_id << CSI2_RX_CFG0_PHY_NUM_SEL;
>> +	val |= csid->phy.cphy << CSI2_RX_CFG0_PHY_TYPE_SEL;
> 
> This field is 1-wide, this would be neater:
> 
> if (csid->phy.cphy)
> 	val |= BIT(CSI2_RX_CFG0_PHY_TYPE_SEL);

Hello Konrad,

while your change make sense as we work with 1-bit.
On other hand, due to TYPE_SEL naming, it's not very explicit why we set 
this bit when cphy is on.

Maybe I could propose renaming CSI2_RX_CFG0_PHY_TYPE_SEL to 
CSI2_RX_CFG0_PHY_TYPE_SEL_CPHY, then setting 1 to it would make sense.

Most clean solution to me would be something like

#define TYPE_SEL_DPHY	0
#define TYPE_SEL_CPHY	1

val |= (csid->phy.cphy ? TYPE_SEL_CPHY : TYPE_SEL_DPHY) << 
CSI2_RX_CFG0_PHY_TYPE_SEL

Do I overthinking this? What do you think?

David

> 
> Konrad

-- 
David Heidelberg


  reply	other threads:[~2025-12-11 15:20 UTC|newest]

Thread overview: 24+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-12-04 16:32 [PATCH WIP v2 0/8] media: camss: Add support for C-PHY configuration on Qualcomm platforms David Heidelberg via B4 Relay
2025-12-04 16:32 ` [PATCH WIP v2 1/8] media: qcom: camss: csiphy: Introduce PHY configuration David Heidelberg via B4 Relay
2025-12-04 16:32 ` [PATCH WIP v2 2/8] media: qcom: camss: csiphy-3ph: Use odd bits for configuring C-PHY lanes David Heidelberg via B4 Relay
2025-12-05 10:33   ` Bryan O'Donoghue
2025-12-05 11:59     ` David Heidelberg
2025-12-04 16:32 ` [PATCH WIP v2 3/8] media: qcom: camss: Prepare CSID for C-PHY support David Heidelberg via B4 Relay
2025-12-05  9:43   ` Konrad Dybcio
2025-12-11 15:20     ` David Heidelberg [this message]
2025-12-17 13:31       ` Konrad Dybcio
2025-12-17 15:02         ` David Heidelberg
2025-12-04 16:32 ` [PATCH WIP v2 4/8] media: qcom: camss: Initialize lanes after lane configuration is available David Heidelberg via B4 Relay
2025-12-04 16:32 ` [PATCH WIP v2 5/8] media: qcom: camss: csiphy-3ph: Add Gen2 v1.1 MIPI CSI-2 CPHY init David Heidelberg via B4 Relay
2025-12-05  9:54   ` Konrad Dybcio
2025-12-05 11:56     ` David Heidelberg
2025-12-05 12:00       ` Konrad Dybcio
2025-12-05 12:11         ` David Heidelberg
2025-12-04 16:32 ` [PATCH WIP v2 6/8] media: qcom: camss: csiphy-3ph: Add Gen2 v1.2.1 MIPI CSI-2 C-PHY init David Heidelberg via B4 Relay
2025-12-05  9:59   ` Konrad Dybcio
2025-12-04 16:32 ` [PATCH WIP v2 7/8] media: qcom: camss: csiphy-3ph: C-PHY needs own lane configuration David Heidelberg via B4 Relay
2025-12-05 10:01   ` Konrad Dybcio
2025-12-05 10:38   ` Bryan O'Donoghue
2025-12-05 10:39     ` Bryan O'Donoghue
2025-12-04 16:32 ` [PATCH WIP v2 8/8] media: qcom: camss: Account for C-PHY when calculating link frequency David Heidelberg via B4 Relay
2025-12-06  6:55   ` kernel test robot

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