Re: [PATCH WIP v2 3/8] media: qcom: camss: Prepare CSID for C-PHY support

[Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>]

On 12/11/25 4:20 PM, David Heidelberg wrote:
> On 05/12/2025 10:43, Konrad Dybcio wrote:
>> On 12/4/25 5:32 PM, David Heidelberg via B4 Relay wrote:
>>> From: David Heidelberg <david@ixit.cz>
>>>
>>> Inherit C-PHY information from CSIPHY, so we can configure CSID
>>> properly.
>>>
>>> CSI2_RX_CFG0_PHY_TYPE_SEL must be set to 1, when C-PHY mode is used.
>>>
>>> Signed-off-by: David Heidelberg <david@ixit.cz>
>>> ---
>>>   drivers/media/platform/qcom/camss/camss-csid-gen2.c | 1 +
>>>   drivers/media/platform/qcom/camss/camss-csid.c      | 1 +
>>>   drivers/media/platform/qcom/camss/camss-csid.h      | 1 +
>>>   3 files changed, 3 insertions(+)
>>>
>>> diff --git a/drivers/media/platform/qcom/camss/camss-csid-gen2.c b/drivers/media/platform/qcom/camss/camss-csid-gen2.c
>>> index 2a1746dcc1c5b..033036ae28a4f 100644
>>> --- a/drivers/media/platform/qcom/camss/camss-csid-gen2.c
>>> +++ b/drivers/media/platform/qcom/camss/camss-csid-gen2.c
>>> @@ -183,6 +183,7 @@ static void __csid_configure_rx(struct csid_device *csid,
>>>       val = (lane_cnt - 1) << CSI2_RX_CFG0_NUM_ACTIVE_LANES;
>>>       val |= phy->lane_assign << CSI2_RX_CFG0_DL0_INPUT_SEL;
>>>       val |= phy->csiphy_id << CSI2_RX_CFG0_PHY_NUM_SEL;
>>> +    val |= csid->phy.cphy << CSI2_RX_CFG0_PHY_TYPE_SEL;
>>
>> This field is 1-wide, this would be neater:
>>
>> if (csid->phy.cphy)
>>     val |= BIT(CSI2_RX_CFG0_PHY_TYPE_SEL);
> 
> Hello Konrad,
> 
> while your change make sense as we work with 1-bit.
> On other hand, due to TYPE_SEL naming, it's not very explicit why we set this bit when cphy is on.

This is the actual name of the register field

> 
> Maybe I could propose renaming CSI2_RX_CFG0_PHY_TYPE_SEL to CSI2_RX_CFG0_PHY_TYPE_SEL_CPHY, then setting 1 to it would make sense.
> 
> Most clean solution to me would be something like
> 
> #define TYPE_SEL_DPHY    0
> #define TYPE_SEL_CPHY    1
> 
> val |= (csid->phy.cphy ? TYPE_SEL_CPHY : TYPE_SEL_DPHY) << CSI2_RX_CFG0_PHY_TYPE_SEL
> 
> Do I overthinking this? What do you think?

Perhaps just:

/* Set the PHY_TYPE_SEL bit to enable C-PHY mode */
if (csid->phy.cphy)
	val |= BIT(CSI2_RX_CFG0_PHY_TYPE_SEL);

?

Konrad