Re: [PATCH V22 00/22] Add support UHS-II for GL9755 and GL9767

[Adrian Hunter <adrian.hunter@intel.com>]

On 13/09/24 13:28, Victor Shih wrote:
> From: Victor Shih <victor.shih@genesyslogic.com.tw>
> 
> Summary
> =======
> These patches[1] support UHS-II and fix GL9755 and GL9767
> UHS-II compatibility.
> 
> About UHS-II, roughly deal with the following three parts:
> 1) A UHS-II detection and initialization:
> - Host setup to support UHS-II (Section 3.13.1 Host Controller Setup
>   Sequence[2]).
> - Detect a UHS-II I/F (Section 3.13.2 Card Interface Detection Sequence
>   [2]).
> - In step(9) of Section 3.13.2 in [2], UHS-II initialization is include
>   Section 3.13.3 UHS-II Card Initialization and Section 3.13.4 UHS-II
>   Setting Register Setup Sequence.
> 
> 2) Send Legacy SD command through SD-TRAN
> - Encapsulated SD packets are defined in SD-TRAN in order to ensure Legacy
>   SD compatibility and preserve Legacy SD infrastructures (Section 7.1.1
>   Packet Types and Format Overview[3]).
> - Host issue a UHS-II CCMD packet or a UHS-II DCMD (Section 3.13.5 UHS-II
>   CCMD Packet issuing and Section 3.13.6 UHS-II DCMD Packet issuing[2]).
> 
> 3) UHS-II Interrupt
> - Except for UHS-II error interrupts, most interrupts share the original
>   interrupt registers.
> 
> Patch structure
> ===============
> patch#1-#7:  for core
> patch#8-#20: for sdhci
> patch#21:    for GL9755
> patch#22:    for GL9767
> 
> Tests
> =====
> Ran 'dd' command to evaluate the performance 3 times:
> (SanDisk UHS-II card on GL9755 controller)
>                              Read    Write
> UHS-II disabled (UHS-I): 85.5MB/s 56.3MB/s
> UHS-II enabled         :  182MB/s 75.5MB/s
>                              Read    Write
> UHS-II disabled (UHS-I): 86.7MB/s 52.1MB/s
> UHS-II enabled         :  179MB/s 77.6MB/s
>                              Read    Write
> UHS-II disabled (UHS-I): 85.8MB/s 49.1MB/s
> UHS-II enabled         :  181MB/s 89.8MB/s
> (SanDisk UHS-II card on GL9767 controller)
>                              Read    Write
> UHS-II disabled (UHS-I): 81.9MB/s 49.0MB/s
> UHS-II enabled         :  186MB/s 87.9MB/s
>                              Read    Write
> UHS-II disabled (UHS-I): 80.8MB/s 53.5MB/s
> UHS-II enabled         :  192MB/s 87.3MB/s
>                              Read    Write
> UHS-II disabled (UHS-I): 81.0MB/s 53.9MB/s
> UHS-II enabled         :  199MB/s 73.6MB/s
> 
> Test command
> =====
> Read: dd if=/dev/mmcxxx of=/dev/null bs=4096k count=2000 iflag=direct
> Write:dd if=/dev/zero of=/dev/mmcxxx bs=4096k count=2000 oflag=direct
> 
> Changes in v22 (September. 13, 2024)
> * Rebase on latest mmc/next.
> * Adjust patch order to avoid defined but nt used warnings:
>   v21 patch#18 to v22 patch#14.
>   v21 patch#14 to v22 patch#15.
>   v21 patch#15 to v22 patch#16.
>   v21 patch#16 to v22 patch#18.
> * Patch#14: Remove unnecessary code to avoid defined but not used warnings.
> * Patch#15: Add necessary code to avoid defined but not used warnings.
> * Patch#16: Remove unnecessary code to avoid defined but not used warnings.
>             Modify commit message.
> * Patch#17: Remove unnecessary code to avoid defined but not used warnings.
> * Patch#18: Add necessary code to avoid defined but not used warnings.

For SDHCI:

Acked-by: Adrian Hunter <adrian.hunter@intel.com>