* [PATCH 1/2] x86/cpufeatures: Put the AMX macros in the word 18 block
@ 2022-02-03 19:43 Jim Mattson
2022-02-03 19:43 ` [PATCH 2/2] x86/cpufeatures: Add macros for Intel's new fast rep string features Jim Mattson
` (2 more replies)
0 siblings, 3 replies; 6+ messages in thread
From: Jim Mattson @ 2022-02-03 19:43 UTC (permalink / raw)
To: Thomas Gleixner, Ingo Molnar, Borislav Petkov, Dave Hansen, x86,
H. Peter Anvin, Paolo Bonzini, Tony Luck, Peter Zijlstra,
Chang S. Bae, Jim Mattson, Juergen Gross, Andrew Cooper,
Babu Moger, Jing Liu, Sean Christopherson, linux-kernel
These macros are for bits in CPUID.(EAX=7,ECX=0):EDX, not for bits in
CPUID(EAX=7,ECX=1):EAX. Put them with their brethren.
Signed-off-by: Jim Mattson <jmattson@google.com>
---
arch/x86/include/asm/cpufeatures.h | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h
index da872b6f8d8b..d7b51ddc8db3 100644
--- a/arch/x86/include/asm/cpufeatures.h
+++ b/arch/x86/include/asm/cpufeatures.h
@@ -299,9 +299,6 @@
/* Intel-defined CPU features, CPUID level 0x00000007:1 (EAX), word 12 */
#define X86_FEATURE_AVX_VNNI (12*32+ 4) /* AVX VNNI instructions */
#define X86_FEATURE_AVX512_BF16 (12*32+ 5) /* AVX512 BFLOAT16 instructions */
-#define X86_FEATURE_AMX_BF16 (18*32+22) /* AMX bf16 Support */
-#define X86_FEATURE_AMX_TILE (18*32+24) /* AMX tile Support */
-#define X86_FEATURE_AMX_INT8 (18*32+25) /* AMX int8 Support */
/* AMD-defined CPU features, CPUID level 0x80000008 (EBX), word 13 */
#define X86_FEATURE_CLZERO (13*32+ 0) /* CLZERO instruction */
@@ -391,6 +388,9 @@
#define X86_FEATURE_ARCH_LBR (18*32+19) /* Intel ARCH LBR */
#define X86_FEATURE_AVX512_FP16 (18*32+23) /* AVX512 FP16 */
#define X86_FEATURE_SPEC_CTRL (18*32+26) /* "" Speculation Control (IBRS + IBPB) */
+#define X86_FEATURE_AMX_BF16 (18*32+22) /* AMX bf16 Support */
+#define X86_FEATURE_AMX_TILE (18*32+24) /* AMX tile Support */
+#define X86_FEATURE_AMX_INT8 (18*32+25) /* AMX int8 Support */
#define X86_FEATURE_INTEL_STIBP (18*32+27) /* "" Single Thread Indirect Branch Predictors */
#define X86_FEATURE_FLUSH_L1D (18*32+28) /* Flush L1D cache */
#define X86_FEATURE_ARCH_CAPABILITIES (18*32+29) /* IA32_ARCH_CAPABILITIES MSR (Intel) */
--
2.35.0.263.gb82422642f-goog
^ permalink raw reply [flat|nested] 6+ messages in thread* [PATCH 2/2] x86/cpufeatures: Add macros for Intel's new fast rep string features
2022-02-03 19:43 [PATCH 1/2] x86/cpufeatures: Put the AMX macros in the word 18 block Jim Mattson
@ 2022-02-03 19:43 ` Jim Mattson
2022-02-03 20:25 ` Dave Hansen
2022-02-03 20:27 ` [tip: x86/cpu] x86/cpufeatures: Put the AMX macros in the word 18 block tip-bot2 for Jim Mattson
2022-02-08 9:54 ` tip-bot2 for Jim Mattson
2 siblings, 1 reply; 6+ messages in thread
From: Jim Mattson @ 2022-02-03 19:43 UTC (permalink / raw)
To: Thomas Gleixner, Ingo Molnar, Borislav Petkov, Dave Hansen, x86,
H. Peter Anvin, Paolo Bonzini, Tony Luck, Peter Zijlstra,
Chang S. Bae, Jim Mattson, Juergen Gross, Andrew Cooper,
Babu Moger, Jing Liu, Sean Christopherson, linux-kernel
Even if no one else cares, these features should be exposed to kvm
guests, and the code for the KVM_GET_SUPPORTED_CPUID ioctl is more
readable if the bits have corresponding X86_FEATURE macros.
Signed-off-by: Jim Mattson <jmattson@google.com>
---
arch/x86/include/asm/cpufeatures.h | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h
index d7b51ddc8db3..138a50bc7bbd 100644
--- a/arch/x86/include/asm/cpufeatures.h
+++ b/arch/x86/include/asm/cpufeatures.h
@@ -299,6 +299,9 @@
/* Intel-defined CPU features, CPUID level 0x00000007:1 (EAX), word 12 */
#define X86_FEATURE_AVX_VNNI (12*32+ 4) /* AVX VNNI instructions */
#define X86_FEATURE_AVX512_BF16 (12*32+ 5) /* AVX512 BFLOAT16 instructions */
+#define X86_FEATURE_FZRM (12*32+10) /* Fast zero-length REP MOVSB */
+#define X86_FEATURE_FSRS (12*32+11) /* Fast short REP STOSB */
+#define X86_FEATURE_FSRC (12*32+12) /* Fast short REP {CMPSB,SCASB} */
/* AMD-defined CPU features, CPUID level 0x80000008 (EBX), word 13 */
#define X86_FEATURE_CLZERO (13*32+ 0) /* CLZERO instruction */
--
2.35.0.263.gb82422642f-goog
^ permalink raw reply [flat|nested] 6+ messages in thread* Re: [PATCH 2/2] x86/cpufeatures: Add macros for Intel's new fast rep string features
2022-02-03 19:43 ` [PATCH 2/2] x86/cpufeatures: Add macros for Intel's new fast rep string features Jim Mattson
@ 2022-02-03 20:25 ` Dave Hansen
2022-02-03 20:50 ` Jim Mattson
0 siblings, 1 reply; 6+ messages in thread
From: Dave Hansen @ 2022-02-03 20:25 UTC (permalink / raw)
To: Jim Mattson, Thomas Gleixner, Ingo Molnar, Borislav Petkov,
Dave Hansen, x86, H. Peter Anvin, Paolo Bonzini, Tony Luck,
Peter Zijlstra, Chang S. Bae, Juergen Gross, Andrew Cooper,
Babu Moger, Jing Liu, Sean Christopherson, linux-kernel
On 2/3/22 11:43, Jim Mattson wrote:
> Even if no one else cares, these features should be exposed to kvm
> guests, and the code for the KVM_GET_SUPPORTED_CPUID ioctl is more
> readable if the bits have corresponding X86_FEATURE macros.
I went digging around KVM_GET_SUPPORTED_CPUID and didn't see any obvious
unreadable things resulting from not having these defines. Maybe I'm
looking in the wrong spot. Do you have a slightly more specific pointer?
> +#define X86_FEATURE_FZRM (12*32+10) /* Fast zero-length REP MOVSB */
> +#define X86_FEATURE_FSRS (12*32+11) /* Fast short REP STOSB */
> +#define X86_FEATURE_FSRC (12*32+12) /* Fast short REP {CMPSB,SCASB} */
If the use really is for inside the kernel, maybe we should hide them
from cpuinfo:
#define X86_FEATURE_FSRC (12*32+12) /* "" Fast short REP {CMPSB,SCASB} */
^ permalink raw reply [flat|nested] 6+ messages in thread* Re: [PATCH 2/2] x86/cpufeatures: Add macros for Intel's new fast rep string features
2022-02-03 20:25 ` Dave Hansen
@ 2022-02-03 20:50 ` Jim Mattson
0 siblings, 0 replies; 6+ messages in thread
From: Jim Mattson @ 2022-02-03 20:50 UTC (permalink / raw)
To: Dave Hansen
Cc: Thomas Gleixner, Ingo Molnar, Borislav Petkov, Dave Hansen, x86,
H. Peter Anvin, Paolo Bonzini, Tony Luck, Peter Zijlstra,
Chang S. Bae, Juergen Gross, Andrew Cooper, Babu Moger, Jing Liu,
Sean Christopherson, linux-kernel
On Thu, Feb 3, 2022 at 12:25 PM Dave Hansen <dave.hansen@intel.com> wrote:
>
> On 2/3/22 11:43, Jim Mattson wrote:
> > Even if no one else cares, these features should be exposed to kvm
> > guests, and the code for the KVM_GET_SUPPORTED_CPUID ioctl is more
> > readable if the bits have corresponding X86_FEATURE macros.
>
> I went digging around KVM_GET_SUPPORTED_CPUID and didn't see any obvious
> unreadable things resulting from not having these defines. Maybe I'm
> looking in the wrong spot. Do you have a slightly more specific pointer?
These features are not currently enumerated by
KVM_GET_SUPPORTED_CPUID. They would be added as follows [gmail mangles
diffs; sorry]:
diff --git a/arch/x86/kvm/cpuid.c b/arch/x86/kvm/cpuid.c
index 28be02adc669..11e621b6faac 100644
--- a/arch/x86/kvm/cpuid.c
+++ b/arch/x86/kvm/cpuid.c
@@ -599,7 +599,7 @@ void kvm_set_cpu_caps(void)
kvm_cpu_cap_set(X86_FEATURE_SPEC_CTRL_SSBD);
kvm_cpu_cap_mask(CPUID_7_1_EAX,
- F(AVX_VNNI) | F(AVX512_BF16)
+ F(AVX_VNNI) | F(AVX512_BF16) | F(FZRM) | F(FSRS) | F(FSRC)
);
kvm_cpu_cap_mask(CPUID_D_1_EAX,
(Of course, we can always define these macros in that file, if that's
preferable.)
> > +#define X86_FEATURE_FZRM (12*32+10) /* Fast zero-length REP MOVSB */
> > +#define X86_FEATURE_FSRS (12*32+11) /* Fast short REP STOSB */
> > +#define X86_FEATURE_FSRC (12*32+12) /* Fast short REP {CMPSB,SCASB} */
>
> If the use really is for inside the kernel, maybe we should hide them
> from cpuinfo:
>
> #define X86_FEATURE_FSRC (12*32+12) /* "" Fast short REP {CMPSB,SCASB} */
That sounds good to me.
^ permalink raw reply [flat|nested] 6+ messages in thread
* [tip: x86/cpu] x86/cpufeatures: Put the AMX macros in the word 18 block
2022-02-03 19:43 [PATCH 1/2] x86/cpufeatures: Put the AMX macros in the word 18 block Jim Mattson
2022-02-03 19:43 ` [PATCH 2/2] x86/cpufeatures: Add macros for Intel's new fast rep string features Jim Mattson
@ 2022-02-03 20:27 ` tip-bot2 for Jim Mattson
2022-02-08 9:54 ` tip-bot2 for Jim Mattson
2 siblings, 0 replies; 6+ messages in thread
From: tip-bot2 for Jim Mattson @ 2022-02-03 20:27 UTC (permalink / raw)
To: linux-tip-commits; +Cc: Jim Mattson, Dave Hansen, x86, linux-kernel
The following commit has been merged into the x86/cpu branch of tip:
Commit-ID: ae75fa54228162ecd65341f9780886f21f557cc4
Gitweb: https://git.kernel.org/tip/ae75fa54228162ecd65341f9780886f21f557cc4
Author: Jim Mattson <jmattson@google.com>
AuthorDate: Thu, 03 Feb 2022 11:43:07 -08:00
Committer: Dave Hansen <dave.hansen@linux.intel.com>
CommitterDate: Thu, 03 Feb 2022 12:19:39 -08:00
x86/cpufeatures: Put the AMX macros in the word 18 block
These macros are for bits in CPUID.(EAX=7,ECX=0):EDX, not for bits in
CPUID(EAX=7,ECX=1):EAX. Put them with their brethren.
Signed-off-by: Jim Mattson <jmattson@google.com>
Signed-off-by: Dave Hansen <dave.hansen@linux.intel.com>
Link: https://lkml.kernel.org/r/20220203194308.2469117-1-jmattson@google.com
---
arch/x86/include/asm/cpufeatures.h | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h
index 6db4e29..4cc0ef9 100644
--- a/arch/x86/include/asm/cpufeatures.h
+++ b/arch/x86/include/asm/cpufeatures.h
@@ -299,9 +299,6 @@
/* Intel-defined CPU features, CPUID level 0x00000007:1 (EAX), word 12 */
#define X86_FEATURE_AVX_VNNI (12*32+ 4) /* AVX VNNI instructions */
#define X86_FEATURE_AVX512_BF16 (12*32+ 5) /* AVX512 BFLOAT16 instructions */
-#define X86_FEATURE_AMX_BF16 (18*32+22) /* AMX bf16 Support */
-#define X86_FEATURE_AMX_TILE (18*32+24) /* AMX tile Support */
-#define X86_FEATURE_AMX_INT8 (18*32+25) /* AMX int8 Support */
/* AMD-defined CPU features, CPUID level 0x80000008 (EBX), word 13 */
#define X86_FEATURE_CLZERO (13*32+ 0) /* CLZERO instruction */
@@ -392,6 +389,9 @@
#define X86_FEATURE_ARCH_LBR (18*32+19) /* Intel ARCH LBR */
#define X86_FEATURE_AVX512_FP16 (18*32+23) /* AVX512 FP16 */
#define X86_FEATURE_SPEC_CTRL (18*32+26) /* "" Speculation Control (IBRS + IBPB) */
+#define X86_FEATURE_AMX_BF16 (18*32+22) /* AMX bf16 Support */
+#define X86_FEATURE_AMX_TILE (18*32+24) /* AMX tile Support */
+#define X86_FEATURE_AMX_INT8 (18*32+25) /* AMX int8 Support */
#define X86_FEATURE_INTEL_STIBP (18*32+27) /* "" Single Thread Indirect Branch Predictors */
#define X86_FEATURE_FLUSH_L1D (18*32+28) /* Flush L1D cache */
#define X86_FEATURE_ARCH_CAPABILITIES (18*32+29) /* IA32_ARCH_CAPABILITIES MSR (Intel) */
^ permalink raw reply [flat|nested] 6+ messages in thread
* [tip: x86/cpu] x86/cpufeatures: Put the AMX macros in the word 18 block
2022-02-03 19:43 [PATCH 1/2] x86/cpufeatures: Put the AMX macros in the word 18 block Jim Mattson
2022-02-03 19:43 ` [PATCH 2/2] x86/cpufeatures: Add macros for Intel's new fast rep string features Jim Mattson
2022-02-03 20:27 ` [tip: x86/cpu] x86/cpufeatures: Put the AMX macros in the word 18 block tip-bot2 for Jim Mattson
@ 2022-02-08 9:54 ` tip-bot2 for Jim Mattson
2 siblings, 0 replies; 6+ messages in thread
From: tip-bot2 for Jim Mattson @ 2022-02-08 9:54 UTC (permalink / raw)
To: linux-tip-commits
Cc: Jim Mattson, Dave Hansen, Borislav Petkov, x86, linux-kernel
The following commit has been merged into the x86/cpu branch of tip:
Commit-ID: fa31a4d669bd471e9510db1abf9b91e1a6be6ff7
Gitweb: https://git.kernel.org/tip/fa31a4d669bd471e9510db1abf9b91e1a6be6ff7
Author: Jim Mattson <jmattson@google.com>
AuthorDate: Thu, 03 Feb 2022 11:43:07 -08:00
Committer: Borislav Petkov <bp@suse.de>
CommitterDate: Tue, 08 Feb 2022 10:23:35 +01:00
x86/cpufeatures: Put the AMX macros in the word 18 block
These macros are for bits in CPUID.(EAX=7,ECX=0):EDX, not for bits in
CPUID(EAX=7,ECX=1):EAX. Put them with their brethren.
[ bp: Sort word 18 bits properly, as caught by Like Xu
<like.xu.linux@gmail.com> ]
Signed-off-by: Jim Mattson <jmattson@google.com>
Signed-off-by: Dave Hansen <dave.hansen@linux.intel.com>
Signed-off-by: Borislav Petkov <bp@suse.de>
Link: https://lkml.kernel.org/r/20220203194308.2469117-1-jmattson@google.com
---
arch/x86/include/asm/cpufeatures.h | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h
index 6db4e29..5cd2209 100644
--- a/arch/x86/include/asm/cpufeatures.h
+++ b/arch/x86/include/asm/cpufeatures.h
@@ -299,9 +299,6 @@
/* Intel-defined CPU features, CPUID level 0x00000007:1 (EAX), word 12 */
#define X86_FEATURE_AVX_VNNI (12*32+ 4) /* AVX VNNI instructions */
#define X86_FEATURE_AVX512_BF16 (12*32+ 5) /* AVX512 BFLOAT16 instructions */
-#define X86_FEATURE_AMX_BF16 (18*32+22) /* AMX bf16 Support */
-#define X86_FEATURE_AMX_TILE (18*32+24) /* AMX tile Support */
-#define X86_FEATURE_AMX_INT8 (18*32+25) /* AMX int8 Support */
/* AMD-defined CPU features, CPUID level 0x80000008 (EBX), word 13 */
#define X86_FEATURE_CLZERO (13*32+ 0) /* CLZERO instruction */
@@ -390,7 +387,10 @@
#define X86_FEATURE_TSXLDTRK (18*32+16) /* TSX Suspend Load Address Tracking */
#define X86_FEATURE_PCONFIG (18*32+18) /* Intel PCONFIG */
#define X86_FEATURE_ARCH_LBR (18*32+19) /* Intel ARCH LBR */
+#define X86_FEATURE_AMX_BF16 (18*32+22) /* AMX bf16 Support */
#define X86_FEATURE_AVX512_FP16 (18*32+23) /* AVX512 FP16 */
+#define X86_FEATURE_AMX_TILE (18*32+24) /* AMX tile Support */
+#define X86_FEATURE_AMX_INT8 (18*32+25) /* AMX int8 Support */
#define X86_FEATURE_SPEC_CTRL (18*32+26) /* "" Speculation Control (IBRS + IBPB) */
#define X86_FEATURE_INTEL_STIBP (18*32+27) /* "" Single Thread Indirect Branch Predictors */
#define X86_FEATURE_FLUSH_L1D (18*32+28) /* Flush L1D cache */
^ permalink raw reply [flat|nested] 6+ messages in thread
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