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* [PATCH v2 1/2] x86/cpufeatures: Add virtual TSC_AUX feature bit
@ 2022-04-19 20:53 Babu Moger
  2022-04-19 20:54 ` [PATCH v2 2/2] KVM: SVM: Disable RDTSCP and TSC_AUX MSR intercepts when V_TSC_AUX is present Babu Moger
                   ` (2 more replies)
  0 siblings, 3 replies; 5+ messages in thread
From: Babu Moger @ 2022-04-19 20:53 UTC (permalink / raw)
  To: tglx, mingo, bp, dave.hansen, hpa, pbonzini, seanjc
  Cc: vkuznets, jmattson, joro, wanpengli, joro, babu.moger,
	linux-kernel, kvm, x86

The TSC_AUX Virtualization feature allows AMD SEV-ES guests to securely use
TSC_AUX (auxiliary time stamp counter data) MSR in RDTSCP and RDPID
instructions.

The TSC_AUX MSR is typically initialized to APIC ID or another unique
identifier so that software can quickly associate returned TSC value
with the logical processor.

Add the feature bit and also include it in the kvm for detection.

Signed-off-by: Babu Moger <babu.moger@amd.com>
Acked-by: Borislav Petkov <bp@suse.de>
---
v2:
Fixed the text(commented by Boris).
Added Acked-by from Boris.

v1:
https://lore.kernel.org/kvm/164937947020.1047063.14919887750944564032.stgit@bmoger-ubuntu/

 arch/x86/include/asm/cpufeatures.h |    1 +
 arch/x86/kvm/cpuid.c               |    2 +-
 2 files changed, 2 insertions(+), 1 deletion(-)

diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h
index 73e643ae94b6..1bc66a17a95a 100644
--- a/arch/x86/include/asm/cpufeatures.h
+++ b/arch/x86/include/asm/cpufeatures.h
@@ -405,6 +405,7 @@
 #define X86_FEATURE_SEV			(19*32+ 1) /* AMD Secure Encrypted Virtualization */
 #define X86_FEATURE_VM_PAGE_FLUSH	(19*32+ 2) /* "" VM Page Flush MSR is supported */
 #define X86_FEATURE_SEV_ES		(19*32+ 3) /* AMD Secure Encrypted Virtualization - Encrypted State */
+#define X86_FEATURE_V_TSC_AUX		(19*32+ 9) /* Virtual TSC_AUX */
 #define X86_FEATURE_SME_COHERENT	(19*32+10) /* "" AMD hardware-enforced cache coherency */
 
 /*
diff --git a/arch/x86/kvm/cpuid.c b/arch/x86/kvm/cpuid.c
index b24ca7f4ed7c..99a4c078b397 100644
--- a/arch/x86/kvm/cpuid.c
+++ b/arch/x86/kvm/cpuid.c
@@ -674,7 +674,7 @@ void kvm_set_cpu_caps(void)
 
 	kvm_cpu_cap_mask(CPUID_8000_001F_EAX,
 		0 /* SME */ | F(SEV) | 0 /* VM_PAGE_FLUSH */ | F(SEV_ES) |
-		F(SME_COHERENT));
+		F(V_TSC_AUX) | F(SME_COHERENT));
 
 	kvm_cpu_cap_mask(CPUID_C000_0001_EDX,
 		F(XSTORE) | F(XSTORE_EN) | F(XCRYPT) | F(XCRYPT_EN) |



^ permalink raw reply	[flat|nested] 5+ messages in thread

end of thread, other threads:[~2022-04-20 16:27 UTC | newest]

Thread overview: 5+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-04-19 20:53 [PATCH v2 1/2] x86/cpufeatures: Add virtual TSC_AUX feature bit Babu Moger
2022-04-19 20:54 ` [PATCH v2 2/2] KVM: SVM: Disable RDTSCP and TSC_AUX MSR intercepts when V_TSC_AUX is present Babu Moger
2022-04-20 11:43 ` [PATCH v2 1/2] x86/cpufeatures: Add virtual TSC_AUX feature bit Borislav Petkov
2022-04-20 15:02   ` Moger, Babu
2022-04-20 16:27 ` Paolo Bonzini

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