[PATCH v2 0/2] Enable Display Port for Qualcomm SA8775P-ride platform

[PATCH v2 0/2] Enable Display Port for Qualcomm SA8775P-ride platform

[Soutrik Mukhopadhyay]

This series adds the DPTX0 and DPTX1 nodes, as a part of mdss0
on Qualcomm SA8775P SoC. It also enables Display Port on Qualcomm
SA8775P-ride platform.

---
This patch depends on following series:
https://lore.kernel.org/all/20240816-sa8775p-mm-v3-v1-0-77d53c3c0cef@quicinc.com/
https://lore.kernel.org/all/20241001-patchv3_1-v3-0-d23284f45977@quicinc.com/
https://lore.kernel.org/all/20241004103046.22209-1-quic_mukhopad@quicinc.com/
Link to v1: https://lore.kernel.org/all/20240916091344.27607-1-quic_mukhopad@quicinc.com/

v2: Fixed review comments from Dmitry, Konrad and Bjorn
	- Added a new patchset to separate out the soc and board parts.[Konrad]
	- Patchset 1 now comprises of the soc parts and patchset 2 includes board specific changes.[Bjorn]
	- Patchset 2 enables all the DP ports validated on the sa8775p-ride platform.[Bjorn]
	- Fixed indentation errors in the dtsi file containing the soc information.[Dmitry][Konrad]
	- Updated clocks to be used by respective PHYs.[Dmitry]
	- Added mdss0_dp1 device node.[Dmitry]
	- Updated the names of PHYs using label prefix "mdssM_dpN" for clarity.[Bjorn]
	- Avoided use of referring any label in the board(dts) file in the dtsi(platform) file.[Bjorn]

---

Soutrik Mukhopadhyay (2):
  arm64: dts: qcom: sa8775p: add DisplayPort device nodes
  arm64: dts: qcom: sa8775p-ride: Enable Display Port

 arch/arm64/boot/dts/qcom/sa8775p-ride.dtsi |  54 ++++++
 arch/arm64/boot/dts/qcom/sa8775p.dtsi      | 216 ++++++++++++++++++++-
 2 files changed, 269 insertions(+), 1 deletion(-)

-- 
2.17.1

[PATCH v2 1/2] arm64: dts: qcom: sa8775p: add DisplayPort device nodes

[Soutrik Mukhopadhyay]

Add device tree nodes for the DPTX0 and DPTX1 controllers
with their corresponding PHYs found on Qualcomm SA8775P SoC.

Signed-off-by: Soutrik Mukhopadhyay <quic_mukhopad@quicinc.com>
---
 arch/arm64/boot/dts/qcom/sa8775p.dtsi | 216 +++++++++++++++++++++++++-
 1 file changed, 215 insertions(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi
index 0bf1112a0adb..3b02a80da197 100644
--- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi
+++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi
@@ -3343,6 +3343,25 @@
 				interrupt-parent = <&mdss0>;
 				interrupts = <0>;
 
+				ports {
+					#address-cells = <1>;
+					#size-cells = <0>;
+
+					port@0 {
+						reg = <0>;
+						dpu_intf0_out: endpoint {
+							remote-endpoint = <&mdss0_dp0_in>;
+						};
+					};
+
+					port@1 {
+						reg = <0>;
+						dpu_intf4_out: endpoint {
+							remote-endpoint = <&mdss0_dp1_in>;
+						};
+					};
+				};
+
 				mdss0_mdp_opp_table: opp-table {
 					compatible = "operating-points-v2";
 
@@ -3367,6 +3386,200 @@
 					};
 				};
 			};
+
+			mdss0_dp0_phy: phy@aec2a00 {
+				compatible = "qcom,sa8775p-edp-phy";
+
+				reg = <0x0 0xaec2a00 0x0 0x200>,
+				      <0x0 0xaec2200 0x0 0xd0>,
+				      <0x0 0xaec2600 0x0 0xd0>,
+				      <0x0 0xaec2000 0x0 0x1c8>;
+
+				clocks =<&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_AUX_CLK>,
+					<&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>;
+				clock-names = "aux",
+					      "cfg_ahb";
+
+				#clock-cells = <1>;
+				#phy-cells = <0>;
+
+				status = "disabled";
+			};
+
+			mdss0_dp1_phy: phy@aec5a00 {
+				compatible = "qcom,sa8775p-edp-phy";
+
+				reg = <0 0xaec5a00 0 0x200>,
+				      <0 0xaec5200 0 0xd0>,
+				      <0 0xaec5600 0 0xd0>,
+				      <0 0xaec5000 0 0x1c8>;
+
+				clocks =<&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_AUX_CLK>,
+					<&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>;
+				clock-names = "aux",
+					      "cfg_ahb";
+
+				#clock-cells = <1>;
+				#phy-cells = <0>;
+
+				status = "disabled";
+			};
+
+			mdss0_dp0: displayport-controller@af54000 {
+				compatible = "qcom,sa8775p-dp";
+
+				reg = <0x0 0xaf54000 0x0 0x104>,
+				      <0x0 0xaf54200 0x0 0x0c0>,
+				      <0x0 0xaf55000 0x0 0x770>,
+				      <0x0 0xaf56000 0x0 0x09c>;
+
+				interrupt-parent = <&mdss0>;
+				interrupts = <12>;
+
+				clocks = <&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>,
+					 <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_AUX_CLK>,
+					 <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_LINK_CLK>,
+					 <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>,
+					 <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL0_CLK>;
+				clock-names = "core_iface",
+					      "core_aux",
+					      "ctrl_link",
+					      "ctrl_link_iface",
+					      "stream_pixel";
+				assigned-clocks = <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>,
+						  <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>;
+				assigned-clock-parents = <&mdss0_dp0_phy 0>, <&mdss0_dp0_phy 1>;
+				phys = <&mdss0_dp0_phy>;
+				phy-names = "dp";
+
+				operating-points-v2 = <&dp_opp_table>;
+				power-domains = <&rpmhpd SA8775P_MMCX>;
+
+				#sound-dai-cells = <0>;
+
+				status = "disabled";
+
+				ports {
+					#address-cells = <1>;
+					#size-cells = <0>;
+
+					port@0 {
+						reg = <0>;
+
+						mdss0_dp0_in: endpoint {
+							remote-endpoint = <&dpu_intf0_out>;
+						};
+					};
+
+					port@1 {
+						reg = <1>;
+
+						mdss0_dp0_out: endpoint { };
+					};
+				};
+
+				dp_opp_table: opp-table {
+					compatible = "operating-points-v2";
+
+					opp-160000000 {
+						opp-hz = /bits/ 64 <160000000>;
+						required-opps = <&rpmhpd_opp_low_svs>;
+					};
+
+					opp-270000000 {
+						opp-hz = /bits/ 64 <270000000>;
+						required-opps = <&rpmhpd_opp_svs>;
+					};
+
+					opp-540000000 {
+						opp-hz = /bits/ 64 <540000000>;
+						required-opps = <&rpmhpd_opp_svs_l1>;
+					};
+
+					opp-810000000 {
+						opp-hz = /bits/ 64 <810000000>;
+						required-opps = <&rpmhpd_opp_nom>;
+					};
+				};
+			};
+
+			mdss0_dp1: displayport-controller@af5c000 {
+				compatible = "qcom,sa8775p-dp";
+
+				reg = <0 0xaf5c000 0 0x104>,
+				      <0 0xaf5c200 0 0x0c0>,
+				      <0 0xaf5d000 0 0x770>,
+				      <0 0xaf5e000 0 0x09c>;
+
+				interrupt-parent = <&mdss0>;
+				interrupts = <13>;
+
+				clocks = <&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>,
+					 <&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_AUX_CLK>,
+					 <&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_LINK_CLK>,
+					 <&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_LINK_INTF_CLK>,
+					 <&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_PIXEL0_CLK>;
+				clock-names = "core_iface",
+					      "core_aux",
+					      "ctrl_link",
+					      "ctrl_link_iface",
+					      "stream_pixel";
+				assigned-clocks = <&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_LINK_CLK_SRC>,
+						  <&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC>;
+				assigned-clock-parents = <&mdss0_dp1_phy 0>, <&mdss0_dp1_phy 1>;
+				phys = <&mdss0_dp1_phy>;
+				phy-names = "dp";
+
+				operating-points-v2 = <&dp1_opp_table>;
+				power-domains = <&rpmhpd SA8775P_MMCX>;
+
+				#sound-dai-cells = <0>;
+
+				status = "disabled";
+
+				ports {
+					#address-cells = <1>;
+					#size-cells = <0>;
+
+					port@0 {
+						reg = <0>;
+
+						mdss0_dp1_in: endpoint {
+							remote-endpoint = <&dpu_intf4_out>;
+						};
+					};
+
+					port@1 {
+						reg = <1>;
+
+						mdss0_dp1_out: endpoint { };
+					};
+				};
+
+				dp1_opp_table: opp-table {
+					compatible = "operating-points-v2";
+
+					opp-160000000 {
+						opp-hz = /bits/ 64 <160000000>;
+						required-opps = <&rpmhpd_opp_low_svs>;
+					};
+
+					opp-270000000 {
+						opp-hz = /bits/ 64 <270000000>;
+						required-opps = <&rpmhpd_opp_svs>;
+					};
+
+					opp-540000000 {
+						opp-hz = /bits/ 64 <540000000>;
+						required-opps = <&rpmhpd_opp_svs_l1>;
+					};
+
+					opp-810000000 {
+						opp-hz = /bits/ 64 <810000000>;
+						required-opps = <&rpmhpd_opp_nom>;
+					};
+				};
+			};
 		};
 
 		dispcc0: clock-controller@af00000 {
@@ -3376,7 +3589,8 @@
 				 <&rpmhcc RPMH_CXO_CLK>,
 				 <&rpmhcc RPMH_CXO_CLK_A>,
 				 <&sleep_clk>,
-				 <0>, <0>, <0>, <0>,
+				 <&mdss0_dp0_phy 0>, <&mdss0_dp0_phy 1>,
+				 <&mdss0_dp1_phy 0>, <&mdss0_dp1_phy 1>,
 				 <0>, <0>, <0>, <0>;
 			power-domains = <&rpmhpd SA8775P_MMCX>;
 			#clock-cells = <1>;
-- 
2.17.1

[PATCH v2 2/2] arm64: dts: qcom: sa8775p-ride: Enable Display Port

[Soutrik Mukhopadhyay]

Enable DPTX0 and DPTX1 along with their corresponding PHYs for
sa8775p-ride platform.

Signed-off-by: Soutrik Mukhopadhyay <quic_mukhopad@quicinc.com>
---
 arch/arm64/boot/dts/qcom/sa8775p-ride.dtsi | 54 ++++++++++++++++++++++
 1 file changed, 54 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/sa8775p-ride.dtsi b/arch/arm64/boot/dts/qcom/sa8775p-ride.dtsi
index adb71aeff339..5a38de918024 100644
--- a/arch/arm64/boot/dts/qcom/sa8775p-ride.dtsi
+++ b/arch/arm64/boot/dts/qcom/sa8775p-ride.dtsi
@@ -421,6 +421,48 @@
 	status = "okay";
 };
 
+&mdss0 {
+	status = "okay";
+};
+
+&mdss0_dp0 {
+	status = "okay";
+
+	pinctrl-0 = <&dp0_hot_plug_det>;
+	pinctrl-names = "default";
+};
+
+&mdss0_dp0_out {
+	data-lanes = <0 1 2 3>;
+	link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>;
+};
+
+&mdss0_dp0_phy {
+	status = "okay";
+
+	vdda-phy-supply = <&vreg_l1c>;
+	vdda-pll-supply = <&vreg_l4a>;
+};
+
+&mdss0_dp1 {
+	status = "okay";
+
+	pinctrl-0 = <&dp1_hot_plug_det>;
+	pinctrl-names = "default";
+};
+
+&mdss0_dp1_out {
+	data-lanes = <0 1 2 3>;
+	link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>;
+};
+
+&mdss0_dp1_phy {
+	status = "okay";
+
+	vdda-phy-supply = <&vreg_l1c>;
+	vdda-pll-supply = <&vreg_l4a>;
+};
+
 &pmm8654au_0_gpios {
 	gpio-line-names = "DS_EN",
 			  "POFF_COMPLETE",
@@ -527,6 +569,18 @@
 };
 
 &tlmm {
+	dp0_hot_plug_det: dp0-hot-plug-det-state {
+		pins = "gpio101";
+		function = "edp0_hot";
+		bias-disable;
+	};
+
+	dp1_hot_plug_det: dp1-hot-plug-det-state {
+		pins = "gpio102";
+		function = "edp1_hot";
+		bias-disable;
+	};
+
 	ethernet0_default: ethernet0-default-state {
 		ethernet0_mdc: ethernet0-mdc-pins {
 			pins = "gpio8";
-- 
2.17.1

Re: [PATCH v2 2/2] arm64: dts: qcom: sa8775p-ride: Enable Display Port

[Dmitry Baryshkov]

On Tue, Oct 08, 2024 at 04:55:16PM GMT, Soutrik Mukhopadhyay wrote:
> Enable DPTX0 and DPTX1 along with their corresponding PHYs for
> sa8775p-ride platform.

What is connected to those DP lanes? If they are routed directly to the
DisplayPort connectors, please add corresponding devices (see
dp-connector).

> 
> Signed-off-by: Soutrik Mukhopadhyay <quic_mukhopad@quicinc.com>
> ---
>  arch/arm64/boot/dts/qcom/sa8775p-ride.dtsi | 54 ++++++++++++++++++++++
>  1 file changed, 54 insertions(+)
> 
> 

-- 
With best wishes
Dmitry

Re: [PATCH v2 2/2] arm64: dts: qcom: sa8775p-ride: Enable Display Port

[Soutrik Mukhopadhyay]

On 10/8/2024 5:46 PM, Dmitry Baryshkov wrote:
> On Tue, Oct 08, 2024 at 04:55:16PM GMT, Soutrik Mukhopadhyay wrote:
>> Enable DPTX0 and DPTX1 along with their corresponding PHYs for
>> sa8775p-ride platform.
> What is connected to those DP lanes? If they are routed directly to the
> DisplayPort connectors, please add corresponding devices (see
> dp-connector).


We are defining the functionality of gpio101 and gpio102 as "edp0_hot" 
and "edp1_hot"

respectively. This ensures that the hot plug will be directly routed via 
the display interrupt

line "mdss0" to the display port driver and no external dependencies on 
dp-connector is

necessary.


>   
>> Signed-off-by: Soutrik Mukhopadhyay <quic_mukhopad@quicinc.com>
>> ---
>>   arch/arm64/boot/dts/qcom/sa8775p-ride.dtsi | 54 ++++++++++++++++++++++
>>   1 file changed, 54 insertions(+)
>>
>>

Re: [PATCH v2 2/2] arm64: dts: qcom: sa8775p-ride: Enable Display Port

[Dmitry Baryshkov]

On Mon, 28 Oct 2024 at 10:49, Soutrik Mukhopadhyay
<quic_mukhopad@quicinc.com> wrote:
>
>
> On 10/8/2024 5:46 PM, Dmitry Baryshkov wrote:
> > On Tue, Oct 08, 2024 at 04:55:16PM GMT, Soutrik Mukhopadhyay wrote:
> >> Enable DPTX0 and DPTX1 along with their corresponding PHYs for
> >> sa8775p-ride platform.
> > What is connected to those DP lanes? If they are routed directly to the
> > DisplayPort connectors, please add corresponding devices (see
> > dp-connector).
>
>
> We are defining the functionality of gpio101 and gpio102 as "edp0_hot"
> and "edp1_hot"
>
> respectively. This ensures that the hot plug will be directly routed via
> the display interrupt
>
> line "mdss0" to the display port driver and no external dependencies on
> dp-connector is
>
> necessary.

Please describe the hardware, not the driver necessities.
If the board has a DP connector, please add the node. E.g. it allows
one to specify the label and the type used by the connector.

Also could you please fix your email client so that you don't have
strange/unnecessary line wraps and empty lines?

-- 
With best wishes
Dmitry

Re: [PATCH v2 2/2] arm64: dts: qcom: sa8775p-ride: Enable Display Port

[Soutrik Mukhopadhyay]

On 10/28/2024 3:15 PM, Dmitry Baryshkov wrote:
> On Mon, 28 Oct 2024 at 10:49, Soutrik Mukhopadhyay
> <quic_mukhopad@quicinc.com> wrote:
>>
>> On 10/8/2024 5:46 PM, Dmitry Baryshkov wrote:
>>> On Tue, Oct 08, 2024 at 04:55:16PM GMT, Soutrik Mukhopadhyay wrote:
>>>> Enable DPTX0 and DPTX1 along with their corresponding PHYs for
>>>> sa8775p-ride platform.
>>> What is connected to those DP lanes? If they are routed directly to the
>>> DisplayPort connectors, please add corresponding devices (see
>>> dp-connector).
>>
>> We are defining the functionality of gpio101 and gpio102 as "edp0_hot"
>> and "edp1_hot"
>>
>> respectively. This ensures that the hot plug will be directly routed via
>> the display interrupt
>>
>> line "mdss0" to the display port driver and no external dependencies on
>> dp-connector is
>>
>> necessary.
> Please describe the hardware, not the driver necessities.
> If the board has a DP connector, please add the node. E.g. it allows
> one to specify the label and the type used by the connector.
>
> Also could you please fix your email client so that you don't have
> strange/unnecessary line wraps and empty lines?

Addition of DP connector node with the hpd-gpio property does not allow 
hpd to be detected since the gpio

101/102 have the "edp0_hot" as function. If the hpd-gpio property is 
removed from the DP connector node,

the probe of DP connector will fail.


>

Re: [PATCH v2 2/2] arm64: dts: qcom: sa8775p-ride: Enable Display Port

[Dmitry Baryshkov]

On Tue, 29 Oct 2024 at 08:08, Soutrik Mukhopadhyay
<quic_mukhopad@quicinc.com> wrote:
>
>
> On 10/28/2024 3:15 PM, Dmitry Baryshkov wrote:
> > On Mon, 28 Oct 2024 at 10:49, Soutrik Mukhopadhyay
> > <quic_mukhopad@quicinc.com> wrote:
> >>
> >> On 10/8/2024 5:46 PM, Dmitry Baryshkov wrote:
> >>> On Tue, Oct 08, 2024 at 04:55:16PM GMT, Soutrik Mukhopadhyay wrote:
> >>>> Enable DPTX0 and DPTX1 along with their corresponding PHYs for
> >>>> sa8775p-ride platform.
> >>> What is connected to those DP lanes? If they are routed directly to the
> >>> DisplayPort connectors, please add corresponding devices (see
> >>> dp-connector).
> >>
> >> We are defining the functionality of gpio101 and gpio102 as "edp0_hot"
> >> and "edp1_hot"
> >>
> >> respectively. This ensures that the hot plug will be directly routed via
> >> the display interrupt
> >>
> >> line "mdss0" to the display port driver and no external dependencies on
> >> dp-connector is
> >>
> >> necessary.
> > Please describe the hardware, not the driver necessities.
> > If the board has a DP connector, please add the node. E.g. it allows
> > one to specify the label and the type used by the connector.
> >
> > Also could you please fix your email client so that you don't have
> > strange/unnecessary line wraps and empty lines?
>
> Addition of DP connector node with the hpd-gpio property does not allow
> hpd to be detected since the gpio
>
> 101/102 have the "edp0_hot" as function. If the hpd-gpio property is
> removed from the DP connector node,
>
> the probe of DP connector will fail.

No, it wont. It uses devm_gpiod_get_optional(). And if it does fail,
it is a bug which needs to be fixed.

And please, fix your email client so that it doesn't insert stray empty lines.

-- 
With best wishes
Dmitry