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From: Shawn Lin <shawn.lin@rock-chips.com>
To: "Heiko Stübner" <heiko@sntech.de>,
	aiyengar1990@gmail.com, "Will Deacon" <will@kernel.org>,
	"Robin Murphy" <robin.murphy@arm.com>,
	"Joerg Roedel (AMD)" <joro@8bytes.org>,
	"Rob Herring" <robh@kernel.org>,
	"Krzysztof Kozlowski" <krzk+dt@kernel.org>,
	"Conor Dooley" <conor+dt@kernel.org>,
	"Niklas Cassel" <cassel@kernel.org>
Cc: shawn.lin@rock-chips.com, linux-arm-kernel@lists.infradead.org,
	iommu@lists.linux.dev, devicetree@vger.kernel.org,
	linux-kernel@vger.kernel.org, linux-rockchip@lists.infradead.org,
	Simon Xue <xxm@rock-chips.com>,
	"finley.xiao" <finley.xiao@rock-chips.com>
Subject: Re: [PATCH 0/5] iommu/arm-smmu-v3: power domain and clock of the RK3588 PCIe SMMU
Date: Wed, 11 Nov 2026 16:02:30 +0800	[thread overview]
Message-ID: <ea8fa04c-4a8c-4c55-b4fa-f37d74267e93@rock-chips.com> (raw)
In-Reply-To: <10924894.NyiUUSuA9g@diego>

Hi Heiko

在 2026/11/10 星期二 16:49, Heiko Stübner 写道:
> Am Dienstag, 10. November 2026, 09:40:44 Mitteleuropäische Normalzeit schrieb Shawn Lin:
>> Cc: Simon and Finley
>>
>> 在 2026/11/10 星期二 15:11, Arun Iyengar via B4 Relay 写道:
>>> The MMU-600 in front of the PCIe controllers of the Rockchip RK3588
>>> (mmu600_pcie) is enabled for every RK3588 board, but its node describes
>>> neither the power domain it lives in (RK3588_PD_PCIE) nor its clock
>>> (ACLK_MMU_PCIE). Both are held by any enabled PCIe controller, which is
>>> why nobody noticed: on a board that enables no PCIe controller in that
>>> domain (an Orange Pi 5 with its M.2 slot in SATA mode, or any RK3588
>>> board without PCIe), genpd powers the domain off and the clock framework
>>> gates the clock as unused after boot, while arm-smmu-v3 stays bound.
>>> At reboot, arm_smmu_device_shutdown() then writes CR0 and polls CR0ACK on
>>> the dead block, the interconnect stalls, "reboot: Restarting system" is
>>> never reached and the board only comes back ~90 s later when the
>>> watchdog fires.
> 
> We have a work-around for that in some boards, manually disabling the
> smmu until now. As the SMMU is part of the SoC and always present
> the general DT practice is to have it always enabled, as it does not
> depend on the actual board design.
> 
> Hence we end up in the situation described above.
> 

I notice that mmu600_php is disabled in rk3588-base.dtsi. If describing
the SMMU that way is incorrect, should we enable mmu600_php as well? I'm
asking because I see a different picture in the RK3588 TRM: both
mmu600_php and mmu600_pcie reside under PD_PHP, not PD_PCIE. Therefore,
even without any PCIe controller enabled, PD_PHP should remain powered
on (it is never added in rk3588-base.dtsi, so it should be outside the
kernel’s scope). How does the original problem occur in that case?

> So this series fixes the actual underlying problem, making these
> workarounds unnecessary in the future :-)
> 
> 
> So definitly thanks a lot
> Heiko
> 
> 
> 


  reply	other threads:[~2026-11-11  8:02 UTC|newest]

Thread overview: 16+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-11-10  7:11 Arun Iyengar via B4 Relay
2026-11-10  7:11 ` [PATCH 1/5] dt-bindings: iommu: arm,smmu-v3: allow a power domain Arun Iyengar via B4 Relay
2026-11-10 14:51   ` Sebastian Reichel
2026-11-10  7:11 ` [PATCH 2/5] dt-bindings: iommu: arm,smmu-v3: allow clocks Arun Iyengar via B4 Relay
2026-11-10 14:55   ` Sebastian Reichel
2026-11-10  7:11 ` [PATCH 3/5] iommu/arm-smmu-v3: enable optional clocks Arun Iyengar via B4 Relay
2026-11-10 14:53   ` Sebastian Reichel
2026-11-10  7:11 ` [PATCH 4/5] arm64: dts: rockchip: add the PCIe power domain to the RK3588 PCIe SMMU Arun Iyengar via B4 Relay
2026-11-10 15:00   ` Sebastian Reichel
2026-11-11  6:53   ` Shawn Lin
2026-11-10  7:11 ` [PATCH 5/5] arm64: dts: rockchip: add the clock of " Arun Iyengar via B4 Relay
2026-11-10 15:07   ` Sebastian Reichel
2026-11-10  8:40 ` [PATCH 0/5] iommu/arm-smmu-v3: power domain and " Shawn Lin
2026-11-10  8:49   ` Heiko Stübner
2026-11-11  8:02     ` Shawn Lin [this message]
2026-11-10 15:13 ` Sebastian Reichel

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