[PATCH v5 0/2] drm/rockchip: vop: Add NV15, NV20 and NV30 support

[PATCH v5 0/2] drm/rockchip: vop: Add NV15, NV20 and NV30 support

[Jonas Karlman]

This series add support for displaying 10-bit 4:2:0 and 4:2:2 formats produced
by the Rockchip Video Decoder on RK322X, RK3288, RK3328, RK3368 and RK3399.
Also include 10-bit 4:4:4 support since VOP can support that also.

First patch adds new fourcc 10-bit YUV formats with 4:2:2/4:4:4 sub-sampling.
Second patch adds support for displaying the new fourcc formats.

These patches have been in use by LibreELEC and other distros for the
past 3+ years, hoping they can be merged this time around.

A rough libdrm/modetest patch [2] have been used to validate use of
NV15, NV20 and NV30 formats on RK3288, RK3328 and RK3399 boards.

  modetest -s <connector_id>@<crtc_id>:<mode>-<vrefresh>@<format>

Tinker Board R2.0 (rk3288w):
  modetest -s 50:1920x1080-60@NV15

Rock Pi 4 (rk3399):
  modetest -s 52@44:1920x1080-60@NV15

Rock64 (rk3328):
  modetest -s 42:1920x1080-60@NV15

Changes in v5:
- Use drm_format_info_min_pitch() for correct bpp
- Add missing NV21, NV61 and NV42 formats

Changes in v4:
- Rework RK3328/RK3399 win0/1 data to not affect RK3368

Changes in v3:
- No changes, rebased on next-20230616
- R-B tags was collected

Changes in v2:
- Add NV30 format
- R-B tags was not collected due to NV30 changes

This series is also available at [1] and libdrm/modetest patch at [2].

[1] https://github.com/Kwiboo/linux-rockchip/commits/v6.6-rc7-vop-nv15
[2] https://github.com/Kwiboo/libdrm/commits/nv15

Jonas Karlman (2):
  drm/fourcc: Add NV20 and NV30 YUV formats
  drm/rockchip: vop: Add NV15, NV20 and NV30 support

 drivers/gpu/drm/drm_fourcc.c                |  8 +++
 drivers/gpu/drm/rockchip/rockchip_drm_vop.c | 36 ++++++++---
 drivers/gpu/drm/rockchip/rockchip_drm_vop.h |  1 +
 drivers/gpu/drm/rockchip/rockchip_vop_reg.c | 66 +++++++++++++++++----
 include/uapi/drm/drm_fourcc.h               |  2 +
 5 files changed, 96 insertions(+), 17 deletions(-)

-- 
2.42.0

[PATCH v5 1/2] drm/fourcc: Add NV20 and NV30 YUV formats

[Jonas Karlman]

DRM_FORMAT_NV20 and DRM_FORMAT_NV30 formats is the 2x1 and non-subsampled
variant of NV15, a 10-bit 2-plane YUV format that has no padding between
components. Instead, luminance and chrominance samples are grouped into 4s
so that each group is packed into an integer number of bytes:

YYYY = UVUV = 4 * 10 bits = 40 bits = 5 bytes

The '20' and '30' suffix refers to the optimum effective bits per pixel
which is achieved when the total number of luminance samples is a multiple
of 4.

V2: Added NV30 format

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Sandy Huang <hjc@rock-chips.com>
---
 drivers/gpu/drm/drm_fourcc.c  | 8 ++++++++
 include/uapi/drm/drm_fourcc.h | 2 ++
 2 files changed, 10 insertions(+)

diff --git a/drivers/gpu/drm/drm_fourcc.c b/drivers/gpu/drm/drm_fourcc.c
index 0f17dfa8702b..193cf8ed7912 100644
--- a/drivers/gpu/drm/drm_fourcc.c
+++ b/drivers/gpu/drm/drm_fourcc.c
@@ -299,6 +299,14 @@ const struct drm_format_info *__drm_format_info(u32 format)
 		  .num_planes = 2, .char_per_block = { 5, 5, 0 },
 		  .block_w = { 4, 2, 0 }, .block_h = { 1, 1, 0 }, .hsub = 2,
 		  .vsub = 2, .is_yuv = true },
+		{ .format = DRM_FORMAT_NV20,		.depth = 0,
+		  .num_planes = 2, .char_per_block = { 5, 5, 0 },
+		  .block_w = { 4, 2, 0 }, .block_h = { 1, 1, 0 }, .hsub = 2,
+		  .vsub = 1, .is_yuv = true },
+		{ .format = DRM_FORMAT_NV30,		.depth = 0,
+		  .num_planes = 2, .char_per_block = { 5, 5, 0 },
+		  .block_w = { 4, 2, 0 }, .block_h = { 1, 1, 0 }, .hsub = 1,
+		  .vsub = 1, .is_yuv = true },
 		{ .format = DRM_FORMAT_Q410,		.depth = 0,
 		  .num_planes = 3, .char_per_block = { 2, 2, 2 },
 		  .block_w = { 1, 1, 1 }, .block_h = { 1, 1, 1 }, .hsub = 1,
diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h
index 8db7fd3f743e..3151f1fc7ebb 100644
--- a/include/uapi/drm/drm_fourcc.h
+++ b/include/uapi/drm/drm_fourcc.h
@@ -323,6 +323,8 @@ extern "C" {
  * index 1 = Cr:Cb plane, [39:0] Cr1:Cb1:Cr0:Cb0 little endian
  */
 #define DRM_FORMAT_NV15		fourcc_code('N', 'V', '1', '5') /* 2x2 subsampled Cr:Cb plane */
+#define DRM_FORMAT_NV20		fourcc_code('N', 'V', '2', '0') /* 2x1 subsampled Cr:Cb plane */
+#define DRM_FORMAT_NV30		fourcc_code('N', 'V', '3', '0') /* non-subsampled Cr:Cb plane */
 
 /*
  * 2 plane YCbCr MSB aligned
-- 
2.42.0

Re: [PATCH v5 1/2] drm/fourcc: Add NV20 and NV30 YUV formats

[Christopher Obbard]

Hi Jonas,

On Mon, 2023-10-23 at 17:37 +0000, Jonas Karlman wrote:
> DRM_FORMAT_NV20 and DRM_FORMAT_NV30 formats is the 2x1 and non-subsampled
> variant of NV15, a 10-bit 2-plane YUV format that has no padding between
> components. Instead, luminance and chrominance samples are grouped into 4s
> so that each group is packed into an integer number of bytes:
> 
> YYYY = UVUV = 4 * 10 bits = 40 bits = 5 bytes
> 
> The '20' and '30' suffix refers to the optimum effective bits per pixel
> which is achieved when the total number of luminance samples is a multiple
> of 4.
> 
> V2: Added NV30 format
> 
> Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
> Reviewed-by: Sandy Huang <hjc@rock-chips.com>

Reviewed-by: Christopher Obbard <chris.obbard@collabora.com>
Tested-by: Christopher Obbard <chris.obbard@collabora.com>


Cheers!

Chris

> ---
>  drivers/gpu/drm/drm_fourcc.c  | 8 ++++++++
>  include/uapi/drm/drm_fourcc.h | 2 ++
>  2 files changed, 10 insertions(+)
> 
> diff --git a/drivers/gpu/drm/drm_fourcc.c b/drivers/gpu/drm/drm_fourcc.c
> index 0f17dfa8702b..193cf8ed7912 100644
> --- a/drivers/gpu/drm/drm_fourcc.c
> +++ b/drivers/gpu/drm/drm_fourcc.c
> @@ -299,6 +299,14 @@ const struct drm_format_info *__drm_format_info(u32
> format)
>  		  .num_planes = 2, .char_per_block = { 5, 5, 0 },
>  		  .block_w = { 4, 2, 0 }, .block_h = { 1, 1, 0 }, .hsub =
> 2,
>  		  .vsub = 2, .is_yuv = true },
> +		{ .format = DRM_FORMAT_NV20,		.depth = 0,
> +		  .num_planes = 2, .char_per_block = { 5, 5, 0 },
> +		  .block_w = { 4, 2, 0 }, .block_h = { 1, 1, 0 }, .hsub =
> 2,
> +		  .vsub = 1, .is_yuv = true },
> +		{ .format = DRM_FORMAT_NV30,		.depth = 0,
> +		  .num_planes = 2, .char_per_block = { 5, 5, 0 },
> +		  .block_w = { 4, 2, 0 }, .block_h = { 1, 1, 0 }, .hsub =
> 1,
> +		  .vsub = 1, .is_yuv = true },
>  		{ .format = DRM_FORMAT_Q410,		.depth = 0,
>  		  .num_planes = 3, .char_per_block = { 2, 2, 2 },
>  		  .block_w = { 1, 1, 1 }, .block_h = { 1, 1, 1 }, .hsub =
> 1,
> diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h
> index 8db7fd3f743e..3151f1fc7ebb 100644
> --- a/include/uapi/drm/drm_fourcc.h
> +++ b/include/uapi/drm/drm_fourcc.h
> @@ -323,6 +323,8 @@ extern "C" {
>   * index 1 = Cr:Cb plane, [39:0] Cr1:Cb1:Cr0:Cb0 little endian
>   */
>  #define DRM_FORMAT_NV15		fourcc_code('N', 'V', '1', '5') /*
> 2x2 subsampled Cr:Cb plane */
> +#define DRM_FORMAT_NV20		fourcc_code('N', 'V', '2', '0') /*
> 2x1 subsampled Cr:Cb plane */
> +#define DRM_FORMAT_NV30		fourcc_code('N', 'V', '3', '0') /*
> non-subsampled Cr:Cb plane */
>  
>  /*
>   * 2 plane YCbCr MSB aligned

[PATCH v5 2/2] drm/rockchip: vop: Add NV15, NV20 and NV30 support

[Jonas Karlman]

Add support for displaying 10-bit 4:2:0 and 4:2:2 formats produced by
the Rockchip Video Decoder on RK322X, RK3288, RK3328 and RK3399.
Also add support for 10-bit 4:4:4 format while at it.

V5: Use drm_format_info_min_pitch() for correct bpp
    Add missing NV21, NV61 and NV42 formats
V4: Rework RK3328/RK3399 win0/1 data to not affect RK3368
V2: Added NV30 support

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Sandy Huang <hjc@rock-chips.com>
---
 drivers/gpu/drm/rockchip/rockchip_drm_vop.c | 36 ++++++++---
 drivers/gpu/drm/rockchip/rockchip_drm_vop.h |  1 +
 drivers/gpu/drm/rockchip/rockchip_vop_reg.c | 66 +++++++++++++++++----
 3 files changed, 86 insertions(+), 17 deletions(-)

diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
index 14320bc73e5b..b3d0b6ae9294 100644
--- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
+++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
@@ -272,6 +272,18 @@ static bool has_uv_swapped(uint32_t format)
 	}
 }
 
+static bool is_fmt_10(uint32_t format)
+{
+	switch (format) {
+	case DRM_FORMAT_NV15:
+	case DRM_FORMAT_NV20:
+	case DRM_FORMAT_NV30:
+		return true;
+	default:
+		return false;
+	}
+}
+
 static enum vop_data_format vop_convert_format(uint32_t format)
 {
 	switch (format) {
@@ -287,12 +299,15 @@ static enum vop_data_format vop_convert_format(uint32_t format)
 	case DRM_FORMAT_BGR565:
 		return VOP_FMT_RGB565;
 	case DRM_FORMAT_NV12:
+	case DRM_FORMAT_NV15:
 	case DRM_FORMAT_NV21:
 		return VOP_FMT_YUV420SP;
 	case DRM_FORMAT_NV16:
+	case DRM_FORMAT_NV20:
 	case DRM_FORMAT_NV61:
 		return VOP_FMT_YUV422SP;
 	case DRM_FORMAT_NV24:
+	case DRM_FORMAT_NV30:
 	case DRM_FORMAT_NV42:
 		return VOP_FMT_YUV444SP;
 	default:
@@ -944,7 +959,12 @@ static void vop_plane_atomic_update(struct drm_plane *plane,
 	dsp_sty = dest->y1 + crtc->mode.vtotal - crtc->mode.vsync_start;
 	dsp_st = dsp_sty << 16 | (dsp_stx & 0xffff);
 
-	offset = (src->x1 >> 16) * fb->format->cpp[0];
+	if (fb->format->char_per_block[0])
+		offset = drm_format_info_min_pitch(fb->format, 0,
+						   src->x1 >> 16);
+	else
+		offset = (src->x1 >> 16) * fb->format->cpp[0];
+
 	offset += (src->y1 >> 16) * fb->pitches[0];
 	dma_addr = rk_obj->dma_addr + offset + fb->offsets[0];
 
@@ -970,6 +990,7 @@ static void vop_plane_atomic_update(struct drm_plane *plane,
 	}
 
 	VOP_WIN_SET(vop, win, format, format);
+	VOP_WIN_SET(vop, win, fmt_10, is_fmt_10(fb->format->format));
 	VOP_WIN_SET(vop, win, yrgb_vir, DIV_ROUND_UP(fb->pitches[0], 4));
 	VOP_WIN_SET(vop, win, yrgb_mst, dma_addr);
 	VOP_WIN_YUV2YUV_SET(vop, win_yuv2yuv, y2r_en, is_yuv);
@@ -979,15 +1000,16 @@ static void vop_plane_atomic_update(struct drm_plane *plane,
 		    (new_state->rotation & DRM_MODE_REFLECT_X) ? 1 : 0);
 
 	if (is_yuv) {
-		int hsub = fb->format->hsub;
-		int vsub = fb->format->vsub;
-		int bpp = fb->format->cpp[1];
-
 		uv_obj = fb->obj[1];
 		rk_uv_obj = to_rockchip_obj(uv_obj);
 
-		offset = (src->x1 >> 16) * bpp / hsub;
-		offset += (src->y1 >> 16) * fb->pitches[1] / vsub;
+		if (fb->format->char_per_block[1])
+			offset = drm_format_info_min_pitch(fb->format, 1,
+							   src->x1 >> 16);
+		else
+			offset = (src->x1 >> 16) * fb->format->cpp[1];
+		offset /= fb->format->hsub;
+		offset += (src->y1 >> 16) * fb->pitches[1] / fb->format->vsub;
 
 		dma_addr = rk_uv_obj->dma_addr + offset + fb->offsets[1];
 		VOP_WIN_SET(vop, win, uv_vir, DIV_ROUND_UP(fb->pitches[1], 4));
diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.h b/drivers/gpu/drm/rockchip/rockchip_drm_vop.h
index 5f56e0597df8..4b2daefeb8c1 100644
--- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.h
+++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.h
@@ -186,6 +186,7 @@ struct vop_win_phy {
 	struct vop_reg enable;
 	struct vop_reg gate;
 	struct vop_reg format;
+	struct vop_reg fmt_10;
 	struct vop_reg rb_swap;
 	struct vop_reg uv_swap;
 	struct vop_reg act_info;
diff --git a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
index 7b2805006776..f8cef0cb7bff 100644
--- a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
+++ b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
@@ -53,6 +53,26 @@ static const uint32_t formats_win_full[] = {
 	DRM_FORMAT_NV42,
 };
 
+static const uint32_t formats_win_full_10[] = {
+	DRM_FORMAT_XRGB8888,
+	DRM_FORMAT_ARGB8888,
+	DRM_FORMAT_XBGR8888,
+	DRM_FORMAT_ABGR8888,
+	DRM_FORMAT_RGB888,
+	DRM_FORMAT_BGR888,
+	DRM_FORMAT_RGB565,
+	DRM_FORMAT_BGR565,
+	DRM_FORMAT_NV12,
+	DRM_FORMAT_NV21,
+	DRM_FORMAT_NV16,
+	DRM_FORMAT_NV61,
+	DRM_FORMAT_NV24,
+	DRM_FORMAT_NV42,
+	DRM_FORMAT_NV15,
+	DRM_FORMAT_NV20,
+	DRM_FORMAT_NV30,
+};
+
 static const uint64_t format_modifiers_win_full[] = {
 	DRM_FORMAT_MOD_LINEAR,
 	DRM_FORMAT_MOD_INVALID,
@@ -627,11 +647,12 @@ static const struct vop_scl_regs rk3288_win_full_scl = {
 
 static const struct vop_win_phy rk3288_win01_data = {
 	.scl = &rk3288_win_full_scl,
-	.data_formats = formats_win_full,
-	.nformats = ARRAY_SIZE(formats_win_full),
+	.data_formats = formats_win_full_10,
+	.nformats = ARRAY_SIZE(formats_win_full_10),
 	.format_modifiers = format_modifiers_win_full,
 	.enable = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 0),
 	.format = VOP_REG(RK3288_WIN0_CTRL0, 0x7, 1),
+	.fmt_10 = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 4),
 	.rb_swap = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 12),
 	.uv_swap = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 15),
 	.act_info = VOP_REG(RK3288_WIN0_ACT_INFO, 0x1fff1fff, 0),
@@ -936,13 +957,38 @@ static const struct vop_win_yuv2yuv_data rk3399_vop_big_win_yuv2yuv_data[] = {
 
 };
 
-static const struct vop_win_phy rk3399_win01_data = {
+static const struct vop_win_phy rk3399_win0_data = {
 	.scl = &rk3288_win_full_scl,
-	.data_formats = formats_win_full,
-	.nformats = ARRAY_SIZE(formats_win_full),
+	.data_formats = formats_win_full_10,
+	.nformats = ARRAY_SIZE(formats_win_full_10),
 	.format_modifiers = format_modifiers_win_full_afbc,
 	.enable = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 0),
 	.format = VOP_REG(RK3288_WIN0_CTRL0, 0x7, 1),
+	.fmt_10 = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 4),
+	.rb_swap = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 12),
+	.uv_swap = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 15),
+	.x_mir_en = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 21),
+	.y_mir_en = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 22),
+	.act_info = VOP_REG(RK3288_WIN0_ACT_INFO, 0x1fff1fff, 0),
+	.dsp_info = VOP_REG(RK3288_WIN0_DSP_INFO, 0x0fff0fff, 0),
+	.dsp_st = VOP_REG(RK3288_WIN0_DSP_ST, 0x1fff1fff, 0),
+	.yrgb_mst = VOP_REG(RK3288_WIN0_YRGB_MST, 0xffffffff, 0),
+	.uv_mst = VOP_REG(RK3288_WIN0_CBR_MST, 0xffffffff, 0),
+	.yrgb_vir = VOP_REG(RK3288_WIN0_VIR, 0x3fff, 0),
+	.uv_vir = VOP_REG(RK3288_WIN0_VIR, 0x3fff, 16),
+	.src_alpha_ctl = VOP_REG(RK3288_WIN0_SRC_ALPHA_CTRL, 0xff, 0),
+	.dst_alpha_ctl = VOP_REG(RK3288_WIN0_DST_ALPHA_CTRL, 0xff, 0),
+	.channel = VOP_REG(RK3288_WIN0_CTRL2, 0xff, 0),
+};
+
+static const struct vop_win_phy rk3399_win1_data = {
+	.scl = &rk3288_win_full_scl,
+	.data_formats = formats_win_full_10,
+	.nformats = ARRAY_SIZE(formats_win_full_10),
+	.format_modifiers = format_modifiers_win_full,
+	.enable = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 0),
+	.format = VOP_REG(RK3288_WIN0_CTRL0, 0x7, 1),
+	.fmt_10 = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 4),
 	.rb_swap = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 12),
 	.uv_swap = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 15),
 	.x_mir_en = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 21),
@@ -965,9 +1011,9 @@ static const struct vop_win_phy rk3399_win01_data = {
  * AFBC on the primary plane.
  */
 static const struct vop_win_data rk3399_vop_win_data[] = {
-	{ .base = 0x00, .phy = &rk3399_win01_data,
+	{ .base = 0x00, .phy = &rk3399_win0_data,
 	  .type = DRM_PLANE_TYPE_PRIMARY },
-	{ .base = 0x40, .phy = &rk3368_win01_data,
+	{ .base = 0x40, .phy = &rk3399_win1_data,
 	  .type = DRM_PLANE_TYPE_OVERLAY },
 	{ .base = 0x00, .phy = &rk3368_win23_data,
 	  .type = DRM_PLANE_TYPE_OVERLAY },
@@ -1099,11 +1145,11 @@ static const struct vop_intr rk3328_vop_intr = {
 };
 
 static const struct vop_win_data rk3328_vop_win_data[] = {
-	{ .base = 0xd0, .phy = &rk3368_win01_data,
+	{ .base = 0xd0, .phy = &rk3399_win1_data,
 	  .type = DRM_PLANE_TYPE_PRIMARY },
-	{ .base = 0x1d0, .phy = &rk3368_win01_data,
+	{ .base = 0x1d0, .phy = &rk3399_win1_data,
 	  .type = DRM_PLANE_TYPE_OVERLAY },
-	{ .base = 0x2d0, .phy = &rk3368_win01_data,
+	{ .base = 0x2d0, .phy = &rk3399_win1_data,
 	  .type = DRM_PLANE_TYPE_CURSOR },
 };
 
-- 
2.42.0

Re: [PATCH v5 2/2] drm/rockchip: vop: Add NV15, NV20 and NV30 support

[Christopher Obbard]

Hi Jonas,

On Mon, 2023-10-23 at 17:37 +0000, Jonas Karlman wrote:
> Add support for displaying 10-bit 4:2:0 and 4:2:2 formats produced by
> the Rockchip Video Decoder on RK322X, RK3288, RK3328 and RK3399.
> Also add support for 10-bit 4:4:4 format while at it.
> 
> V5: Use drm_format_info_min_pitch() for correct bpp
>     Add missing NV21, NV61 and NV42 formats
> V4: Rework RK3328/RK3399 win0/1 data to not affect RK3368
> V2: Added NV30 support
> 
> Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
> Reviewed-by: Sandy Huang <hjc@rock-chips.com>

Reviewed-by: Christopher Obbard <chris.obbard@collabora.com>
Tested-by: Christopher Obbard <chris.obbard@collabora.com>


Cheers!

Chris

> ---
>  drivers/gpu/drm/rockchip/rockchip_drm_vop.c | 36 ++++++++---
>  drivers/gpu/drm/rockchip/rockchip_drm_vop.h |  1 +
>  drivers/gpu/drm/rockchip/rockchip_vop_reg.c | 66 +++++++++++++++++----
>  3 files changed, 86 insertions(+), 17 deletions(-)
> 
> diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
> b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
> index 14320bc73e5b..b3d0b6ae9294 100644
> --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
> +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
> @@ -272,6 +272,18 @@ static bool has_uv_swapped(uint32_t format)
>  	}
>  }
>  
> +static bool is_fmt_10(uint32_t format)
> +{
> +	switch (format) {
> +	case DRM_FORMAT_NV15:
> +	case DRM_FORMAT_NV20:
> +	case DRM_FORMAT_NV30:
> +		return true;
> +	default:
> +		return false;
> +	}
> +}
> +
>  static enum vop_data_format vop_convert_format(uint32_t format)
>  {
>  	switch (format) {
> @@ -287,12 +299,15 @@ static enum vop_data_format
> vop_convert_format(uint32_t format)
>  	case DRM_FORMAT_BGR565:
>  		return VOP_FMT_RGB565;
>  	case DRM_FORMAT_NV12:
> +	case DRM_FORMAT_NV15:
>  	case DRM_FORMAT_NV21:
>  		return VOP_FMT_YUV420SP;
>  	case DRM_FORMAT_NV16:
> +	case DRM_FORMAT_NV20:
>  	case DRM_FORMAT_NV61:
>  		return VOP_FMT_YUV422SP;
>  	case DRM_FORMAT_NV24:
> +	case DRM_FORMAT_NV30:
>  	case DRM_FORMAT_NV42:
>  		return VOP_FMT_YUV444SP;
>  	default:
> @@ -944,7 +959,12 @@ static void vop_plane_atomic_update(struct drm_plane
> *plane,
>  	dsp_sty = dest->y1 + crtc->mode.vtotal - crtc->mode.vsync_start;
>  	dsp_st = dsp_sty << 16 | (dsp_stx & 0xffff);
>  
> -	offset = (src->x1 >> 16) * fb->format->cpp[0];
> +	if (fb->format->char_per_block[0])
> +		offset = drm_format_info_min_pitch(fb->format, 0,
> +						   src->x1 >> 16);
> +	else
> +		offset = (src->x1 >> 16) * fb->format->cpp[0];
> +
>  	offset += (src->y1 >> 16) * fb->pitches[0];
>  	dma_addr = rk_obj->dma_addr + offset + fb->offsets[0];
>  
> @@ -970,6 +990,7 @@ static void vop_plane_atomic_update(struct drm_plane
> *plane,
>  	}
>  
>  	VOP_WIN_SET(vop, win, format, format);
> +	VOP_WIN_SET(vop, win, fmt_10, is_fmt_10(fb->format->format));
>  	VOP_WIN_SET(vop, win, yrgb_vir, DIV_ROUND_UP(fb->pitches[0], 4));
>  	VOP_WIN_SET(vop, win, yrgb_mst, dma_addr);
>  	VOP_WIN_YUV2YUV_SET(vop, win_yuv2yuv, y2r_en, is_yuv);
> @@ -979,15 +1000,16 @@ static void vop_plane_atomic_update(struct drm_plane
> *plane,
>  		    (new_state->rotation & DRM_MODE_REFLECT_X) ? 1 : 0);
>  
>  	if (is_yuv) {
> -		int hsub = fb->format->hsub;
> -		int vsub = fb->format->vsub;
> -		int bpp = fb->format->cpp[1];
> -
>  		uv_obj = fb->obj[1];
>  		rk_uv_obj = to_rockchip_obj(uv_obj);
>  
> -		offset = (src->x1 >> 16) * bpp / hsub;
> -		offset += (src->y1 >> 16) * fb->pitches[1] / vsub;
> +		if (fb->format->char_per_block[1])
> +			offset = drm_format_info_min_pitch(fb->format, 1,
> +							   src->x1 >> 16);
> +		else
> +			offset = (src->x1 >> 16) * fb->format->cpp[1];
> +		offset /= fb->format->hsub;
> +		offset += (src->y1 >> 16) * fb->pitches[1] / fb->format-
> >vsub;
>  
>  		dma_addr = rk_uv_obj->dma_addr + offset + fb->offsets[1];
>  		VOP_WIN_SET(vop, win, uv_vir, DIV_ROUND_UP(fb->pitches[1],
> 4));
> diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.h
> b/drivers/gpu/drm/rockchip/rockchip_drm_vop.h
> index 5f56e0597df8..4b2daefeb8c1 100644
> --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.h
> +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.h
> @@ -186,6 +186,7 @@ struct vop_win_phy {
>  	struct vop_reg enable;
>  	struct vop_reg gate;
>  	struct vop_reg format;
> +	struct vop_reg fmt_10;
>  	struct vop_reg rb_swap;
>  	struct vop_reg uv_swap;
>  	struct vop_reg act_info;
> diff --git a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
> b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
> index 7b2805006776..f8cef0cb7bff 100644
> --- a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
> +++ b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
> @@ -53,6 +53,26 @@ static const uint32_t formats_win_full[] = {
>  	DRM_FORMAT_NV42,
>  };
>  
> +static const uint32_t formats_win_full_10[] = {
> +	DRM_FORMAT_XRGB8888,
> +	DRM_FORMAT_ARGB8888,
> +	DRM_FORMAT_XBGR8888,
> +	DRM_FORMAT_ABGR8888,
> +	DRM_FORMAT_RGB888,
> +	DRM_FORMAT_BGR888,
> +	DRM_FORMAT_RGB565,
> +	DRM_FORMAT_BGR565,
> +	DRM_FORMAT_NV12,
> +	DRM_FORMAT_NV21,
> +	DRM_FORMAT_NV16,
> +	DRM_FORMAT_NV61,
> +	DRM_FORMAT_NV24,
> +	DRM_FORMAT_NV42,
> +	DRM_FORMAT_NV15,
> +	DRM_FORMAT_NV20,
> +	DRM_FORMAT_NV30,
> +};
> +
>  static const uint64_t format_modifiers_win_full[] = {
>  	DRM_FORMAT_MOD_LINEAR,
>  	DRM_FORMAT_MOD_INVALID,
> @@ -627,11 +647,12 @@ static const struct vop_scl_regs rk3288_win_full_scl =
> {
>  
>  static const struct vop_win_phy rk3288_win01_data = {
>  	.scl = &rk3288_win_full_scl,
> -	.data_formats = formats_win_full,
> -	.nformats = ARRAY_SIZE(formats_win_full),
> +	.data_formats = formats_win_full_10,
> +	.nformats = ARRAY_SIZE(formats_win_full_10),
>  	.format_modifiers = format_modifiers_win_full,
>  	.enable = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 0),
>  	.format = VOP_REG(RK3288_WIN0_CTRL0, 0x7, 1),
> +	.fmt_10 = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 4),
>  	.rb_swap = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 12),
>  	.uv_swap = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 15),
>  	.act_info = VOP_REG(RK3288_WIN0_ACT_INFO, 0x1fff1fff, 0),
> @@ -936,13 +957,38 @@ static const struct vop_win_yuv2yuv_data
> rk3399_vop_big_win_yuv2yuv_data[] = {
>  
>  };
>  
> -static const struct vop_win_phy rk3399_win01_data = {
> +static const struct vop_win_phy rk3399_win0_data = {
>  	.scl = &rk3288_win_full_scl,
> -	.data_formats = formats_win_full,
> -	.nformats = ARRAY_SIZE(formats_win_full),
> +	.data_formats = formats_win_full_10,
> +	.nformats = ARRAY_SIZE(formats_win_full_10),
>  	.format_modifiers = format_modifiers_win_full_afbc,
>  	.enable = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 0),
>  	.format = VOP_REG(RK3288_WIN0_CTRL0, 0x7, 1),
> +	.fmt_10 = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 4),
> +	.rb_swap = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 12),
> +	.uv_swap = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 15),
> +	.x_mir_en = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 21),
> +	.y_mir_en = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 22),
> +	.act_info = VOP_REG(RK3288_WIN0_ACT_INFO, 0x1fff1fff, 0),
> +	.dsp_info = VOP_REG(RK3288_WIN0_DSP_INFO, 0x0fff0fff, 0),
> +	.dsp_st = VOP_REG(RK3288_WIN0_DSP_ST, 0x1fff1fff, 0),
> +	.yrgb_mst = VOP_REG(RK3288_WIN0_YRGB_MST, 0xffffffff, 0),
> +	.uv_mst = VOP_REG(RK3288_WIN0_CBR_MST, 0xffffffff, 0),
> +	.yrgb_vir = VOP_REG(RK3288_WIN0_VIR, 0x3fff, 0),
> +	.uv_vir = VOP_REG(RK3288_WIN0_VIR, 0x3fff, 16),
> +	.src_alpha_ctl = VOP_REG(RK3288_WIN0_SRC_ALPHA_CTRL, 0xff, 0),
> +	.dst_alpha_ctl = VOP_REG(RK3288_WIN0_DST_ALPHA_CTRL, 0xff, 0),
> +	.channel = VOP_REG(RK3288_WIN0_CTRL2, 0xff, 0),
> +};
> +
> +static const struct vop_win_phy rk3399_win1_data = {
> +	.scl = &rk3288_win_full_scl,
> +	.data_formats = formats_win_full_10,
> +	.nformats = ARRAY_SIZE(formats_win_full_10),
> +	.format_modifiers = format_modifiers_win_full,
> +	.enable = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 0),
> +	.format = VOP_REG(RK3288_WIN0_CTRL0, 0x7, 1),
> +	.fmt_10 = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 4),
>  	.rb_swap = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 12),
>  	.uv_swap = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 15),
>  	.x_mir_en = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 21),
> @@ -965,9 +1011,9 @@ static const struct vop_win_phy rk3399_win01_data = {
>   * AFBC on the primary plane.
>   */
>  static const struct vop_win_data rk3399_vop_win_data[] = {
> -	{ .base = 0x00, .phy = &rk3399_win01_data,
> +	{ .base = 0x00, .phy = &rk3399_win0_data,
>  	  .type = DRM_PLANE_TYPE_PRIMARY },
> -	{ .base = 0x40, .phy = &rk3368_win01_data,
> +	{ .base = 0x40, .phy = &rk3399_win1_data,
>  	  .type = DRM_PLANE_TYPE_OVERLAY },
>  	{ .base = 0x00, .phy = &rk3368_win23_data,
>  	  .type = DRM_PLANE_TYPE_OVERLAY },
> @@ -1099,11 +1145,11 @@ static const struct vop_intr rk3328_vop_intr = {
>  };
>  
>  static const struct vop_win_data rk3328_vop_win_data[] = {
> -	{ .base = 0xd0, .phy = &rk3368_win01_data,
> +	{ .base = 0xd0, .phy = &rk3399_win1_data,
>  	  .type = DRM_PLANE_TYPE_PRIMARY },
> -	{ .base = 0x1d0, .phy = &rk3368_win01_data,
> +	{ .base = 0x1d0, .phy = &rk3399_win1_data,
>  	  .type = DRM_PLANE_TYPE_OVERLAY },
> -	{ .base = 0x2d0, .phy = &rk3368_win01_data,
> +	{ .base = 0x2d0, .phy = &rk3399_win1_data,
>  	  .type = DRM_PLANE_TYPE_CURSOR },
>  };
>  

Re: [PATCH v5 0/2] drm/rockchip: vop: Add NV15, NV20 and NV30 support

[Christopher Obbard]

Hi Jonas,

On Mon, 2023-10-23 at 17:37 +0000, Jonas Karlman wrote:
> This series add support for displaying 10-bit 4:2:0 and 4:2:2 formats
> produced
> by the Rockchip Video Decoder on RK322X, RK3288, RK3328, RK3368 and RK3399.
> Also include 10-bit 4:4:4 support since VOP can support that also.
> 
> First patch adds new fourcc 10-bit YUV formats with 4:2:2/4:4:4 sub-
> sampling.
> Second patch adds support for displaying the new fourcc formats.
> 
> These patches have been in use by LibreELEC and other distros for the
> past 3+ years, hoping they can be merged this time around.
> 
> A rough libdrm/modetest patch [2] have been used to validate use of
> NV15, NV20 and NV30 formats on RK3288, RK3328 and RK3399 boards.
> 
>   modetest -s <connector_id>@<crtc_id>:<mode>-<vrefresh>@<format>
> 
> Tinker Board R2.0 (rk3288w):
>   modetest -s 50:1920x1080-60@NV15
> 
> Rock Pi 4 (rk3399):
>   modetest -s 52@44:1920x1080-60@NV15
> 
> Rock64 (rk3328):
>   modetest -s 42:1920x1080-60@NV15
> 
> Changes in v5:
> - Use drm_format_info_min_pitch() for correct bpp
> - Add missing NV21, NV61 and NV42 formats
> 
> Changes in v4:
> - Rework RK3328/RK3399 win0/1 data to not affect RK3368
> 
> Changes in v3:
> - No changes, rebased on next-20230616
> - R-B tags was collected
> 
> Changes in v2:
> - Add NV30 format
> - R-B tags was not collected due to NV30 changes
> 
> This series is also available at [1] and libdrm/modetest patch at [2].
> 
> [1] https://github.com/Kwiboo/linux-rockchip/commits/v6.6-rc7-vop-nv15
> [2] https://github.com/Kwiboo/libdrm/commits/nv15

Could you open a draft merge request for libdrm upstream at
https://gitlab.freedesktop.org/mesa/drm pointing to this series? If there are
subsequent revisions of this series, it'd be great to link that merge request
in the cover letter.


Cheers!

Chris

> 
> Jonas Karlman (2):
>   drm/fourcc: Add NV20 and NV30 YUV formats
>   drm/rockchip: vop: Add NV15, NV20 and NV30 support
> 
>  drivers/gpu/drm/drm_fourcc.c                |  8 +++
>  drivers/gpu/drm/rockchip/rockchip_drm_vop.c | 36 ++++++++---
>  drivers/gpu/drm/rockchip/rockchip_drm_vop.h |  1 +
>  drivers/gpu/drm/rockchip/rockchip_vop_reg.c | 66 +++++++++++++++++----
>  include/uapi/drm/drm_fourcc.h               |  2 +
>  5 files changed, 96 insertions(+), 17 deletions(-)
> 

Re: [PATCH v5 0/2] drm/rockchip: vop: Add NV15, NV20 and NV30 support

[Jonas Karlman]

Hi Chris,

On 2023-10-23 19:52, Christopher Obbard wrote:
> Hi Jonas,
> 
> On Mon, 2023-10-23 at 17:37 +0000, Jonas Karlman wrote:
>> This series add support for displaying 10-bit 4:2:0 and 4:2:2 formats
>> produced
>> by the Rockchip Video Decoder on RK322X, RK3288, RK3328, RK3368 and RK3399.
>> Also include 10-bit 4:4:4 support since VOP can support that also.
>>
>> First patch adds new fourcc 10-bit YUV formats with 4:2:2/4:4:4 sub-
>> sampling.
>> Second patch adds support for displaying the new fourcc formats.
>>
>> These patches have been in use by LibreELEC and other distros for the
>> past 3+ years, hoping they can be merged this time around.
>>
>> A rough libdrm/modetest patch [2] have been used to validate use of
>> NV15, NV20 and NV30 formats on RK3288, RK3328 and RK3399 boards.
>>
>>   modetest -s <connector_id>@<crtc_id>:<mode>-<vrefresh>@<format>
>>
>> Tinker Board R2.0 (rk3288w):
>>   modetest -s 50:1920x1080-60@NV15
>>
>> Rock Pi 4 (rk3399):
>>   modetest -s 52@44:1920x1080-60@NV15
>>
>> Rock64 (rk3328):
>>   modetest -s 42:1920x1080-60@NV15
>>
>> Changes in v5:
>> - Use drm_format_info_min_pitch() for correct bpp
>> - Add missing NV21, NV61 and NV42 formats
>>
>> Changes in v4:
>> - Rework RK3328/RK3399 win0/1 data to not affect RK3368
>>
>> Changes in v3:
>> - No changes, rebased on next-20230616
>> - R-B tags was collected
>>
>> Changes in v2:
>> - Add NV30 format
>> - R-B tags was not collected due to NV30 changes
>>
>> This series is also available at [1] and libdrm/modetest patch at [2].
>>
>> [1] https://github.com/Kwiboo/linux-rockchip/commits/v6.6-rc7-vop-nv15
>> [2] https://github.com/Kwiboo/libdrm/commits/nv15
> 
> Could you open a draft merge request for libdrm upstream at
> https://gitlab.freedesktop.org/mesa/drm pointing to this series? If there are
> subsequent revisions of this series, it'd be great to link that merge request
> in the cover letter.

Have created a draft merge reguest for libdrm/modetest changes now.
https://gitlab.freedesktop.org/mesa/drm/-/merge_requests/329

The pattern code could really need some improvements/refactoring, in
current form it should at least be enough to create a test pattern to
help test/validate this series :-)

Regards,
Jonas

> 
> 
> Cheers!
> 
> Chris
> 
>>
>> Jonas Karlman (2):
>>   drm/fourcc: Add NV20 and NV30 YUV formats
>>   drm/rockchip: vop: Add NV15, NV20 and NV30 support
>>
>>  drivers/gpu/drm/drm_fourcc.c                |  8 +++
>>  drivers/gpu/drm/rockchip/rockchip_drm_vop.c | 36 ++++++++---
>>  drivers/gpu/drm/rockchip/rockchip_drm_vop.h |  1 +
>>  drivers/gpu/drm/rockchip/rockchip_vop_reg.c | 66 +++++++++++++++++----
>>  include/uapi/drm/drm_fourcc.h               |  2 +
>>  5 files changed, 96 insertions(+), 17 deletions(-)
>>

Re: [PATCH v5 0/2] drm/rockchip: vop: Add NV15, NV20 and NV30 support

[Heiko Stuebner]

On Mon, 23 Oct 2023 17:37:13 +0000, Jonas Karlman wrote:
> This series add support for displaying 10-bit 4:2:0 and 4:2:2 formats produced
> by the Rockchip Video Decoder on RK322X, RK3288, RK3328, RK3368 and RK3399.
> Also include 10-bit 4:4:4 support since VOP can support that also.
> 
> First patch adds new fourcc 10-bit YUV formats with 4:2:2/4:4:4 sub-sampling.
> Second patch adds support for displaying the new fourcc formats.
> 
> [...]

Applied, thanks!

[1/2] drm/fourcc: Add NV20 and NV30 YUV formats
      commit: 728c15b4b5f3369cbde73d5e0f14701ab370f985
[2/2] drm/rockchip: vop: Add NV15, NV20 and NV30 support
      commit: d4b384228562848e4b76b608a5876c92160e993c

Best regards,
-- 
Heiko Stuebner <heiko@sntech.de>