[PATCH 0/2] ufs: add delay for VCC ramp-up stability

[PATCH 0/2] ufs: add delay for VCC ramp-up stability

[ed.tsai]

Hi,

This patch series resolves a link stability issue found on our certain
platforms where the VCC regulator has a slow ramp-up time.

To fix this, a delay is needed after VCC is turned on. The solution is
implemented in two parts:

1. Introduced the new host quriks, UFSHCD_QUIRK_VCC_ON_DELAY.
2. Applied in our new platform with UFS5 device to enusre the VCC is
   ready before we enable the clocks.

[PATCH 1/2] ufs: core: Add quriks for VCC ramp-up delay

[ed.tsai]

From: Ed Tsai <ed.tsai@mediatek.com>

On some platforms, the VCC regulator has a slow ramp-up time. Add a
delay after enabling VCC to ensure voltage has fully stabilized before
we enable the clocks.

Signed-off-by: Ed Tsai <ed.tsai@mediatek.com>
---
 drivers/ufs/core/ufshcd.c | 12 ++++++++++++
 include/ufs/ufshcd.h      |  6 ++++++
 2 files changed, 18 insertions(+)

diff --git a/drivers/ufs/core/ufshcd.c b/drivers/ufs/core/ufshcd.c
index 899e663fea6e..bea72e7c1d32 100644
--- a/drivers/ufs/core/ufshcd.c
+++ b/drivers/ufs/core/ufshcd.c
@@ -9942,11 +9942,13 @@ static void ufshcd_vreg_set_lpm(struct ufs_hba *hba)
 #ifdef CONFIG_PM
 static int ufshcd_vreg_set_hpm(struct ufs_hba *hba)
 {
+	bool vcc_on = false;
 	int ret = 0;
 
 	if (ufshcd_is_ufs_dev_poweroff(hba) && ufshcd_is_link_off(hba) &&
 	    !hba->dev_info.is_lu_power_on_wp) {
 		ret = ufshcd_setup_vreg(hba, true);
+		vcc_on = true;
 	} else if (!ufshcd_is_ufs_dev_active(hba)) {
 		if (!ufshcd_is_link_active(hba)) {
 			ret = ufshcd_config_vreg_hpm(hba, hba->vreg_info.vccq);
@@ -9957,6 +9959,7 @@ static int ufshcd_vreg_set_hpm(struct ufs_hba *hba)
 				goto vccq_lpm;
 		}
 		ret = ufshcd_toggle_vreg(hba->dev, hba->vreg_info.vcc, true);
+		vcc_on = true;
 	}
 	goto out;
 
@@ -9965,6 +9968,15 @@ static int ufshcd_vreg_set_hpm(struct ufs_hba *hba)
 vcc_disable:
 	ufshcd_toggle_vreg(hba->dev, hba->vreg_info.vcc, false);
 out:
+	/*
+	 * On platforms with a slow VCC ramp-up, a delay is needed after
+	 * turning on VCC to ensure the voltage is stable before the
+	 * reference clock is enabled.
+	 */
+	if (hba->quirks & UFSHCD_QUIRK_VCC_ON_DELAY && !ret && vcc_on &&
+	    hba->vreg_info.vcc && !hba->vreg_info.vcc->always_on)
+		usleep_range(1000, 1100);
+
 	return ret;
 }
 #endif /* CONFIG_PM */
diff --git a/include/ufs/ufshcd.h b/include/ufs/ufshcd.h
index 8563b6648976..bf50078708b9 100644
--- a/include/ufs/ufshcd.h
+++ b/include/ufs/ufshcd.h
@@ -690,6 +690,12 @@ enum ufshcd_quirks {
 	 * because it causes link startup to become unreliable.
 	 */
 	UFSHCD_QUIRK_PERFORM_LINK_STARTUP_ONCE		= 1 << 26,
+
+	/*
+	 * On some platforms, the VCC regulator has a slow ramp-up time. Add a
+	 * delay after enable VCC to ensure it's stable.
+	 */
+	UFSHCD_QUIRK_VCC_ON_DELAY			= 1 << 27,
 };
 
 enum ufshcd_caps {
-- 
2.45.2

[PATCH 2/2] ufs: host: mediatek: Add VCC on delay for stability

[ed.tsai]

From: Ed Tsai <ed.tsai@mediatek.com>

Introduced a delay after enabling UFS5 VCC for MT6995 to ensure
voltage stability before refclk activation.

Signed-off-by: Ed Tsai <ed.tsai@mediatek.com>
---
 drivers/ufs/host/ufs-mediatek.c | 11 +++++++++++
 drivers/ufs/host/ufs-mediatek.h |  4 ++++
 2 files changed, 15 insertions(+)

diff --git a/drivers/ufs/host/ufs-mediatek.c b/drivers/ufs/host/ufs-mediatek.c
index b3daaa07e925..020302f8fbdf 100644
--- a/drivers/ufs/host/ufs-mediatek.c
+++ b/drivers/ufs/host/ufs-mediatek.c
@@ -1960,6 +1960,8 @@ static int ufs_mtk_apply_dev_quirks(struct ufs_hba *hba)
 
 static void ufs_mtk_fixup_dev_quirks(struct ufs_hba *hba)
 {
+	struct ufs_mtk_host *host = ufshcd_get_variant(hba);
+
 	ufshcd_fixup_dev_quirks(hba, ufs_mtk_dev_fixups);
 
 	if (ufs_mtk_is_broken_vcc(hba) && hba->vreg_info.vcc) {
@@ -1971,6 +1973,15 @@ static void ufs_mtk_fixup_dev_quirks(struct ufs_hba *hba)
 		hba->dev_quirks &= ~UFS_DEVICE_QUIRK_DELAY_BEFORE_LPM;
 	}
 
+	/*
+	 * Add a delay after enable UFS5 VCC to ensure the voltage is
+	 * stable before the refclk enable.
+	 */
+	if (hba->dev_info.wspecversion >= 0x0500 &&
+	    (host->ip_ver == IP_VER_MT6995_A0 ||
+	     host->ip_ver == IP_VER_MT6995_B0))
+		hba->quirks |= UFSHCD_QUIRK_VCC_ON_DELAY;
+
 	ufs_mtk_vreg_fix_vcc(hba);
 	ufs_mtk_vreg_fix_vccqx(hba);
 	ufs_mtk_fix_ahit(hba);
diff --git a/drivers/ufs/host/ufs-mediatek.h b/drivers/ufs/host/ufs-mediatek.h
index 9747277f11e8..8547a6f04990 100644
--- a/drivers/ufs/host/ufs-mediatek.h
+++ b/drivers/ufs/host/ufs-mediatek.h
@@ -220,6 +220,10 @@ enum {
 	IP_VER_MT6991_B0 = 0x10470000,
 	IP_VER_MT6993    = 0x10480000,
 
+	/* UFSHCI 5.0 */
+	IP_VER_MT6995_A0 = 0x10490000,
+	IP_VER_MT6995_B0 = 0x10500000,
+
 	IP_VER_NONE      = 0xFFFFFFFF
 };
 
-- 
2.45.2

Re: [PATCH 2/2] ufs: host: mediatek: Add VCC on delay for stability

[Bart Van Assche]

On 3/5/26 2:29 AM, ed.tsai@mediatek.com wrote:
> Introduced a delay after enabling UFS5 VCC for MT6995 to ensure
> voltage stability before refclk activation.

Patch descriptions should use the imperative mood (Introduced ->
Introduce).

> +	/*
> +	 * Add a delay after enable UFS5 VCC to ensure the voltage is
> +	 * stable before the refclk enable.
> +	 */

after enable -> after enabling
refclk enable -> refclk is enabled

Otherwise this patch looks good to me.

Thanks,

Bart.

Re: [PATCH 1/2] ufs: core: Add quriks for VCC ramp-up delay

[Bart Van Assche]

On 3/5/26 2:29 AM, ed.tsai@mediatek.com wrote:
> +	/*
> +	 * On platforms with a slow VCC ramp-up, a delay is needed after
> +	 * turning on VCC to ensure the voltage is stable before the
> +	 * reference clock is enabled.
> +	 */
> +	if (hba->quirks & UFSHCD_QUIRK_VCC_ON_DELAY && !ret && vcc_on &&
> +	    hba->vreg_info.vcc && !hba->vreg_info.vcc->always_on)
> +		usleep_range(1000, 1100);

Since the value of the delay is platform-dependent, has it been
considered to introduce a new vendor operation (vop)?

Thanks,

Bart.

Re: [PATCH 1/2] ufs: core: Add quriks for VCC ramp-up delay

[Ed Tsai (蔡宗軒)]

On Thu, 2026-03-05 at 06:24 -0600, Bart Van Assche wrote:
> On 3/5/26 2:29 AM, ed.tsai@mediatek.com wrote:
> > +     /*
> > +      * On platforms with a slow VCC ramp-up, a delay is needed
> > after
> > +      * turning on VCC to ensure the voltage is stable before the
> > +      * reference clock is enabled.
> > +      */
> > +     if (hba->quirks & UFSHCD_QUIRK_VCC_ON_DELAY && !ret && vcc_on
> > &&
> > +         hba->vreg_info.vcc && !hba->vreg_info.vcc->always_on)
> > +             usleep_range(1000, 1100);
> 
> Since the value of the delay is platform-dependent, has it been
> considered to introduce a new vendor operation (vop)?
> 
> Thanks,
> 
> Bart.

A vop does feel a bit heavyweight for a simple sleep. How about we add
a new configurable variable, similar to the approach used for the VCC
off delay?

Best,

Ed Tsai

Re: [PATCH 1/2] ufs: core: Add quriks for VCC ramp-up delay

[Bart Van Assche]

On 3/5/26 6:19 PM, Ed Tsai (蔡宗軒) wrote:
> On Thu, 2026-03-05 at 06:24 -0600, Bart Van Assche wrote:
>> On 3/5/26 2:29 AM, ed.tsai@mediatek.com wrote:
>>> +     /*
>>> +      * On platforms with a slow VCC ramp-up, a delay is needed
>>> after
>>> +      * turning on VCC to ensure the voltage is stable before the
>>> +      * reference clock is enabled.
>>> +      */
>>> +     if (hba->quirks & UFSHCD_QUIRK_VCC_ON_DELAY && !ret && vcc_on
>>> &&
>>> +         hba->vreg_info.vcc && !hba->vreg_info.vcc->always_on)
>>> +             usleep_range(1000, 1100);
>>
>> Since the value of the delay is platform-dependent, has it been
>> considered to introduce a new vendor operation (vop)?
>
> A vop does feel a bit heavyweight for a simple sleep. How about we add
> a new configurable variable, similar to the approach used for the VCC
> off delay?

Let's postpone introducing such a configuration variable until there is
a real need for such a configuration variable.

Bart.

Re: [PATCH 1/2] ufs: core: Add quriks for VCC ramp-up delay

[Bart Van Assche]

On 3/5/26 2:29 AM, ed.tsai@mediatek.com wrote:
> On some platforms, the VCC regulator has a slow ramp-up time. Add a
> delay after enabling VCC to ensure voltage has fully stabilized before
> we enable the clocks.

Reviewed-by: Bart Van Assche <bvanassche@acm.org>