From: Andrew Lunn <andrew@lunn.ch>
To: Jie Luo <quic_luoj@quicinc.com>
Cc: davem@davemloft.net, edumazet@google.com, kuba@kernel.org,
pabeni@redhat.com, robh+dt@kernel.org,
krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org,
hkallweit1@gmail.com, linux@armlinux.org.uk, corbet@lwn.net,
p.zabel@pengutronix.de, f.fainelli@gmail.com,
netdev@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org
Subject: Re: [PATCH v8 14/14] dt-bindings: net: ar803x: add qca8084 PHY properties
Date: Fri, 15 Dec 2023 14:31:13 +0100 [thread overview]
Message-ID: <f5c5cbce-c36e-498a-97e2-35f06d927d74@lunn.ch> (raw)
In-Reply-To: <a65ad12d-b990-4439-b196-903f4a5f096a@quicinc.com>
On Fri, Dec 15, 2023 at 08:33:00PM +0800, Jie Luo wrote:
>
>
> On 12/15/2023 8:12 PM, Andrew Lunn wrote:
> > > + clocks:
> > > + items:
> > > + - description: APB bridge clock
> > > + - description: AHB clock
> > > + - description: Security control clock
> > > + - description: TLMM clock
> > > + - description: TLMM AHB clock
> > > + - description: CNOC AHB clock
> > > + - description: MDIO AHB clock
> > > + - description: MDIO master AHB clock
> > > + - description: PCS0 system clock
> > > + - description: PCS1 system clock
> > > + - description: EPHY0 system clock
> > > + - description: EPHY1 system clock
> > > + - description: EPHY2 system clock
> > > + - description: EPHY3 system clock
> Hi Andrew,
> These clocks are for the whole PHY package including quad PHYs, since
> these clocks & resets need to be initialized at one point, i put it
> the previous MDIO driver code, these clocks & resets are configured
> after GPIO hardware reset, after these clocks and resets sequences
> configured, each PHY capabilities can be acquired correctly in the PHY
> probe function.
I really expect the hardware is hierarchical. Its unlikely that EPHY0
is connected to all four PHYs in the package. Its specific to one
PHY. So it should be in the DT properties for that one specific PHY. I
expect the resets are the same. It seems there is a soft and hard
reset per PHY, so i would expect these to be in the node for one PHY.
Do the two PCS instances take up two MDIO address? They can be
considered devices on the bus, so could have a DT node, and hence you
can place the PCS clocks on that node?
What exactly do the two MDIO clocks do? I assume these are not for the
MDIO bus master, but the MDIO slave block within the PHY package?
There is one MDIO slave block shared by the four PHYs. So these are
package properties and should be in the package node in DT.
Look at all the other clocks and decide, are they package clocks, or
specific to one block on the MDIO bus? Do the properties go in the
package node, or the per PHY node?
Andrew
next prev parent reply other threads:[~2023-12-15 13:31 UTC|newest]
Thread overview: 52+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-12-15 7:39 [PATCH v8 00/14] add qca8084 ethernet phy driver Luo Jie
2023-12-15 7:39 ` [PATCH v8 01/14] net: phy: introduce core support for phy-mode = "10g-qxgmii" Luo Jie
2023-12-15 7:39 ` [PATCH v8 02/14] dt-bindings: net: ethernet-controller: add 10g-qxgmii mode Luo Jie
2023-12-15 7:39 ` [PATCH v8 03/14] net: phy: at803x: add QCA8084 ethernet phy support Luo Jie
2023-12-15 7:39 ` [PATCH v8 04/14] net: phy: at803x: add the function phydev_id_is_qca808x Luo Jie
2023-12-15 7:39 ` [PATCH v8 05/14] net: phy: at803x: Add qca8084_config_init function Luo Jie
2023-12-15 7:39 ` [PATCH v8 06/14] net: phy: at803x: add qca8084_link_change_notify Luo Jie
2023-12-15 7:39 ` [PATCH v8 07/14] net: phy: at803x: add the possible_interfaces Luo Jie
2023-12-15 7:39 ` [PATCH v8 08/14] net: phy: at803x: add qca8084 switch registe access Luo Jie
2023-12-15 7:39 ` [PATCH v8 09/14] net: phy: at803x: set MDIO address of qca8084 PHY Luo Jie
2023-12-15 7:40 ` [PATCH v8 10/14] net: phy: at803x: parse qca8084 clocks and resets Luo Jie
2023-12-15 7:40 ` [PATCH v8 11/14] net: phy: at803x: add qca808x initial config sequence Luo Jie
2023-12-15 7:40 ` [PATCH v8 12/14] net: phy: at803x: configure qca8084 common clocks Luo Jie
2023-12-15 7:40 ` [PATCH v8 13/14] net: phy: at803x: configure qca8084 work mode Luo Jie
2023-12-17 13:02 ` Simon Horman
2023-12-18 3:33 ` Jie Luo
2023-12-15 7:40 ` [PATCH v8 14/14] dt-bindings: net: ar803x: add qca8084 PHY properties Luo Jie
2023-12-15 8:22 ` Krzysztof Kozlowski
2023-12-15 10:16 ` Jie Luo
2023-12-15 11:25 ` Andrew Lunn
2023-12-15 12:16 ` Jie Luo
2023-12-15 13:42 ` Russell King (Oracle)
2023-12-16 7:57 ` Jie Luo
2023-12-16 17:17 ` Andrew Lunn
2023-12-18 4:53 ` Jie Luo
2023-12-18 9:34 ` Andrew Lunn
2023-12-19 8:52 ` Jie Luo
2023-12-15 12:12 ` Andrew Lunn
2023-12-15 12:33 ` Jie Luo
2023-12-15 13:31 ` Andrew Lunn [this message]
2023-12-16 7:37 ` Jie Luo
2023-12-16 10:21 ` Andrew Lunn
2023-12-16 13:25 ` Jie Luo
2023-12-16 13:51 ` Russell King (Oracle)
2023-12-16 14:41 ` Jie Luo
2023-12-16 16:01 ` Christian Marangi
2023-12-18 5:22 ` Jie Luo
2023-12-16 16:09 ` Russell King (Oracle)
2023-12-18 3:01 ` Jie Luo
2024-01-02 9:57 ` Russell King (Oracle)
2024-01-02 10:08 ` Christian Marangi
2024-01-03 13:27 ` Jie Luo
2024-01-03 14:22 ` Andrew Lunn
2024-01-04 9:53 ` Jie Luo
2024-01-04 13:57 ` Andrew Lunn
2024-01-05 10:26 ` Jie Luo
2024-01-05 13:37 ` Andrew Lunn
2024-01-08 8:27 ` Jie Luo
2023-12-16 17:30 ` Andrew Lunn
2023-12-16 19:08 ` Russell King (Oracle)
2023-12-18 3:31 ` Jie Luo
2023-12-18 3:27 ` Jie Luo
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