Re: [PATCH v12 09/31] LoongArch: KVM: Implement vcpu get, vcpu set registers

[Tianrui Zhao <zhaotianrui@loongson.cn>]

在 2023年06月06日 14:41, Youling Tang 写道:
>
>
> On 05/30/2023 09:52 AM, Tianrui Zhao wrote:
>> Implement LoongArch vcpu get registers and set registers operations, it
>> is called when user space use the ioctl interface to get or set regs.
>>
>> Signed-off-by: Tianrui Zhao <zhaotianrui@loongson.cn>
>> ---
>>  arch/loongarch/kvm/csr_ops.S |  76 +++++++++++++
>>  arch/loongarch/kvm/vcpu.c    | 206 +++++++++++++++++++++++++++++++++++
>>  2 files changed, 282 insertions(+)
>>  create mode 100644 arch/loongarch/kvm/csr_ops.S
>>
>> diff --git a/arch/loongarch/kvm/csr_ops.S b/arch/loongarch/kvm/csr_ops.S
>> new file mode 100644
>> index 000000000000..962b96d8291a
>> --- /dev/null
>> +++ b/arch/loongarch/kvm/csr_ops.S
>> @@ -0,0 +1,76 @@
>> +/* SPDX-License-Identifier: GPL-2.0 */
>> +/*
>> + * Copyright (C) 2020-2023 Loongson Technology Corporation Limited
>> + */
>> +
>> +#include <asm/regdef.h>
>> +#include <linux/linkage.h>
>> +    .text
>> +    .section        .text
>> +    .cfi_sections   .debug_frame
>> +/*
>> + * we have splited hw gcsr into three parts, so we can
>> + * calculate the code offset by gcsrid and jump here to
>> + * run the gcsrwr instruction.
>> + */
>> +SYM_FUNC_START(set_hw_gcsr)
>> +    addi.d      t0,   a0,   0
>> +    addi.w      t1,   zero, 96
>> +    bltu        t1,   t0,   1f
>> +    la.pcrel    t0,   10f
>> +    alsl.d      t0,   a0,   t0, 3
>> +    jirl        zero, t0,   0
> jr t0
Thanks, I will fix those instructions.

Thanks
Tianrui Zhao
>
>> +1:
>> +    addi.w      t1,   a0,   -128
>> +    addi.w      t2,   zero, 15
>> +    bltu        t2,   t1,   2f
>> +    la.pcrel    t0,   11f
>> +    alsl.d      t0,   t1,   t0, 3
>> +    jirl        zero, t0,   0
> jr t0
>
>> +2:
>> +    addi.w      t1,   a0,   -384
>> +    addi.w      t2,   zero, 3
>> +    bltu        t2,   t1,   3f
>> +    la.pcrel    t0,   12f
>> +    alsl.d      t0,   t1,   t0, 3
>> +    jirl        zero, t0,   0
> jr t0
>
>> +3:
>> +    addi.w      a0,   zero, -1
>> +    jirl        zero, ra,   0
> jr ra
>
>> +/*
>> + * write guest csr
>> + * 0x05000000 | (LOONGARCH_CSR_XXX << 10) | 1 << 5 | a1
>> + * range from 0x0(KVM_CSR_CRMD) to 0x60 (KVM_CSR_LLBCTL)
>> + */
>> +10:
>> +    csrnum = 0
>> +    .rept 0x61
>> +        .word 0x05000020 | csrnum << 10 | 5
>> +        jirl zero, ra, 0
> ditto.
>> +        csrnum = csrnum + 1
>> +    .endr
>> +/*
>> + * write guest csr
>> + * 0x05000000 | (LOONGARCH_CSR_XXX << 10) | 1<<5 | a1
>> + * range from 0x80 (KVM_CSR_IMPCTL1) to 0x8f (KVM_CSR_TLBRPRMD)
>> + */
>> +11:
>> +    csrnum = 0x80
>> +    .rept 0x10
>> +        .word 0x05000020 | csrnum << 10 | 5
>> +        jirl zero, ra, 0
> ditto.
>> +        csrnum = csrnum + 1
>> +    .endr
>> +/*
>> + * write guest csr
>> + * 0x05000000 | (LOONGARCH_CSR_XXX << 10) | 1<<5 | a1
>> + * range from 0x180(KVM_CSR_DMWIN0) to 0x183(KVM_CSR_DMWIN3)
>> + */
>> +12:
>> +    csrnum = 0x180
>> +    .rept 0x4
>> +        .word 0x05000020 | csrnum << 10 | 5
>> +        jirl zero, ra, 0
> ditto.
>
> Thanks,
> Youling
>> +        csrnum = csrnum + 1
>> +    .endr
>> +SYM_FUNC_END(set_hw_gcsr)