Re: [PATCH v2 5/6] media: qcom: camss: sm8250: set the VFE AREG clock rate from the VFE

[Bryan O'Donoghue <bod@kernel.org>]

On 24/10/2026 10:40, Atanas Filipov wrote:
> The SM8250 VFE AREG clock lists four rates, 100, 200, 300 and 400 MHz,
> in both the VFE and the CSID resources. The VFE only enables it, as
> vfe_match_clock_names() does not match the AREG clock name, so its rate
> is set by the CSID, which always selects the lowest one.
> 
> Match the VFE AREG clock in vfe_match_clock_names(), so that the VFE
> selects its rate from the pixel rate of its lines like for its other
> clocks, and drop its levels from the CSID resources. The AREG clocks of
> VFE0 and VFE1 share the fast AHB source, which then runs at the highest
> rate requested by the two VFEs.
> 
> Signed-off-by: Atanas Filipov<atanas.filipov@oss.qualcomm.com>
> ---

Sets the lowest, isn't necessarily a bug.

Why is 100MHz a problem and if it is, why not just fix to 400MHz ?

areg is a register access / AHB clock - your worst case outcome is 
'register access goes slower' - which to me accepting we don't do 
driver-specific clock-aggregation => raise the clock required across VFE 
and CSID so that nobody looses out on the bus times..

Again instead of having a driver-specific clock aggregation mechanism, 
if we need to solve for two siblings voting for their parent's rate - 
then lets do that in CCF so that every CCF consumer benefits.

That's obviously a separate and potentially large series so for this 
specific case I'd suggest 400MHz iff a problem can be shown.

---
bod