Re: [PATCH v2] arm64: dts: qcom: qcs615: Add QUPv3 configuration

[Viken Dadhaniya <quic_vdadhani@quicinc.com>]

On 10/28/2024 5:03 PM, Krzysztof Kozlowski wrote:
> On 28/10/2024 12:20, Viken Dadhaniya wrote:
>> Add DT support for QUPv3 Serial Engines.
>>
>> Co-developed-by: Mukesh Kumar Savaliya <quic_msavaliy@quicinc.com>
>> Signed-off-by: Mukesh Kumar Savaliya <quic_msavaliy@quicinc.com>
>> Signed-off-by: Viken Dadhaniya <quic_vdadhani@quicinc.com>
>> ---
>>
>> Build Dependencies:
>>
>> Base:
>> https://lore.kernel.org/linux-devicetree/20240926-add_initial_support_for_qcs615-v3-5-e37617e91c62@quicinc.com/
>> https://lore.kernel.org/linux-devicetree/20240926-add_initial_support_for_qcs615-v3-6-e37617e91c62@quicinc.com/
>>
>> Clock: https://lore.kernel.org/linux-devicetree/20240920-qcs615-clock-driver-v2-3-2f6de44eb2aa@quicinc.com/
>> ICC: https://lore.kernel.org/linux-devicetree/20240924143958.25-2-quic_rlaggysh@quicinc.com/
>> Apps SMMU: https://lore.kernel.org/all/20241011063112.19087-1-quic_qqzhou@quicinc.com/
>>
>> v1 -> v2:
>>
>> - Add opp-shared property.
>> - Use QCOM_ICC_TAG_ALWAYS flag in interconnect property.
>>
>> v1 Link: https://lore.kernel.org/all/20241011103346.22925-1-quic_vdadhani@quicinc.com/
>> ---
>>   arch/arm64/boot/dts/qcom/qcs615.dtsi | 642 ++++++++++++++++++++++++++-
>>   1 file changed, 638 insertions(+), 4 deletions(-)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/qcs615.dtsi b/arch/arm64/boot/dts/qcom/qcs615.dtsi
>> index 865ead601f85..1d1cdf6f9a74 100644
>> --- a/arch/arm64/boot/dts/qcom/qcs615.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/qcs615.dtsi
>> @@ -5,6 +5,7 @@
>>   
>>   #include <dt-bindings/clock/qcom,qcs615-gcc.h>
>>   #include <dt-bindings/clock/qcom,rpmh.h>
>> +#include <dt-bindings/dma/qcom-gpi.h>
>>   #include <dt-bindings/interconnect/qcom,icc.h>
>>   #include <dt-bindings/interconnect/qcom,qcs615-rpmh.h>
>>   #include <dt-bindings/interrupt-controller/arm-gic.h>
>> @@ -17,6 +18,21 @@
>>   	#address-cells = <2>;
>>   	#size-cells = <2>;
>>   
>> +	aliases {
>> +		i2c1 = &i2c1;
>> +		i2c2 = &i2c2;
>> +		i2c3 = &i2c3;
>> +		i2c4 = &i2c4;
>> +		i2c5 = &i2c5;
>> +		i2c6 = &i2c6;
>> +		i2c7 = &i2c7;
>> +		spi2 = &spi2;
>> +		spi4 = &spi4;
>> +		spi6 = &spi6;
>> +		spi7 = &spi7;
>> +		serial0 = &uart0;
> 
> Comments from v1 apply.

Updated in v3.

> 
>> +	};
>> +
>>   	cpus {
>>   		#address-cells = <2>;
>>   		#size-cells = <0>;
>> @@ -296,6 +312,26 @@
>>   		qcom,bcm-voters = <&apps_bcm_voter>;
>>   	};
>>   
>> +	qup_opp_table: opp-table-qup {
>> +		compatible = "operating-points-v2";
>> +		opp-shared;
>> +
>> +		opp-75000000 {
>> +			opp-hz = /bits/ 64 <75000000>;
>> +			required-opps = <&rpmhpd_opp_low_svs>;
>> +		};
>> +
>> +		opp-100000000 {
>> +			opp-hz = /bits/ 64 <100000000>;
>> +			required-opps = <&rpmhpd_opp_svs>;
>> +		};
>> +
>> +		opp-128000000 {
>> +			opp-hz = /bits/ 64 <128000000>;
>> +			required-opps = <&rpmhpd_opp_nom>;
>> +		};
>> +	};
>> +
>>   	psci {
>>   		compatible = "arm,psci-1.0";
>>   		method = "smc";
>> @@ -392,6 +428,24 @@
>>   			#size-cells = <1>;
>>   		};
>>   
>> +		gpi_dma0: qcom,gpi-dma@800000  {
> 
> Nope. Don't post downstream code.

Sure. updated in v3.

> 
> Best regards,
> Krzysztof
>