[PATCH] x86, tsc: Fix tsc ratio calibration to avoid broken mdelay

[PATCH] x86, tsc: Fix tsc ratio calibration to avoid broken mdelay

[yu.c.chen]

From: Chen Yu <yu.c.chen@intel.com>

Currently we fetch the tsc radio by:
ratio = (lo >> 8) & 0x1f;
thus get bit8~bit12 of the MSR_PLATFORM_INFO, however according
to Intel 64 and IA-32 Architectures Software Developer Manual 35.5,
the ratio bit should be bit8~bit15, otherwise we might get incorrect
tsc ratio and cause system hang later(mdelay corrupted).

Fix this problem by masking 0xff instead.

Cc: 3.14+ <stable@vger.kernel.org> # 3.14+
Signed-off-by: Chen Yu <yu.c.chen@intel.com>
---
 arch/x86/kernel/tsc_msr.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/x86/kernel/tsc_msr.c b/arch/x86/kernel/tsc_msr.c
index 92ae6ac..6aa0f4d 100644
--- a/arch/x86/kernel/tsc_msr.c
+++ b/arch/x86/kernel/tsc_msr.c
@@ -92,7 +92,7 @@ unsigned long try_msr_calibrate_tsc(void)
 
 	if (freq_desc_tables[cpu_index].msr_plat) {
 		rdmsr(MSR_PLATFORM_INFO, lo, hi);
-		ratio = (lo >> 8) & 0x1f;
+		ratio = (lo >> 8) & 0xff;
 	} else {
 		rdmsr(MSR_IA32_PERF_STATUS, lo, hi);
 		ratio = (hi >> 8) & 0x1f;
-- 
2.7.4

Re: [PATCH] x86, tsc: Fix tsc ratio calibration to avoid broken mdelay

[Thomas Gleixner]

On Fri, 6 May 2016, yu.c.chen@intel.com wrote:
> From: Chen Yu <yu.c.chen@intel.com>
> 
> Currently we fetch the tsc radio by:
> ratio = (lo >> 8) & 0x1f;
> thus get bit8~bit12 of the MSR_PLATFORM_INFO, however according
> to Intel 64 and IA-32 Architectures Software Developer Manual 35.5,
> the ratio bit should be bit8~bit15, otherwise we might get incorrect
> tsc ratio and cause system hang later(mdelay corrupted).

The resulting issue is that both TSC frequency, which is used for udelay, and
the lapic timer frequency are wrong. mdelay is just the visible damage caused
by that.
 
Thanks,

	tglx

Re: [PATCH] x86, tsc: Fix tsc ratio calibration to avoid broken mdelay

[Thomas Gleixner]

On Fri, 6 May 2016, Thomas Gleixner wrote:
> On Fri, 6 May 2016, yu.c.chen@intel.com wrote:
> > From: Chen Yu <yu.c.chen@intel.com>
> > 
> > Currently we fetch the tsc radio by:
> > ratio = (lo >> 8) & 0x1f;
> > thus get bit8~bit12 of the MSR_PLATFORM_INFO, however according
> > to Intel 64 and IA-32 Architectures Software Developer Manual 35.5,
> > the ratio bit should be bit8~bit15, otherwise we might get incorrect
> > tsc ratio and cause system hang later(mdelay corrupted).
> 
> The resulting issue is that both TSC frequency, which is used for udelay, and
> the lapic timer frequency are wrong. mdelay is just the visible damage caused
> by that.

Aside of that:

> Cc: 3.14+ <stable@vger.kernel.org> # 3.14+

Please use:

Fixes: commit '....'

next time, which identifies the kernel version to which this needs to be
backported and gives a reference to the commit which caused the issue.

Thanks,

	tglx

RE: [PATCH] x86, tsc: Fix tsc ratio calibration to avoid broken mdelay

[Chen, Yu C]

> -----Original Message-----
> From: Thomas Gleixner [mailto:tglx@linutronix.de]
> Sent: Friday, May 06, 2016 5:53 PM
> To: Chen, Yu C
> Cc: x86@kernel.org; linux-kernel@vger.kernel.org; Ingo Molnar; H. Peter Anvin;
> Gao, Bin; Len Brown; Rafael J. Wysocki; 3 . 14+ # 3 . 14+
> Subject: Re: [PATCH] x86, tsc: Fix tsc ratio calibration to avoid broken mdelay
> 
> 
> On Fri, 6 May 2016, Thomas Gleixner wrote:
> > On Fri, 6 May 2016, yu.c.chen@intel.com wrote:
> > > From: Chen Yu <yu.c.chen@intel.com>
> > >
> > > Currently we fetch the tsc radio by:
> > > ratio = (lo >> 8) & 0x1f;
> > > thus get bit8~bit12 of the MSR_PLATFORM_INFO, however according to
> > > Intel 64 and IA-32 Architectures Software Developer Manual 35.5, the
> > > ratio bit should be bit8~bit15, otherwise we might get incorrect tsc
> > > ratio and cause system hang later(mdelay corrupted).
> >
> > The resulting issue is that both TSC frequency, which is used for
> > udelay, and the lapic timer frequency are wrong. mdelay is just the
> > visible damage caused by that.
> 
> Aside of that:
> 
> > Cc: 3.14+ <stable@vger.kernel.org> # 3.14+
> 
> Please use:
> 
> Fixes: commit '....'
> 
> next time, which identifies the kernel version to which this needs to be
> backported and gives a reference to the commit which caused the issue.
> 
OK, thanks!

[tip:x86/urgent] x86/tsc: Read all ratio bits from MSR_PLATFORM_INFO

[tip-bot for Chen Yu]

Commit-ID:  886123fb3a8656699dff40afa0573df359abeb18
Gitweb:     http://git.kernel.org/tip/886123fb3a8656699dff40afa0573df359abeb18
Author:     Chen Yu <yu.c.chen@intel.com>
AuthorDate: Fri, 6 May 2016 11:33:39 +0800
Committer:  Thomas Gleixner <tglx@linutronix.de>
CommitDate: Fri, 6 May 2016 11:50:50 +0200

x86/tsc: Read all ratio bits from MSR_PLATFORM_INFO

Currently we read the tsc radio: ratio = (MSR_PLATFORM_INFO >> 8) & 0x1f;

Thus we get bit 8-12 of MSR_PLATFORM_INFO, however according to the SDM
(35.5), the ratio bits are bit 8-15.

Ignoring the upper bits can result in an incorrect tsc ratio, which causes the
TSC calibration and the Local APIC timer frequency to be incorrect.

Fix this problem by masking 0xff instead.

[ tglx: Massaged changelog ]

Fixes: 7da7c1561366 "x86, tsc: Add static (MSR) TSC calibration on Intel Atom SoCs"
Signed-off-by: Chen Yu <yu.c.chen@intel.com>
Cc: "Rafael J. Wysocki" <rafael@kernel.org>
Cc: stable@vger.kernel.org
Cc: Bin Gao <bin.gao@intel.com>
Cc: Len Brown <lenb@kernel.org>
Link: http://lkml.kernel.org/r/1462505619-5516-1-git-send-email-yu.c.chen@intel.com
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>

---
 arch/x86/kernel/tsc_msr.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/x86/kernel/tsc_msr.c b/arch/x86/kernel/tsc_msr.c
index 92ae6ac..6aa0f4d 100644
--- a/arch/x86/kernel/tsc_msr.c
+++ b/arch/x86/kernel/tsc_msr.c
@@ -92,7 +92,7 @@ unsigned long try_msr_calibrate_tsc(void)
 
 	if (freq_desc_tables[cpu_index].msr_plat) {
 		rdmsr(MSR_PLATFORM_INFO, lo, hi);
-		ratio = (lo >> 8) & 0x1f;
+		ratio = (lo >> 8) & 0xff;
 	} else {
 		rdmsr(MSR_IA32_PERF_STATUS, lo, hi);
 		ratio = (hi >> 8) & 0x1f;