* Updated Skylake Frontend profiling patchkit
@ 2015-06-30 23:33 Andi Kleen
2015-06-30 23:33 ` [PATCH 1/3] x86, perf: Make merge_attr global to use from perf_event_intel Andi Kleen
` (2 more replies)
0 siblings, 3 replies; 6+ messages in thread
From: Andi Kleen @ 2015-06-30 23:33 UTC (permalink / raw)
To: peterz; +Cc: linux-kernel
Reworked the extra reg test val patch to just change the default value.
^ permalink raw reply [flat|nested] 6+ messages in thread* [PATCH 1/3] x86, perf: Make merge_attr global to use from perf_event_intel 2015-06-30 23:33 Updated Skylake Frontend profiling patchkit Andi Kleen @ 2015-06-30 23:33 ` Andi Kleen 2015-06-30 23:33 ` [PATCH 2/3] x86, perf: Use 0x11 as extra reg test value Andi Kleen 2015-06-30 23:33 ` [PATCH 3/3] x86, perf: Add PEBS frontend profiling for Skylake Andi Kleen 2 siblings, 0 replies; 6+ messages in thread From: Andi Kleen @ 2015-06-30 23:33 UTC (permalink / raw) To: peterz; +Cc: linux-kernel, Andi Kleen From: Andi Kleen <ak@linux.intel.com> merge_attr allows to merge two sysfs attribute tables. Export it to be usable by other files too. Next patch is going to use that to extend the sysfs format attributes for a CPU. Signed-off-by: Andi Kleen <ak@linux.intel.com> --- arch/x86/kernel/cpu/perf_event.c | 2 +- arch/x86/kernel/cpu/perf_event.h | 3 +++ 2 files changed, 4 insertions(+), 1 deletion(-) diff --git a/arch/x86/kernel/cpu/perf_event.c b/arch/x86/kernel/cpu/perf_event.c index 5801a14..81e2a74 100644 --- a/arch/x86/kernel/cpu/perf_event.c +++ b/arch/x86/kernel/cpu/perf_event.c @@ -1561,7 +1561,7 @@ static void __init filter_events(struct attribute **attrs) } /* Merge two pointer arrays */ -static __init struct attribute **merge_attr(struct attribute **a, struct attribute **b) +__init struct attribute **merge_attr(struct attribute **a, struct attribute **b) { struct attribute **new; int j, i; diff --git a/arch/x86/kernel/cpu/perf_event.h b/arch/x86/kernel/cpu/perf_event.h index 0db9de4..3598f67 100644 --- a/arch/x86/kernel/cpu/perf_event.h +++ b/arch/x86/kernel/cpu/perf_event.h @@ -795,6 +795,8 @@ static inline void set_linear_ip(struct pt_regs *regs, unsigned long ip) ssize_t x86_event_sysfs_show(char *page, u64 config, u64 event); ssize_t intel_event_sysfs_show(char *page, u64 config); +struct attribute **merge_attr(struct attribute **a, struct attribute **b); + #ifdef CONFIG_CPU_SUP_AMD int amd_pmu_init(void); @@ -940,6 +942,7 @@ static inline int is_ht_workaround_enabled(void) { return !!(x86_pmu.flags & PMU_FL_EXCL_ENABLED); } + #else /* CONFIG_CPU_SUP_INTEL */ static inline void reserve_ds_buffers(void) -- 2.4.2 ^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH 2/3] x86, perf: Use 0x11 as extra reg test value 2015-06-30 23:33 Updated Skylake Frontend profiling patchkit Andi Kleen 2015-06-30 23:33 ` [PATCH 1/3] x86, perf: Make merge_attr global to use from perf_event_intel Andi Kleen @ 2015-06-30 23:33 ` Andi Kleen 2015-08-04 9:00 ` [tip:perf/core] perf/x86/intel: " tip-bot for Andi Kleen 2015-06-30 23:33 ` [PATCH 3/3] x86, perf: Add PEBS frontend profiling for Skylake Andi Kleen 2 siblings, 1 reply; 6+ messages in thread From: Andi Kleen @ 2015-06-30 23:33 UTC (permalink / raw) To: peterz; +Cc: linux-kernel, Andi Kleen From: Andi Kleen <ak@linux.intel.com> The next patch adds a new perf extra reg where 0x1ff is not a valid value. Use 0x11 instead. Signed-off-by: Andi Kleen <ak@linux.intel.com> --- arch/x86/kernel/cpu/perf_event_intel.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/x86/kernel/cpu/perf_event_intel.c b/arch/x86/kernel/cpu/perf_event_intel.c index 7c397e8..28b985c 100644 --- a/arch/x86/kernel/cpu/perf_event_intel.c +++ b/arch/x86/kernel/cpu/perf_event_intel.c @@ -3575,7 +3575,7 @@ __init int intel_pmu_init(void) */ if (x86_pmu.extra_regs) { for (er = x86_pmu.extra_regs; er->msr; er++) { - er->extra_msr_access = check_msr(er->msr, 0x1ffUL); + er->extra_msr_access = check_msr(er->msr, 0x11UL); /* Disable LBR select mapping */ if ((er->idx == EXTRA_REG_LBR) && !er->extra_msr_access) x86_pmu.lbr_sel_map = NULL; -- 2.4.2 ^ permalink raw reply [flat|nested] 6+ messages in thread
* [tip:perf/core] perf/x86/intel: Use 0x11 as extra reg test value 2015-06-30 23:33 ` [PATCH 2/3] x86, perf: Use 0x11 as extra reg test value Andi Kleen @ 2015-08-04 9:00 ` tip-bot for Andi Kleen 0 siblings, 0 replies; 6+ messages in thread From: tip-bot for Andi Kleen @ 2015-08-04 9:00 UTC (permalink / raw) To: linux-tip-commits; +Cc: mingo, hpa, torvalds, peterz, ak, tglx, linux-kernel Commit-ID: 8c4fe7095d633dd5543690ea5c3d522c5cd989b6 Gitweb: http://git.kernel.org/tip/8c4fe7095d633dd5543690ea5c3d522c5cd989b6 Author: Andi Kleen <ak@linux.intel.com> AuthorDate: Tue, 30 Jun 2015 16:33:24 -0700 Committer: Ingo Molnar <mingo@kernel.org> CommitDate: Tue, 4 Aug 2015 10:16:59 +0200 perf/x86/intel: Use 0x11 as extra reg test value The next patch adds a new perf extra register where 0x1ff is not a valid value. Use 0x11 instead. Signed-off-by: Andi Kleen <ak@linux.intel.com> Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Thomas Gleixner <tglx@linutronix.de> Link: http://lkml.kernel.org/r/1435707205-6676-3-git-send-email-andi@firstfloor.org Signed-off-by: Ingo Molnar <mingo@kernel.org> --- arch/x86/kernel/cpu/perf_event_intel.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/x86/kernel/cpu/perf_event_intel.c b/arch/x86/kernel/cpu/perf_event_intel.c index 28fc272..a478e3c 100644 --- a/arch/x86/kernel/cpu/perf_event_intel.c +++ b/arch/x86/kernel/cpu/perf_event_intel.c @@ -3579,7 +3579,7 @@ __init int intel_pmu_init(void) */ if (x86_pmu.extra_regs) { for (er = x86_pmu.extra_regs; er->msr; er++) { - er->extra_msr_access = check_msr(er->msr, 0x1ffUL); + er->extra_msr_access = check_msr(er->msr, 0x11UL); /* Disable LBR select mapping */ if ((er->idx == EXTRA_REG_LBR) && !er->extra_msr_access) x86_pmu.lbr_sel_map = NULL; ^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH 3/3] x86, perf: Add PEBS frontend profiling for Skylake 2015-06-30 23:33 Updated Skylake Frontend profiling patchkit Andi Kleen 2015-06-30 23:33 ` [PATCH 1/3] x86, perf: Make merge_attr global to use from perf_event_intel Andi Kleen 2015-06-30 23:33 ` [PATCH 2/3] x86, perf: Use 0x11 as extra reg test value Andi Kleen @ 2015-06-30 23:33 ` Andi Kleen 2015-09-18 8:46 ` [tip:perf/core] perf/x86/intel/pebs: " tip-bot for Andi Kleen 2 siblings, 1 reply; 6+ messages in thread From: Andi Kleen @ 2015-06-30 23:33 UTC (permalink / raw) To: peterz; +Cc: linux-kernel, Andi Kleen From: Andi Kleen <ak@linux.intel.com> Skylake has a new FRONTEND_LATENCY PEBS event to accurate profile frontend problems (like ITLB or decoding issues) The new event is configured through a separate MSR, which selects a range of sub events. Define the extra MSR as a extra reg and export support for it through sysfs. To avoid duplicating the existing tables use a new function to add new entries to existing tables. v2: Don't use custom test value. Signed-off-by: Andi Kleen <ak@linux.intel.com> --- arch/x86/include/asm/msr-index.h | 2 ++ arch/x86/kernel/cpu/perf_event.h | 1 + arch/x86/kernel/cpu/perf_event_intel.c | 11 ++++++++++- 3 files changed, 13 insertions(+), 1 deletion(-) diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h index 96a00de..a5371dc 100644 --- a/arch/x86/include/asm/msr-index.h +++ b/arch/x86/include/asm/msr-index.h @@ -133,6 +133,8 @@ #define DEBUGCTLMSR_BTS_OFF_USR (1UL << 10) #define DEBUGCTLMSR_FREEZE_LBRS_ON_PMI (1UL << 11) +#define MSR_PEBS_FRONTEND 0x000003f7 + #define MSR_IA32_POWER_CTL 0x000001fc #define MSR_IA32_MC0_CTL 0x00000400 diff --git a/arch/x86/kernel/cpu/perf_event.h b/arch/x86/kernel/cpu/perf_event.h index 3598f67..d9055c1 100644 --- a/arch/x86/kernel/cpu/perf_event.h +++ b/arch/x86/kernel/cpu/perf_event.h @@ -47,6 +47,7 @@ enum extra_reg_type { EXTRA_REG_RSP_1 = 1, /* offcore_response_1 */ EXTRA_REG_LBR = 2, /* lbr_select */ EXTRA_REG_LDLAT = 3, /* ld_lat_threshold */ + EXTRA_REG_FE = 4, /* fe_* */ EXTRA_REG_MAX /* number of entries needed */ }; diff --git a/arch/x86/kernel/cpu/perf_event_intel.c b/arch/x86/kernel/cpu/perf_event_intel.c index 28b985c..66e713e 100644 --- a/arch/x86/kernel/cpu/perf_event_intel.c +++ b/arch/x86/kernel/cpu/perf_event_intel.c @@ -205,6 +205,7 @@ static struct extra_reg intel_skl_extra_regs[] __read_mostly = { INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x3fffff8fffull, RSP_0), INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0x3fffff8fffull, RSP_1), INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd), + INTEL_UEVENT_EXTRA_REG(0x01c6, MSR_PEBS_FRONTEND, 0x3fff17, FE), EVENT_EXTRA_END }; @@ -2875,6 +2876,8 @@ PMU_FORMAT_ATTR(offcore_rsp, "config1:0-63"); PMU_FORMAT_ATTR(ldlat, "config1:0-15"); +PMU_FORMAT_ATTR(frontend, "config1:0-23"); + static struct attribute *intel_arch3_formats_attr[] = { &format_attr_event.attr, &format_attr_umask.attr, @@ -2891,6 +2894,11 @@ static struct attribute *intel_arch3_formats_attr[] = { NULL, }; +static struct attribute *skl_format_attr[] = { + &format_attr_frontend.attr, + NULL, +}; + static __initconst const struct x86_pmu core_pmu = { .name = "core", .handle_irq = x86_pmu_handle_irq, @@ -3500,7 +3508,8 @@ __init int intel_pmu_init(void) x86_pmu.hw_config = hsw_hw_config; x86_pmu.get_event_constraints = hsw_get_event_constraints; - x86_pmu.cpu_events = hsw_events_attrs; + x86_pmu.format_attrs = merge_attr(intel_arch3_formats_attr, + skl_format_attr); WARN_ON(!x86_pmu.format_attrs); x86_pmu.cpu_events = hsw_events_attrs; pr_cont("Skylake events, "); -- 2.4.2 ^ permalink raw reply [flat|nested] 6+ messages in thread
* [tip:perf/core] perf/x86/intel/pebs: Add PEBS frontend profiling for Skylake 2015-06-30 23:33 ` [PATCH 3/3] x86, perf: Add PEBS frontend profiling for Skylake Andi Kleen @ 2015-09-18 8:46 ` tip-bot for Andi Kleen 0 siblings, 0 replies; 6+ messages in thread From: tip-bot for Andi Kleen @ 2015-09-18 8:46 UTC (permalink / raw) To: linux-tip-commits; +Cc: hpa, linux-kernel, torvalds, mingo, peterz, tglx, ak Commit-ID: d0dc8494cd6904f8ad035d9ad97f313948f35d0c Gitweb: http://git.kernel.org/tip/d0dc8494cd6904f8ad035d9ad97f313948f35d0c Author: Andi Kleen <ak@linux.intel.com> AuthorDate: Wed, 9 Sep 2015 14:53:59 -0700 Committer: Ingo Molnar <mingo@kernel.org> CommitDate: Fri, 18 Sep 2015 09:20:22 +0200 perf/x86/intel/pebs: Add PEBS frontend profiling for Skylake Skylake has a new FRONTEND_LATENCY PEBS event to accurately profile frontend problems (like ITLB or decoding issues). The new event is configured through a separate MSR, which selects a range of sub events. Define the extra MSR as a extra reg and export support for it through sysfs. To avoid duplicating the existing tables use a new function to add new entries to existing tables. Signed-off-by: Andi Kleen <ak@linux.intel.com> Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Acked-by: Thomas Gleixner <tglx@linutronix.de> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Peter Zijlstra <peterz@infradead.org> Link: http://lkml.kernel.org/r/1435707205-6676-4-git-send-email-andi@firstfloor.org Signed-off-by: Ingo Molnar <mingo@kernel.org> --- arch/x86/include/asm/msr-index.h | 2 ++ arch/x86/kernel/cpu/perf_event.h | 1 + arch/x86/kernel/cpu/perf_event_intel.c | 11 ++++++++++- 3 files changed, 13 insertions(+), 1 deletion(-) diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h index c1c0a1c..54390bc 100644 --- a/arch/x86/include/asm/msr-index.h +++ b/arch/x86/include/asm/msr-index.h @@ -141,6 +141,8 @@ #define DEBUGCTLMSR_BTS_OFF_USR (1UL << 10) #define DEBUGCTLMSR_FREEZE_LBRS_ON_PMI (1UL << 11) +#define MSR_PEBS_FRONTEND 0x000003f7 + #define MSR_IA32_POWER_CTL 0x000001fc #define MSR_IA32_MC0_CTL 0x00000400 diff --git a/arch/x86/kernel/cpu/perf_event.h b/arch/x86/kernel/cpu/perf_event.h index 5edf6d8..165be83 100644 --- a/arch/x86/kernel/cpu/perf_event.h +++ b/arch/x86/kernel/cpu/perf_event.h @@ -47,6 +47,7 @@ enum extra_reg_type { EXTRA_REG_RSP_1 = 1, /* offcore_response_1 */ EXTRA_REG_LBR = 2, /* lbr_select */ EXTRA_REG_LDLAT = 3, /* ld_lat_threshold */ + EXTRA_REG_FE = 4, /* fe_* */ EXTRA_REG_MAX /* number of entries needed */ }; diff --git a/arch/x86/kernel/cpu/perf_event_intel.c b/arch/x86/kernel/cpu/perf_event_intel.c index 1d84b41..ef74c9d 100644 --- a/arch/x86/kernel/cpu/perf_event_intel.c +++ b/arch/x86/kernel/cpu/perf_event_intel.c @@ -205,6 +205,7 @@ static struct extra_reg intel_skl_extra_regs[] __read_mostly = { INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x3fffff8fffull, RSP_0), INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0x3fffff8fffull, RSP_1), INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd), + INTEL_UEVENT_EXTRA_REG(0x01c6, MSR_PEBS_FRONTEND, 0x3fff17, FE), EVENT_EXTRA_END }; @@ -2891,6 +2892,8 @@ PMU_FORMAT_ATTR(offcore_rsp, "config1:0-63"); PMU_FORMAT_ATTR(ldlat, "config1:0-15"); +PMU_FORMAT_ATTR(frontend, "config1:0-23"); + static struct attribute *intel_arch3_formats_attr[] = { &format_attr_event.attr, &format_attr_umask.attr, @@ -2907,6 +2910,11 @@ static struct attribute *intel_arch3_formats_attr[] = { NULL, }; +static struct attribute *skl_format_attr[] = { + &format_attr_frontend.attr, + NULL, +}; + static __initconst const struct x86_pmu core_pmu = { .name = "core", .handle_irq = x86_pmu_handle_irq, @@ -3516,7 +3524,8 @@ __init int intel_pmu_init(void) x86_pmu.hw_config = hsw_hw_config; x86_pmu.get_event_constraints = hsw_get_event_constraints; - x86_pmu.cpu_events = hsw_events_attrs; + x86_pmu.format_attrs = merge_attr(intel_arch3_formats_attr, + skl_format_attr); WARN_ON(!x86_pmu.format_attrs); x86_pmu.cpu_events = hsw_events_attrs; pr_cont("Skylake events, "); ^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2015-09-18 8:47 UTC | newest] Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2015-06-30 23:33 Updated Skylake Frontend profiling patchkit Andi Kleen 2015-06-30 23:33 ` [PATCH 1/3] x86, perf: Make merge_attr global to use from perf_event_intel Andi Kleen 2015-06-30 23:33 ` [PATCH 2/3] x86, perf: Use 0x11 as extra reg test value Andi Kleen 2015-08-04 9:00 ` [tip:perf/core] perf/x86/intel: " tip-bot for Andi Kleen 2015-06-30 23:33 ` [PATCH 3/3] x86, perf: Add PEBS frontend profiling for Skylake Andi Kleen 2015-09-18 8:46 ` [tip:perf/core] perf/x86/intel/pebs: " tip-bot for Andi Kleen
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