From: tip-bot for Janakarajan Natarajan <tipbot@zytor.com>
To: linux-tip-commits@vger.kernel.org
Cc: peterz@infradead.org, hpa@zytor.com,
alexander.shishkin@linux.intel.com,
Janakarajan.Natarajan@amd.com, tglx@linutronix.de,
torvalds@linux-foundation.org, mingo@kernel.org,
linux-kernel@vger.kernel.org, suravee.suthikulpanit@amd.com,
acme@kernel.org, bp@suse.de
Subject: [tip:perf/core] perf/x86/amd/uncore: Rename cpufeatures macro for cache counters
Date: Thu, 10 Aug 2017 05:02:33 -0700 [thread overview]
Message-ID: <tip-910448bbed066ab1082b510eef1ae61bb792d854@git.kernel.org> (raw)
In-Reply-To: <016311029fdecdc3fdc13b7ed865c6cbf48b2f15.1497452002.git.Janakarajan.Natarajan@amd.com>
Commit-ID: 910448bbed066ab1082b510eef1ae61bb792d854
Gitweb: http://git.kernel.org/tip/910448bbed066ab1082b510eef1ae61bb792d854
Author: Janakarajan Natarajan <Janakarajan.Natarajan@amd.com>
AuthorDate: Wed, 14 Jun 2017 11:26:57 -0500
Committer: Ingo Molnar <mingo@kernel.org>
CommitDate: Thu, 10 Aug 2017 12:08:38 +0200
perf/x86/amd/uncore: Rename cpufeatures macro for cache counters
In Family 17h, L3 is the last level cache as opposed to L2 in previous
families. Avoid this name confusion and rename X86_FEATURE_PERFCTR_L2 to
X86_FEATURE_PERFCTR_LLC to indicate the performance counter on the last
level of cache.
Signed-off-by: Janakarajan Natarajan <Janakarajan.Natarajan@amd.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Reviewed-by: Borislav Petkov <bp@suse.de>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Arnaldo Carvalho de Melo <acme@kernel.org>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
Cc: Thomas Gleixner <tglx@linutronix.de>
Link: http://lkml.kernel.org/r/016311029fdecdc3fdc13b7ed865c6cbf48b2f15.1497452002.git.Janakarajan.Natarajan@amd.com
Signed-off-by: Ingo Molnar <mingo@kernel.org>
---
arch/x86/events/amd/uncore.c | 2 +-
arch/x86/include/asm/cpufeatures.h | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/x86/events/amd/uncore.c b/arch/x86/events/amd/uncore.c
index ad44af0..e34f8a6 100644
--- a/arch/x86/events/amd/uncore.c
+++ b/arch/x86/events/amd/uncore.c
@@ -555,7 +555,7 @@ static int __init amd_uncore_init(void)
ret = 0;
}
- if (boot_cpu_has(X86_FEATURE_PERFCTR_L2)) {
+ if (boot_cpu_has(X86_FEATURE_PERFCTR_LLC)) {
amd_uncore_llc = alloc_percpu(struct amd_uncore *);
if (!amd_uncore_llc) {
ret = -ENOMEM;
diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h
index ca3c48c..73a7127 100644
--- a/arch/x86/include/asm/cpufeatures.h
+++ b/arch/x86/include/asm/cpufeatures.h
@@ -177,7 +177,7 @@
#define X86_FEATURE_PERFCTR_NB ( 6*32+24) /* NB performance counter extensions */
#define X86_FEATURE_BPEXT (6*32+26) /* data breakpoint extension */
#define X86_FEATURE_PTSC ( 6*32+27) /* performance time-stamp counter */
-#define X86_FEATURE_PERFCTR_L2 ( 6*32+28) /* L2 performance counter extensions */
+#define X86_FEATURE_PERFCTR_LLC ( 6*32+28) /* Last Level Cache performance counter extensions */
#define X86_FEATURE_MWAITX ( 6*32+29) /* MWAIT extension (MONITORX/MWAITX) */
/*
next prev parent reply other threads:[~2017-08-10 12:07 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-06-14 16:26 [PATCH v4 0/2] amd: uncore: Fix for AMD Uncore driver Janakarajan Natarajan
2017-06-14 16:26 ` [PATCH v4 1/2] amd: uncore: Rename cpufeatures macro for cache counters Janakarajan Natarajan
2017-08-10 12:02 ` tip-bot for Janakarajan Natarajan [this message]
2017-06-14 16:26 ` [PATCH v4 2/2] amd: uncore: Get correct number of cores sharing last level cache Janakarajan Natarajan
2017-06-15 8:40 ` Borislav Petkov
2017-08-10 12:02 ` [tip:perf/core] perf/x86/amd/uncore: " tip-bot for Janakarajan Natarajan
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