* [PATCH v4 0/2] amd: uncore: Fix for AMD Uncore driver @ 2017-06-14 16:26 Janakarajan Natarajan 2017-06-14 16:26 ` [PATCH v4 1/2] amd: uncore: Rename cpufeatures macro for cache counters Janakarajan Natarajan 2017-06-14 16:26 ` [PATCH v4 2/2] amd: uncore: Get correct number of cores sharing last level cache Janakarajan Natarajan 0 siblings, 2 replies; 6+ messages in thread From: Janakarajan Natarajan @ 2017-06-14 16:26 UTC (permalink / raw) To: linux-kernel Cc: Peter Zijlstra, Ingo Molnar, Arnaldo Carvalho de Melo, Alexander Shishkin, Borislav Petkov, Suravee Suthikulpanit, Janakarajan Natarajan The following series provides fixes for the AMD Uncore driver. * Renamed cache counters cpufeatures macro to better reflect different last level cache for different families. * Get correct information about number of cores sharing last level of cache. v3->v4 * Code cleanup with checkpatch.pl and added Reviewed-by tag in patch description. v2->v3 * Updated patch description and cleaned up code based on feedback from Borislav Petkov. v1->v2 * Replaced while(1) with finite for loop based on feedback from Peter Zijlstra and Borislav Petkov. Janakarajan Natarajan (2): amd: uncore: Rename cpufeatures macro for cache counters amd: uncore: Get correct number of cores sharing last level cache arch/x86/events/amd/uncore.c | 21 +++++++++++++++++---- arch/x86/include/asm/cpufeatures.h | 2 +- 2 files changed, 18 insertions(+), 5 deletions(-) -- 2.7.4 ^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH v4 1/2] amd: uncore: Rename cpufeatures macro for cache counters 2017-06-14 16:26 [PATCH v4 0/2] amd: uncore: Fix for AMD Uncore driver Janakarajan Natarajan @ 2017-06-14 16:26 ` Janakarajan Natarajan 2017-08-10 12:02 ` [tip:perf/core] perf/x86/amd/uncore: " tip-bot for Janakarajan Natarajan 2017-06-14 16:26 ` [PATCH v4 2/2] amd: uncore: Get correct number of cores sharing last level cache Janakarajan Natarajan 1 sibling, 1 reply; 6+ messages in thread From: Janakarajan Natarajan @ 2017-06-14 16:26 UTC (permalink / raw) To: linux-kernel Cc: Peter Zijlstra, Ingo Molnar, Arnaldo Carvalho de Melo, Alexander Shishkin, Borislav Petkov, Suravee Suthikulpanit, Janakarajan Natarajan In Family 17h, L3 is the last level cache as opposed to L2 in previous families. Avoid this name confusion and rename X86_FEATURE_PERFCTR_L2 to X86_FEATURE_PERFCTR_LLC to indicate the performance counter on the last level of cache. Signed-off-by: Janakarajan Natarajan <Janakarajan.Natarajan@amd.com> Reviewed-by: Borislav Petkov <bp@suse.de> --- arch/x86/events/amd/uncore.c | 2 +- arch/x86/include/asm/cpufeatures.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/x86/events/amd/uncore.c b/arch/x86/events/amd/uncore.c index ad44af0..e34f8a6 100644 --- a/arch/x86/events/amd/uncore.c +++ b/arch/x86/events/amd/uncore.c @@ -555,7 +555,7 @@ static int __init amd_uncore_init(void) ret = 0; } - if (boot_cpu_has(X86_FEATURE_PERFCTR_L2)) { + if (boot_cpu_has(X86_FEATURE_PERFCTR_LLC)) { amd_uncore_llc = alloc_percpu(struct amd_uncore *); if (!amd_uncore_llc) { ret = -ENOMEM; diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h index 2701e5f..e3f3d0c 100644 --- a/arch/x86/include/asm/cpufeatures.h +++ b/arch/x86/include/asm/cpufeatures.h @@ -177,7 +177,7 @@ #define X86_FEATURE_PERFCTR_NB ( 6*32+24) /* NB performance counter extensions */ #define X86_FEATURE_BPEXT (6*32+26) /* data breakpoint extension */ #define X86_FEATURE_PTSC ( 6*32+27) /* performance time-stamp counter */ -#define X86_FEATURE_PERFCTR_L2 ( 6*32+28) /* L2 performance counter extensions */ +#define X86_FEATURE_PERFCTR_LLC ( 6*32+28) /* Last Level Cache performance counter extensions */ #define X86_FEATURE_MWAITX ( 6*32+29) /* MWAIT extension (MONITORX/MWAITX) */ /* -- 2.7.4 ^ permalink raw reply [flat|nested] 6+ messages in thread
* [tip:perf/core] perf/x86/amd/uncore: Rename cpufeatures macro for cache counters 2017-06-14 16:26 ` [PATCH v4 1/2] amd: uncore: Rename cpufeatures macro for cache counters Janakarajan Natarajan @ 2017-08-10 12:02 ` tip-bot for Janakarajan Natarajan 0 siblings, 0 replies; 6+ messages in thread From: tip-bot for Janakarajan Natarajan @ 2017-08-10 12:02 UTC (permalink / raw) To: linux-tip-commits Cc: peterz, hpa, alexander.shishkin, Janakarajan.Natarajan, tglx, torvalds, mingo, linux-kernel, suravee.suthikulpanit, acme, bp Commit-ID: 910448bbed066ab1082b510eef1ae61bb792d854 Gitweb: http://git.kernel.org/tip/910448bbed066ab1082b510eef1ae61bb792d854 Author: Janakarajan Natarajan <Janakarajan.Natarajan@amd.com> AuthorDate: Wed, 14 Jun 2017 11:26:57 -0500 Committer: Ingo Molnar <mingo@kernel.org> CommitDate: Thu, 10 Aug 2017 12:08:38 +0200 perf/x86/amd/uncore: Rename cpufeatures macro for cache counters In Family 17h, L3 is the last level cache as opposed to L2 in previous families. Avoid this name confusion and rename X86_FEATURE_PERFCTR_L2 to X86_FEATURE_PERFCTR_LLC to indicate the performance counter on the last level of cache. Signed-off-by: Janakarajan Natarajan <Janakarajan.Natarajan@amd.com> Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Reviewed-by: Borislav Petkov <bp@suse.de> Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com> Cc: Arnaldo Carvalho de Melo <acme@kernel.org> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com> Cc: Thomas Gleixner <tglx@linutronix.de> Link: http://lkml.kernel.org/r/016311029fdecdc3fdc13b7ed865c6cbf48b2f15.1497452002.git.Janakarajan.Natarajan@amd.com Signed-off-by: Ingo Molnar <mingo@kernel.org> --- arch/x86/events/amd/uncore.c | 2 +- arch/x86/include/asm/cpufeatures.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/x86/events/amd/uncore.c b/arch/x86/events/amd/uncore.c index ad44af0..e34f8a6 100644 --- a/arch/x86/events/amd/uncore.c +++ b/arch/x86/events/amd/uncore.c @@ -555,7 +555,7 @@ static int __init amd_uncore_init(void) ret = 0; } - if (boot_cpu_has(X86_FEATURE_PERFCTR_L2)) { + if (boot_cpu_has(X86_FEATURE_PERFCTR_LLC)) { amd_uncore_llc = alloc_percpu(struct amd_uncore *); if (!amd_uncore_llc) { ret = -ENOMEM; diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h index ca3c48c..73a7127 100644 --- a/arch/x86/include/asm/cpufeatures.h +++ b/arch/x86/include/asm/cpufeatures.h @@ -177,7 +177,7 @@ #define X86_FEATURE_PERFCTR_NB ( 6*32+24) /* NB performance counter extensions */ #define X86_FEATURE_BPEXT (6*32+26) /* data breakpoint extension */ #define X86_FEATURE_PTSC ( 6*32+27) /* performance time-stamp counter */ -#define X86_FEATURE_PERFCTR_L2 ( 6*32+28) /* L2 performance counter extensions */ +#define X86_FEATURE_PERFCTR_LLC ( 6*32+28) /* Last Level Cache performance counter extensions */ #define X86_FEATURE_MWAITX ( 6*32+29) /* MWAIT extension (MONITORX/MWAITX) */ /* ^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH v4 2/2] amd: uncore: Get correct number of cores sharing last level cache 2017-06-14 16:26 [PATCH v4 0/2] amd: uncore: Fix for AMD Uncore driver Janakarajan Natarajan 2017-06-14 16:26 ` [PATCH v4 1/2] amd: uncore: Rename cpufeatures macro for cache counters Janakarajan Natarajan @ 2017-06-14 16:26 ` Janakarajan Natarajan 2017-06-15 8:40 ` Borislav Petkov 2017-08-10 12:02 ` [tip:perf/core] perf/x86/amd/uncore: " tip-bot for Janakarajan Natarajan 1 sibling, 2 replies; 6+ messages in thread From: Janakarajan Natarajan @ 2017-06-14 16:26 UTC (permalink / raw) To: linux-kernel Cc: Peter Zijlstra, Ingo Molnar, Arnaldo Carvalho de Melo, Alexander Shishkin, Borislav Petkov, Suravee Suthikulpanit, Janakarajan Natarajan In Family 17h, the number of cores sharing a cache level is obtained from the Cache Properties CPUID leaf (0x8000001d) by passing in the cache level in ECX. In prior families, a cache level of 2 was used to determine this information. To get the right information, irrespective of Family, iterate over the cache levels using CPUID 0x8000001d. The last level cache is the last value to return a non-zero value in EAX. Signed-off-by: Janakarajan Natarajan <Janakarajan.Natarajan@amd.com> --- arch/x86/events/amd/uncore.c | 19 ++++++++++++++++--- 1 file changed, 16 insertions(+), 3 deletions(-) diff --git a/arch/x86/events/amd/uncore.c b/arch/x86/events/amd/uncore.c index e34f8a6..f5cbbba 100644 --- a/arch/x86/events/amd/uncore.c +++ b/arch/x86/events/amd/uncore.c @@ -400,11 +400,24 @@ static int amd_uncore_cpu_starting(unsigned int cpu) if (amd_uncore_llc) { unsigned int apicid = cpu_data(cpu).apicid; - unsigned int nshared; + unsigned int nshared, subleaf, prev_eax = 0; uncore = *per_cpu_ptr(amd_uncore_llc, cpu); - cpuid_count(0x8000001d, 2, &eax, &ebx, &ecx, &edx); - nshared = ((eax >> 14) & 0xfff) + 1; + /* + * Iterate over Cache Topology Definition leaves until no + * more cache descriptions are available. + */ + for (subleaf = 0; subleaf < 5; subleaf++) { + cpuid_count(0x8000001d, subleaf, &eax, &ebx, &ecx, &edx); + + /* EAX[0:4] gives type of cache */ + if (!(eax & 0x1f)) + break; + + prev_eax = eax; + } + nshared = ((prev_eax >> 14) & 0xfff) + 1; + uncore->id = apicid - (apicid % nshared); uncore = amd_uncore_find_online_sibling(uncore, amd_uncore_llc); -- 2.7.4 ^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH v4 2/2] amd: uncore: Get correct number of cores sharing last level cache 2017-06-14 16:26 ` [PATCH v4 2/2] amd: uncore: Get correct number of cores sharing last level cache Janakarajan Natarajan @ 2017-06-15 8:40 ` Borislav Petkov 2017-08-10 12:02 ` [tip:perf/core] perf/x86/amd/uncore: " tip-bot for Janakarajan Natarajan 1 sibling, 0 replies; 6+ messages in thread From: Borislav Petkov @ 2017-06-15 8:40 UTC (permalink / raw) To: Janakarajan Natarajan Cc: linux-kernel, Peter Zijlstra, Ingo Molnar, Arnaldo Carvalho de Melo, Alexander Shishkin, Suravee Suthikulpanit On Wed, Jun 14, 2017 at 11:26:58AM -0500, Janakarajan Natarajan wrote: > In Family 17h, the number of cores sharing a cache level is obtained > from the Cache Properties CPUID leaf (0x8000001d) by passing in the > cache level in ECX. In prior families, a cache level of 2 was used to > determine this information. > > To get the right information, irrespective of Family, iterate over > the cache levels using CPUID 0x8000001d. The last level cache is the > last value to return a non-zero value in EAX. > > Signed-off-by: Janakarajan Natarajan <Janakarajan.Natarajan@amd.com> > --- > arch/x86/events/amd/uncore.c | 19 ++++++++++++++++--- > 1 file changed, 16 insertions(+), 3 deletions(-) Reviewed-by: Borislav Petkov <bp@suse.de> -- Regards/Gruss, Boris. Good mailing practices for 400: avoid top-posting and trim the reply. ^ permalink raw reply [flat|nested] 6+ messages in thread
* [tip:perf/core] perf/x86/amd/uncore: Get correct number of cores sharing last level cache 2017-06-14 16:26 ` [PATCH v4 2/2] amd: uncore: Get correct number of cores sharing last level cache Janakarajan Natarajan 2017-06-15 8:40 ` Borislav Petkov @ 2017-08-10 12:02 ` tip-bot for Janakarajan Natarajan 1 sibling, 0 replies; 6+ messages in thread From: tip-bot for Janakarajan Natarajan @ 2017-08-10 12:02 UTC (permalink / raw) To: linux-tip-commits Cc: tglx, hpa, suravee.suthikulpanit, Janakarajan.Natarajan, alexander.shishkin, torvalds, mingo, acme, bp, linux-kernel, peterz Commit-ID: ab027620e95987b5f0145013090a109b4152d23b Gitweb: http://git.kernel.org/tip/ab027620e95987b5f0145013090a109b4152d23b Author: Janakarajan Natarajan <Janakarajan.Natarajan@amd.com> AuthorDate: Wed, 14 Jun 2017 11:26:58 -0500 Committer: Ingo Molnar <mingo@kernel.org> CommitDate: Thu, 10 Aug 2017 12:08:39 +0200 perf/x86/amd/uncore: Get correct number of cores sharing last level cache In Family 17h, the number of cores sharing a cache level is obtained from the Cache Properties CPUID leaf (0x8000001d) by passing in the cache level in ECX. In prior families, a cache level of 2 was used to determine this information. To get the right information, irrespective of Family, iterate over the cache levels using CPUID 0x8000001d. The last level cache is the last value to return a non-zero value in EAX. Signed-off-by: Janakarajan Natarajan <Janakarajan.Natarajan@amd.com> Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Reviewed-by: Borislav Petkov <bp@suse.de> Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com> Cc: Arnaldo Carvalho de Melo <acme@kernel.org> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com> Cc: Thomas Gleixner <tglx@linutronix.de> Link: http://lkml.kernel.org/r/5ab569025b39cdfaeca55b571d78c0fc800bdb69.1497452002.git.Janakarajan.Natarajan@amd.com Signed-off-by: Ingo Molnar <mingo@kernel.org> --- arch/x86/events/amd/uncore.c | 19 ++++++++++++++++--- 1 file changed, 16 insertions(+), 3 deletions(-) diff --git a/arch/x86/events/amd/uncore.c b/arch/x86/events/amd/uncore.c index e34f8a6..f5cbbba 100644 --- a/arch/x86/events/amd/uncore.c +++ b/arch/x86/events/amd/uncore.c @@ -400,11 +400,24 @@ static int amd_uncore_cpu_starting(unsigned int cpu) if (amd_uncore_llc) { unsigned int apicid = cpu_data(cpu).apicid; - unsigned int nshared; + unsigned int nshared, subleaf, prev_eax = 0; uncore = *per_cpu_ptr(amd_uncore_llc, cpu); - cpuid_count(0x8000001d, 2, &eax, &ebx, &ecx, &edx); - nshared = ((eax >> 14) & 0xfff) + 1; + /* + * Iterate over Cache Topology Definition leaves until no + * more cache descriptions are available. + */ + for (subleaf = 0; subleaf < 5; subleaf++) { + cpuid_count(0x8000001d, subleaf, &eax, &ebx, &ecx, &edx); + + /* EAX[0:4] gives type of cache */ + if (!(eax & 0x1f)) + break; + + prev_eax = eax; + } + nshared = ((prev_eax >> 14) & 0xfff) + 1; + uncore->id = apicid - (apicid % nshared); uncore = amd_uncore_find_online_sibling(uncore, amd_uncore_llc); ^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2017-08-10 12:07 UTC | newest] Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2017-06-14 16:26 [PATCH v4 0/2] amd: uncore: Fix for AMD Uncore driver Janakarajan Natarajan 2017-06-14 16:26 ` [PATCH v4 1/2] amd: uncore: Rename cpufeatures macro for cache counters Janakarajan Natarajan 2017-08-10 12:02 ` [tip:perf/core] perf/x86/amd/uncore: " tip-bot for Janakarajan Natarajan 2017-06-14 16:26 ` [PATCH v4 2/2] amd: uncore: Get correct number of cores sharing last level cache Janakarajan Natarajan 2017-06-15 8:40 ` Borislav Petkov 2017-08-10 12:02 ` [tip:perf/core] perf/x86/amd/uncore: " tip-bot for Janakarajan Natarajan
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