[PATCH] x86, cpufeature: add feature bit for SDBG

[PATCH] x86, cpufeature: add feature bit for SDBG

[Mathias Krause]

Add a CPUID feature bit for the SDBG (Silicon Debug) CPU feature found
on recent Intel systems starting with Haswell.

Using the IA32_DEBUG_INTERFACE MSR (index C80H) one can at least detect
if SDBG has been enabled by the firmware and if it has been used or not.

Signed-off-by: Mathias Krause <minipli@googlemail.com>
Cc: Borislav Petkov <bp@alien8.de>
Cc: H. Peter Anvin <hpa@zytor.com>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Thomas Gleixner <tglx@linutronix.de>
---
 arch/x86/include/asm/cpufeature.h |    1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/x86/include/asm/cpufeature.h b/arch/x86/include/asm/cpufeature.h
index 3d6606fb97d0..4b11974b4ea7 100644
--- a/arch/x86/include/asm/cpufeature.h
+++ b/arch/x86/include/asm/cpufeature.h
@@ -119,6 +119,7 @@
 #define X86_FEATURE_TM2		( 4*32+ 8) /* Thermal Monitor 2 */
 #define X86_FEATURE_SSSE3	( 4*32+ 9) /* Supplemental SSE-3 */
 #define X86_FEATURE_CID		( 4*32+10) /* Context ID */
+#define X86_FEATURE_SDBG	( 4*32+11) /* Silicon Debug */
 #define X86_FEATURE_FMA		( 4*32+12) /* Fused multiply-add */
 #define X86_FEATURE_CX16	( 4*32+13) /* CMPXCHG16B */
 #define X86_FEATURE_XTPR	( 4*32+14) /* Send Task Priority Messages */
-- 
1.7.10.4

Re: [PATCH] x86, cpufeature: add feature bit for SDBG

[Borislav Petkov]

On Sun, Jul 19, 2015 at 08:26:43PM +0200, Mathias Krause wrote:
> Add a CPUID feature bit for the SDBG (Silicon Debug) CPU feature found
> on recent Intel systems starting with Haswell.
> 
> Using the IA32_DEBUG_INTERFACE MSR (index C80H) one can at least detect
> if SDBG has been enabled by the firmware and if it has been used or not.
> 
> Signed-off-by: Mathias Krause <minipli@googlemail.com>
> Cc: Borislav Petkov <bp@alien8.de>
> Cc: H. Peter Anvin <hpa@zytor.com>
> Cc: Ingo Molnar <mingo@redhat.com>
> Cc: Thomas Gleixner <tglx@linutronix.de>
> ---
>  arch/x86/include/asm/cpufeature.h |    1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/arch/x86/include/asm/cpufeature.h b/arch/x86/include/asm/cpufeature.h
> index 3d6606fb97d0..4b11974b4ea7 100644
> --- a/arch/x86/include/asm/cpufeature.h
> +++ b/arch/x86/include/asm/cpufeature.h
> @@ -119,6 +119,7 @@
>  #define X86_FEATURE_TM2		( 4*32+ 8) /* Thermal Monitor 2 */
>  #define X86_FEATURE_SSSE3	( 4*32+ 9) /* Supplemental SSE-3 */
>  #define X86_FEATURE_CID		( 4*32+10) /* Context ID */
> +#define X86_FEATURE_SDBG	( 4*32+11) /* Silicon Debug */
>  #define X86_FEATURE_FMA		( 4*32+12) /* Fused multiply-add */
>  #define X86_FEATURE_CX16	( 4*32+13) /* CMPXCHG16B */
>  #define X86_FEATURE_XTPR	( 4*32+14) /* Send Task Priority Messages */

Acked-by: Borislav Petkov <bp@suse.de>

-- 
Regards/Gruss,
    Boris.

ECO tip #101: Trim your mails when you reply.
--

Re: [PATCH] x86, cpufeature: add feature bit for SDBG

[Borislav Petkov]

On Mon, Jul 20, 2015 at 01:54:05PM +0200, Borislav Petkov wrote:
> Acked-by: Borislav Petkov <bp@suse.de>

... and applied, thanks.

-- 
Regards/Gruss,
    Boris.

ECO tip #101: Trim your mails when you reply.
--

[tip:x86/cpu] x86/cpufeature: Add feature bit for Intel' s Silicon Debug CPUID bit

[tip-bot for Mathias Krause]

Commit-ID:  b1c599b8ff80ea79b9f8277a3f9f36a7b0cfedce
Gitweb:     http://git.kernel.org/tip/b1c599b8ff80ea79b9f8277a3f9f36a7b0cfedce
Author:     Mathias Krause <minipli@googlemail.com>
AuthorDate: Fri, 24 Jul 2015 09:15:11 +0200
Committer:  Ingo Molnar <mingo@kernel.org>
CommitDate: Fri, 31 Jul 2015 10:34:07 +0200

x86/cpufeature: Add feature bit for Intel's Silicon Debug CPUID bit

Add a CPUID feature bit for the SDBG (Silicon Debug) CPU feature
found on recent Intel systems starting with Haswell.

Using the IA32_DEBUG_INTERFACE MSR (index C80H) one can at least
detect if SDBG has been enabled by the firmware and if it has
been used or not.

Signed-off-by: Mathias Krause <minipli@googlemail.com>
Signed-off-by: Borislav Petkov <bp@suse.de>
Cc: Aaron Lu <aaron.lu@intel.com>
Cc: Dave Hansen <dave.hansen@linux.intel.com>
Cc: Dirk Brandewie <dirk.j.brandewie@intel.com>
Cc: H. Peter Anvin <hpa@zytor.com>
Cc: Josh Triplett <josh@joshtriplett.org>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Ross Zwisler <ross.zwisler@linux.intel.com>
Cc: Thomas Gleixner <tglx@linutronix.de>
Link: http://lkml.kernel.org/r/1437330403-12102-1-git-send-email-minipli@googlemail.com
Signed-off-by: Ingo Molnar <mingo@kernel.org>
---
 arch/x86/include/asm/cpufeature.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/x86/include/asm/cpufeature.h b/arch/x86/include/asm/cpufeature.h
index 3d6606f..4b11974 100644
--- a/arch/x86/include/asm/cpufeature.h
+++ b/arch/x86/include/asm/cpufeature.h
@@ -119,6 +119,7 @@
 #define X86_FEATURE_TM2		( 4*32+ 8) /* Thermal Monitor 2 */
 #define X86_FEATURE_SSSE3	( 4*32+ 9) /* Supplemental SSE-3 */
 #define X86_FEATURE_CID		( 4*32+10) /* Context ID */
+#define X86_FEATURE_SDBG	( 4*32+11) /* Silicon Debug */
 #define X86_FEATURE_FMA		( 4*32+12) /* Fused multiply-add */
 #define X86_FEATURE_CX16	( 4*32+13) /* CMPXCHG16B */
 #define X86_FEATURE_XTPR	( 4*32+14) /* Send Task Priority Messages */