[PATCH] gpu: host1x: mipi: Disable clock again after powering down the pads

[PATCH] gpu: host1x: mipi: Disable clock again after powering down the pads

[Patrick Fischer via B4 Relay]

From: Patrick Fischer <admin@tsv-stahl-riesa.de>

tegra114_mipi_power_down() enables the MIPI calibration clock to access
the bias pad registers but never disables it. Every disable/enable cycle
of a DSI or CSI user therefore leaks one enable count, and the clock
stays on for good after the first power down.

Add the missing clk_disable(), matching tegra114_mipi_power_up().

The leak gets more costly with "clk: tegra: Fix Tegra114 MIPI
calibration clock parent", which makes PLL_P_OUT3 the parent of
mipi-cal: without this fix PLL_P_OUT3 would then stay on as well.

On a Tegra Note 7 (P1640) the enable count of mipi-cal in clk_summary
grew by one with each DPMS off/on cycle of the DSI panel. With this
patch it returns to 0 after each cycle.

Fixes: 15372d4be7f0 ("gpu: host1x: mipi: Power down regulators when unused")
Signed-off-by: Patrick Fischer <admin@tsv-stahl-riesa.de>
---
Mikko's "clk: tegra: Fix Tegra114 MIPI calibration clock parent" [1]
fixes the MIPI calibration timeouts on Tegra114. While testing the same
change on a Tegra Note 7 (P1640) I noticed that
tegra114_mipi_power_down() leaks the clock enable it takes. With [1]
applied that leak keeps PLL_P_OUT3 on after the first DPMS off, so the
two belong together, although this patch applies and makes sense on
its own.

[1] https://lore.kernel.org/all/20260930-b4-dalmore-fixes-mipical-clk-v1-1-0518be6c7979@nvidia.com/

Tool use (see Documentation/process/generated-content.rst): this patch,
its changelog and this note were prepared with an LLM coding assistant
(Claude Code). It traced the clock enable counts from my clk_summary
dumps and wrote the code change and the texts from my measurements and
instructions. I reviewed the change and ran the test on the device.
---
 drivers/gpu/host1x/tegra114-mipi.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/gpu/host1x/tegra114-mipi.c b/drivers/gpu/host1x/tegra114-mipi.c
index c084a09784d1..83a43a5e33af 100644
--- a/drivers/gpu/host1x/tegra114-mipi.c
+++ b/drivers/gpu/host1x/tegra114-mipi.c
@@ -197,6 +197,8 @@ static int tegra114_mipi_power_down(struct tegra_mipi *mipi)
 	value |= MIPI_CAL_BIAS_PAD_PDVCLAMP;
 	tegra_mipi_writel(mipi, value, MIPI_CAL_BIAS_PAD_CFG0);
 
+	clk_disable(mipi->clk);
+
 	return 0;
 }
 

---
base-commit: 734bef548a96e8774d6eef5dfa2026c6edc4e80b
change-id: 20261025-upstream-host1x-mipi-clk-867edad177b0

Best regards,
--  
Patrick Fischer <admin@tsv-stahl-riesa.de>

Re: [PATCH] gpu: host1x: mipi: Disable clock again after powering down the pads

[Svyatoslav Ryhel]

нд, 25 жовт. 2026 р. о 19:13 Patrick Fischer via B4 Relay
<devnull+admin.tsv-stahl-riesa.de@kernel.org> пише:
>
> From: Patrick Fischer <admin@tsv-stahl-riesa.de>
>
> tegra114_mipi_power_down() enables the MIPI calibration clock to access
> the bias pad registers but never disables it. Every disable/enable cycle
> of a DSI or CSI user therefore leaks one enable count, and the clock
> stays on for good after the first power down.
>
> Add the missing clk_disable(), matching tegra114_mipi_power_up().
>
> The leak gets more costly with "clk: tegra: Fix Tegra114 MIPI
> calibration clock parent", which makes PLL_P_OUT3 the parent of
> mipi-cal: without this fix PLL_P_OUT3 would then stay on as well.
>
> On a Tegra Note 7 (P1640) the enable count of mipi-cal in clk_summary
> grew by one with each DPMS off/on cycle of the DSI panel. With this
> patch it returns to 0 after each cycle.
>
> Fixes: 15372d4be7f0 ("gpu: host1x: mipi: Power down regulators when unused")
> Signed-off-by: Patrick Fischer <admin@tsv-stahl-riesa.de>
> ---
> Mikko's "clk: tegra: Fix Tegra114 MIPI calibration clock parent" [1]
> fixes the MIPI calibration timeouts on Tegra114. While testing the same
> change on a Tegra Note 7 (P1640) I noticed that
> tegra114_mipi_power_down() leaks the clock enable it takes. With [1]
> applied that leak keeps PLL_P_OUT3 on after the first DPMS off, so the
> two belong together, although this patch applies and makes sense on
> its own.
>
> [1] https://lore.kernel.org/all/20260930-b4-dalmore-fixes-mipical-clk-v1-1-0518be6c7979@nvidia.com/
>
> Tool use (see Documentation/process/generated-content.rst): this patch,
> its changelog and this note were prepared with an LLM coding assistant
> (Claude Code). It traced the clock enable counts from my clk_summary
> dumps and wrote the code change and the texts from my measurements and
> instructions. I reviewed the change and ran the test on the device.
> ---
>  drivers/gpu/host1x/tegra114-mipi.c | 2 ++
>  1 file changed, 2 insertions(+)
>
> diff --git a/drivers/gpu/host1x/tegra114-mipi.c b/drivers/gpu/host1x/tegra114-mipi.c
> index c084a09784d1..83a43a5e33af 100644
> --- a/drivers/gpu/host1x/tegra114-mipi.c
> +++ b/drivers/gpu/host1x/tegra114-mipi.c
> @@ -197,6 +197,8 @@ static int tegra114_mipi_power_down(struct tegra_mipi *mipi)
>         value |= MIPI_CAL_BIAS_PAD_PDVCLAMP;
>         tegra_mipi_writel(mipi, value, MIPI_CAL_BIAS_PAD_CFG0);
>
> +       clk_disable(mipi->clk);
> +
>         return 0;
>  }
>
>
> ---
> base-commit: 734bef548a96e8774d6eef5dfa2026c6edc4e80b
> change-id: 20261025-upstream-host1x-mipi-clk-867edad177b0
>
> Best regards,
> --
> Patrick Fischer <admin@tsv-stahl-riesa.de>
>

Tested-by: Svyatoslav Ryhel <clamor95@gmail.com> # Tegratab (P1988)
and ASUS TF701T
Reviewed-by: Svyatoslav Ryhel <clamor95@gmail.com>

Re: [PATCH] gpu: host1x: mipi: Disable clock again after powering down the pads

[Mikko Perttunen]

On Monday, October 26, 2026 2:13 AM Patrick Fischer via B4 Relay wrote:
> From: Patrick Fischer <admin@tsv-stahl-riesa.de>
> 
> tegra114_mipi_power_down() enables the MIPI calibration clock to access
> the bias pad registers but never disables it. Every disable/enable cycle
> of a DSI or CSI user therefore leaks one enable count, and the clock
> stays on for good after the first power down.
> 
> Add the missing clk_disable(), matching tegra114_mipi_power_up().
> 
> The leak gets more costly with "clk: tegra: Fix Tegra114 MIPI
> calibration clock parent", which makes PLL_P_OUT3 the parent of
> mipi-cal: without this fix PLL_P_OUT3 would then stay on as well.
> 
> On a Tegra Note 7 (P1640) the enable count of mipi-cal in clk_summary
> grew by one with each DPMS off/on cycle of the DSI panel. With this
> patch it returns to 0 after each cycle.
> 
> Fixes: 15372d4be7f0 ("gpu: host1x: mipi: Power down regulators when unused")
> Signed-off-by: Patrick Fischer <admin@tsv-stahl-riesa.de>
> ---
> Mikko's "clk: tegra: Fix Tegra114 MIPI calibration clock parent" [1]
> fixes the MIPI calibration timeouts on Tegra114. While testing the same
> change on a Tegra Note 7 (P1640) I noticed that
> tegra114_mipi_power_down() leaks the clock enable it takes. With [1]
> applied that leak keeps PLL_P_OUT3 on after the first DPMS off, so the
> two belong together, although this patch applies and makes sense on
> its own.
> 
> [1] https://lore.kernel.org/all/20260930-b4-dalmore-fixes-mipical-clk-v1-1-0518be6c7979@nvidia.com/
> 
> Tool use (see Documentation/process/generated-content.rst): this patch,
> its changelog and this note were prepared with an LLM coding assistant
> (Claude Code). It traced the clock enable counts from my clk_summary
> dumps and wrote the code change and the texts from my measurements and
> instructions. I reviewed the change and ran the test on the device.
> ---
>  drivers/gpu/host1x/tegra114-mipi.c | 2 ++
>  1 file changed, 2 insertions(+)
> 
> diff --git a/drivers/gpu/host1x/tegra114-mipi.c b/drivers/gpu/host1x/tegra114-mipi.c
> index c084a09784d1..83a43a5e33af 100644
> --- a/drivers/gpu/host1x/tegra114-mipi.c
> +++ b/drivers/gpu/host1x/tegra114-mipi.c
> @@ -197,6 +197,8 @@ static int tegra114_mipi_power_down(struct tegra_mipi *mipi)
>  	value |= MIPI_CAL_BIAS_PAD_PDVCLAMP;
>  	tegra_mipi_writel(mipi, value, MIPI_CAL_BIAS_PAD_CFG0);
>  
> +	clk_disable(mipi->clk);
> +
>  	return 0;
>  }
>  
> 
> ---
> base-commit: 734bef548a96e8774d6eef5dfa2026c6edc4e80b
> change-id: 20261025-upstream-host1x-mipi-clk-867edad177b0
> 
> Best regards,
> --  
> Patrick Fischer <admin@tsv-stahl-riesa.de>

Thanks!

Reviewed-by: Mikko Perttunen <mperttunen@nvidia.com>