Re: [PATCH v10 08/11] dt-bindings: ufs: Add NXP S32N79 UFS host controller

[Larisa Ileana Grigore <larisa.grigore@oss.nxp.com>]

On 11/5/2026 8:28 PM, Krzysztof Kozlowski wrote:
> On 04/11/2026 10:41, Larisa Ileana Grigore wrote:
>> On 11/4/2026 10:40 AM, Krzysztof Kozlowski wrote:
>> v8:
>> https://lore.kernel.org/all/20261013103003.373156-1-larisa.grigore@oss.nxp.com/
>> v9:
>> https://lore.kernel.org/all/20261024122533.3609180-1-larisa.grigore@oss.nxp.com/
>> v10:
>> https://lore.kernel.org/all/20261103133215.1385823-1-larisa.grigore@oss.nxp.com
>>
>> Regarding your comments on v9:
>>
>> Frank's Reviewed-by was given publicly on v8 [1]. The series only looked
>> like a v1 because of the wrong version number.
>> The tag ordering was changed in v10 since the patch was changed.
>> The single 0 Hz OPP entry: as discussed on v8 [2][3], the clock rate is
>> set outside Linux and is not scaled. The OPP table lets the UFS core
> 
> That is not the purpose of OPP table. OPP defines performance point.
> Performance point of 0 makes no sense. You cannot use Linux limitations
> as reason to add some DTS, because answer is simple: fix your Linux
> limitations.
>

Hi Krzysztof,

Thanks for the clarification. I understand that an OPP table is not 
appropriate here.

Existing platform DTs, such as Hi3660 and MT8195, define freq-table-hz 
containing only <0 0> pairs. This allows the UFS core to manage clock 
enable/disable without setting their rates. With freq-table-hz 
deprecated, there seems to be a gap for this use case, beyond S32N.

Could you please advise on the preferred way to address this?

Regards,
Larisa

>> enable and gate the clock. As you suggested, v10 explains this in the
>> commit message. Let me know if you would like more details there.
> 
> 
> 
> Best regards,
> Krzysztof