Re: [PATCH v4 6/6] x86/resctrl: Add support for L3 occupancy monitoring via RMID MMIO read

["Chen, Yu C" <yu.c.chen@intel.com>]

Hi Reinette,

On 6/19/2026 7:40 AM, Reinette Chatre wrote:
> Hi Chenyu,
> 
> On 6/13/26 12:57 AM, Chen Yu wrote:
>> The CMRC (Cache Monitoring Registers for CPU Agents Description)
>> ACPI sub-table provides the MMIO address used to read the LLC
>> occupancy counter for each RMID. When ERDT is enabled on the
>> platform, use this MMIO interface instead of the legacy MSR read
>> to obtain the L3 occupancy value.
>>
>> Introduce erdt_mon_read(), a helper that retrieves monitoring
>> data for a given RMID and event ID from an ERDT domain. Initial
>> support is added for the L3 occupancy monitoring event
>> (QOS_L3_OCCUP_EVENT_ID).
>>
>> If the platform supports ERDT, CMRC-based MMIO access is used by
>> default. If ERDT is unavailable, the implementation is to use
>> MSR-based operations.
> 
> (nit: please write in imperative tone and use entire line length available)
> 
> ...
> 

OK, will do in next version.

>> diff --git a/arch/x86/include/asm/resctrl.h b/arch/x86/include/asm/resctrl.h
>> index 97c2f6bc7a5f..9b3b03279dd8 100644
>> --- a/arch/x86/include/asm/resctrl.h
>> +++ b/arch/x86/include/asm/resctrl.h
>> @@ -41,6 +41,8 @@ struct resctrl_pqr_state {
>>   };
>>   
>>   bool erdt_enabled(void);
>> +struct rdt_domain_hdr;
>> +int erdt_mon_read(struct rdt_domain_hdr *hdr, int ev_id, int rmid, u64 *val);
>>   
>>   DECLARE_PER_CPU(struct resctrl_pqr_state, pqr_state);
>>   
>> diff --git a/arch/x86/kernel/cpu/resctrl/core.c b/arch/x86/kernel/cpu/resctrl/core.c
>> index 90730f0851fa..fe812f7190fc 100644
>> --- a/arch/x86/kernel/cpu/resctrl/core.c
>> +++ b/arch/x86/kernel/cpu/resctrl/core.c
>> @@ -965,7 +965,7 @@ static __init bool get_rdt_mon_resources(void)
>>   	bool ret = false;
>>   
>>   	if (rdt_cpu_has(X86_FEATURE_CQM_OCCUP_LLC)) {
>> -		resctrl_enable_mon_event(QOS_L3_OCCUP_EVENT_ID, false, 0, NULL);
>> +		resctrl_enable_mon_event(QOS_L3_OCCUP_EVENT_ID, erdt_enabled(), 0, NULL);
>>   		ret = true;
>>   	}
>>   	if (rdt_cpu_has(X86_FEATURE_CQM_MBM_TOTAL)) {
> 
> As mentioned in patch #1, when erdt_enabled() is true the enumeration still proceeds to
> enumerate the monitoring properties via CPUID to discover the number of RMIDs that the
> *MSR* supports and use it as the maximum RMID (and thus the maximum number of registers)
> that MMIO supports?
> 

OK, will switch to the maximum RMID exposed by ACPI table, if 
erdt_enabled() is true.

>> diff --git a/arch/x86/kernel/cpu/resctrl/monitor.c b/arch/x86/kernel/cpu/resctrl/monitor.c
>> index 9209927f88a2..1491f96b57c3 100644
>> --- a/arch/x86/kernel/cpu/resctrl/monitor.c
>> +++ b/arch/x86/kernel/cpu/resctrl/monitor.c
>> @@ -278,6 +278,13 @@ int resctrl_arch_rmid_read(struct rdt_resource *r, struct rdt_domain_hdr *hdr,
>>   
>>   	switch (r->rid) {
>>   	case RDT_RESOURCE_L3:
>> +		/*
>> +		 * No SNC for mmio based L3 occupancy, so there is no need
> 
> "No SNC for mmio based L3 occupancy" is too significant to be buried like this. Could you
> please elaborate on this claim and enforce it with the implementation? For example,
> could rdt_get_l3_mon_config() WARN and *not* set r->mon_capable if erdt_enable() and
> snc_nodes_per_l3_cache > 1?
> 

IIUC, SNC happens to be unsupported on platforms that currently support 
MMIO-based
access. I’m not sure if there will be a platform that enables both MMIO 
access and
SNC. I’ll add a WARN here as suggested (and handle the case if such 
platform is
introduced later).

thanks,
Chenyu

>> +		 * to convert logical RMID to a physical RMID via
>> +		 * logical_rmid_to_physical_rmid().
>> +		 */
>> +		if (erdt_enabled() && eventid == QOS_L3_OCCUP_EVENT_ID)
>> +			return erdt_mon_read(hdr, eventid, rmid, val);
>>   		return arch_l3_read_event(hdr, rmid, eventid, val, r);
>>   	case RDT_RESOURCE_PERF_PKG:
>>   		return intel_aet_read_event(hdr->id, rmid, arch_priv, val);
> 
> Reinette