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From: "Chen, Yu C" <yu.c.chen@intel.com>
To: Reinette Chatre <reinette.chatre@intel.com>,
	Chen Yu <yu.c.chen@intel.com>
Cc: <x86@kernel.org>, <linux-kernel@vger.kernel.org>,
	<tglx@kernel.org>, <bp@alien8.de>, <mingo@redhat.com>,
	<dave.hansen@linux.intel.com>, <hpa@zytor.com>,
	<dave.martin@arm.com>, <james.morse@arm.com>,
	<fenghuay@nvidia.com>, <babu.moger@amd.com>,
	<anil.keshavamurthy@broadcom.com>, <tony.luck@intel.com>,
	<chen.yu@linux.dev>
Subject: Re: [PATCH v4 1/6] x86/resctrl: Parse ACPI ERDT table and map RMDD domains by L3 cache ID
Date: Wed, 24 Jun 2026 14:04:00 +0800	[thread overview]
Message-ID: <1c671ba2-501d-4b31-bd33-9cb23b54db01@intel.com> (raw)
In-Reply-To: <4b48ec4d-517d-44d0-8be0-7e24d0970b7b@intel.com>

On 6/24/2026 12:05 PM, Chen, Yu C wrote:
> On 6/24/2026 12:46 AM, Reinette Chatre wrote:
>> Hi Chenyu,
>>
>> On 6/23/26 4:43 AM, Chen, Yu C wrote:
>>> On 6/23/2026 2:29 PM, Chen, Yu C wrote:
>>>>>>>    From what I can tell it is tmp that is essentially returned by 
>>>>>>> this function and it
>>>>>>> is the result of get_cpu_cacheinfo_id() that returns the cache ID 
>>>>>>> initialized from
>>>>>>> CPUID leaf 0x4 ... the function name 
>>>>>>> ("get_l3_cache_id_from_cacd()") and function comment
>>>>>>> "Resolve L3 cache ID from CACD subtable" implies differently and 
>>>>>>> the way this is done
>>>>>>> makes me wonder why CACD needs to be parsed at all.
>>>>>>>
>>>>>>> resctrl already has a hotplug handler and it dynamically 
>>>>>>> determines the domain ID
>>>>>>> based on the cache ID returned from get_cpu_cacheinfo_id(). If 
>>>>>>> the domain ID used by the
>>>>>>> new ERDT tables can be, as it appears is done here, trusted to 
>>>>>>> what Linux already
>>>>>>> treating as domain ID then why is it needed to parse CACD at all? 
>>>>>>> Why not just
>>>>>>> pick the domain ID from RMDD directly and use it directly as 
>>>>>>> domain ID?
>>>>>>>
>>>>>>> Later the domain ID from RMDD is just used in error messages ... 
>>>>>>> never actually used
>>>>>>> as a domain ID to guide the implementation so the correlation 
>>>>>>> appears to be implicit with
>>>>>>> this CACD parsing not intuitive.
>>>>>>>
>>>>>>
>>>>>> You are right that the cache ID ultimately comes from 
>>>>>> get_cpu_cacheinfo_id(),
>>>>>> not from CACD directly - the function name is misleading and 
>>>>>> should be improved.
>>>>>>
>>>>>> However, my understanding is that CACD parsing acts as the bridge 
>>>>>> between ACPI's
>>>>>> RMDD domain namespace and the kernel's L3 domain ID: CACD 
>>>>>> enumerates which CPUs
>>>>>> belong to each RMDD, and from those CPUs we derive the kernel-side 
>>>>>> L3 cache ID.
>>>>>> The specification defines an RMDD DomainID as an identifier unique 
>>>>>> within the
>>>>>> ERDT table, yet it does not guarantee that this ID matches the 
>>>>>> kernel’s cache ID
>>>>>> obtained via CPUID leaf 0x4. For this reason, we omitted the RMDD 
>>>>>> domain ID in
>>>>>> the current release.
>>>>>
>>>>> get_l3_cache_id_from_cacd() implies a straightforward query and the 
>>>>> function
>>>>> comments supports this. At the same time the function includes what 
>>>>> appears to be
>>>>> sanity checks but from what you say turns out to be essential 
>>>>> enforcement of the
>>>>> RMDD to CPUID leaf 0x4 mapping. Is this correct? As sanity checks 
>>>>> these additional
>>>>> checks are ok but as RMDD to CPUID leaf 0x4 mapping enforcement I 
>>>>> find them inadequate
>>>>> because its correctness requires all CPUs of all domains to be 
>>>>> online which cannot be
>>>>> guaranteed when this initialization runs.
>>>>>
>>>>> Consider for example a scenario where RMDD and CPUID do not agree 
>>>>> on which CPUs form
>>>>> part of a domain. If only one CPU of this RMDD domain is online at 
>>>>> the time this
>>>>> initialization is done then the mismatch will never be noticed and 
>>>>> resctrl will just
>>>>> silently use the CPUID mapping, no?
>>>>>
>>>>
>>>> I suppose you are referring to the following scenario:
>>>> CACD says CPUs {0,1,2,3} belong to RMDD-A, and CPUID says
>>>> CPUs {0,1} share L3-X while CPUs {2,3} share L3-Y (a mismatch).
>>>> If only CPU 0 is brought online:
>>>>
>>>> get_l3_cache_id_from_cacd() iterates CACD's X2APIC list: {0,1,2,3}
>>>> CPU 1, 2, 3 are offline -> skipped
>>>> CPU 0 is online -> cache_id = get_cpu_cacheinfo_id(0) = L3-X,
>>>> all passed.
>>>>
>>>> Then later CPU2 is online, resctrl's hotplug creates domain L3-Y.
>>>> But the xarray has no entry for L3-Y, so erdt_mon_read() will return
>>>> -EIO for that domain.
>>
>> An error would at least give indication of a problem but I also see a 
>> possible
>> scenario where the data will happily be read from the wrong register. 
>> Consider the
>> following change to the scenario you present:
>> CACD: RMDD-A = {0, 2}; RMDD-B = {1, 3}
>> CPUID: L3-X = {0, 1}; L3-Y = {2, 3}
>>
>> If ACPI enumeration is done with CPUs 1, 2, and 3 offline then they 
>> are skipped.
>> CPU 0 is online -> cache_id = get_cpu_cacheinfo_id(0) = L3-X
>>
>> Later when CPU 1 comes online resctrl will consider it to be in L3-X and
>> also find an xarray entry for L3-X which will result in 
>> erdt_mon_read() to
>> read the RMID data from RMDD-A instead of RMDD-B?
>>
> 
> Yes, this approach is feasible. However, I am uncertain whether RDT should
> be enabled. The underlying issue is that the firmware(BIOS) and 
> silicon(CPUID)
> will be out of sync, leaving RDT in an unstable state.
> 

That said, there remains an open question as to whether we ought to enable
RDT on platforms where the domain information returned by firmware (BIOS)
is inconsistent with the CPUID values exposed by the silicon.

thanks,
Chenyu


  reply	other threads:[~2026-06-24  6:04 UTC|newest]

Thread overview: 34+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-06-13  7:56 [PATCH v4 0/6] Introduce MMIO-based CMT access for Enhanced RDT Chen Yu
2026-06-13  7:56 ` [PATCH v4 1/6] x86/resctrl: Parse ACPI ERDT table and map RMDD domains by L3 cache ID Chen Yu
2026-06-18 23:37   ` Reinette Chatre
2026-06-22  9:07     ` Chen, Yu C
2026-06-22 21:28       ` Reinette Chatre
2026-06-23  6:29         ` Chen, Yu C
2026-06-23 11:43           ` Chen, Yu C
2026-06-23 16:46             ` Reinette Chatre
2026-06-24  4:05               ` Chen, Yu C
2026-06-24  6:04                 ` Chen, Yu C [this message]
2026-06-24 23:44                   ` Reinette Chatre
2026-06-24 23:58                     ` Luck, Tony
2026-06-25  0:24                       ` Reinette Chatre
2026-06-25 14:59                         ` Chen, Yu C
2026-06-25 14:33                     ` Chen, Yu C
2026-06-25 15:54                       ` Reinette Chatre
2026-06-13  7:57 ` [PATCH v4 2/6] x86/resctrl: Parse ACPI CMRC table Chen Yu
2026-06-13  7:57 ` [PATCH v4 3/6] x86/resctrl: Rename prev_msr to prev_mon_val Chen Yu
2026-06-18 23:39   ` Reinette Chatre
2026-06-22 12:42     ` Chen, Yu C
2026-06-22 21:29       ` Reinette Chatre
2026-06-23  7:48         ` Chen, Yu C
2026-06-23 16:47           ` Reinette Chatre
2026-06-24  6:16             ` Chen, Yu C
2026-06-13  7:57 ` [PATCH v4 4/6] x86/resctrl: Refactor the monitor read function Chen Yu
2026-06-13  7:57 ` [PATCH v4 5/6] fs/resctrl: Do not invoke smp_processor_id() in preemptible context Chen Yu
2026-06-13  7:57 ` [PATCH v4 6/6] x86/resctrl: Add support for L3 occupancy monitoring via RMID MMIO read Chen Yu
2026-06-18 23:40   ` Reinette Chatre
2026-06-22 14:09     ` Chen, Yu C
2026-06-22 21:30       ` Reinette Chatre
2026-06-23  5:00         ` Chen, Yu C
2026-06-23 16:48           ` Reinette Chatre
2026-06-24  9:00             ` Chen, Yu C
2026-06-24 23:44               ` Reinette Chatre

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