From: Stafford Horne <shorne@gmail.com>
To: Jonas Bonn <jonas@southpole.se>,
Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
Cc: linux@roeck-us.net, openrisc@lists.librecores.org,
linux-kernel@vger.kernel.org,
Peter Zijlstra <peterz@infradead.org>,
Stafford Horne <shorne@gmail.com>
Subject: [PATCH v4 07/24] openrisc: add atomic bitops
Date: Fri, 24 Feb 2017 13:32:27 +0900 [thread overview]
Message-ID: <06bdc8a2358b4c556933e314ec7f2279c14ea9bd.1487910170.git.shorne@gmail.com> (raw)
In-Reply-To: <cover.1487910170.git.shorne@gmail.com>
In-Reply-To: <cover.1487910170.git.shorne@gmail.com>
From: Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
This utilize the load-link/store-conditional l.lwa and l.swa
instructions to implement the atomic bitops.
When those instructions are not available emulation is provided.
Cc: Peter Zijlstra <peterz@infradead.org>
Signed-off-by: Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
[shorne@gmail.com: remove OPENRISC_HAVE_INST_LWA_SWA config suggesed by
Alan Cox https://lkml.org/lkml/2014/7/23/666, implement
test_and_change_bit]
Signed-off-by: Stafford Horne <shorne@gmail.com>
---
arch/openrisc/include/asm/bitops.h | 2 +-
arch/openrisc/include/asm/bitops/atomic.h | 123 ++++++++++++++++++++++++++++++
2 files changed, 124 insertions(+), 1 deletion(-)
create mode 100644 arch/openrisc/include/asm/bitops/atomic.h
diff --git a/arch/openrisc/include/asm/bitops.h b/arch/openrisc/include/asm/bitops.h
index 3003cda..689f568 100644
--- a/arch/openrisc/include/asm/bitops.h
+++ b/arch/openrisc/include/asm/bitops.h
@@ -45,7 +45,7 @@
#include <asm-generic/bitops/hweight.h>
#include <asm-generic/bitops/lock.h>
-#include <asm-generic/bitops/atomic.h>
+#include <asm/bitops/atomic.h>
#include <asm-generic/bitops/non-atomic.h>
#include <asm-generic/bitops/le.h>
#include <asm-generic/bitops/ext2-atomic.h>
diff --git a/arch/openrisc/include/asm/bitops/atomic.h b/arch/openrisc/include/asm/bitops/atomic.h
new file mode 100644
index 0000000..35fb85f
--- /dev/null
+++ b/arch/openrisc/include/asm/bitops/atomic.h
@@ -0,0 +1,123 @@
+/*
+ * Copyright (C) 2014 Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2. This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+
+#ifndef __ASM_OPENRISC_BITOPS_ATOMIC_H
+#define __ASM_OPENRISC_BITOPS_ATOMIC_H
+
+static inline void set_bit(int nr, volatile unsigned long *addr)
+{
+ unsigned long mask = BIT_MASK(nr);
+ unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr);
+ unsigned long tmp;
+
+ __asm__ __volatile__(
+ "1: l.lwa %0,0(%1) \n"
+ " l.or %0,%0,%2 \n"
+ " l.swa 0(%1),%0 \n"
+ " l.bnf 1b \n"
+ " l.nop \n"
+ : "=&r"(tmp)
+ : "r"(p), "r"(mask)
+ : "cc", "memory");
+}
+
+static inline void clear_bit(int nr, volatile unsigned long *addr)
+{
+ unsigned long mask = BIT_MASK(nr);
+ unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr);
+ unsigned long tmp;
+
+ __asm__ __volatile__(
+ "1: l.lwa %0,0(%1) \n"
+ " l.and %0,%0,%2 \n"
+ " l.swa 0(%1),%0 \n"
+ " l.bnf 1b \n"
+ " l.nop \n"
+ : "=&r"(tmp)
+ : "r"(p), "r"(~mask)
+ : "cc", "memory");
+}
+
+static inline void change_bit(int nr, volatile unsigned long *addr)
+{
+ unsigned long mask = BIT_MASK(nr);
+ unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr);
+ unsigned long tmp;
+
+ __asm__ __volatile__(
+ "1: l.lwa %0,0(%1) \n"
+ " l.xor %0,%0,%2 \n"
+ " l.swa 0(%1),%0 \n"
+ " l.bnf 1b \n"
+ " l.nop \n"
+ : "=&r"(tmp)
+ : "r"(p), "r"(mask)
+ : "cc", "memory");
+}
+
+static inline int test_and_set_bit(int nr, volatile unsigned long *addr)
+{
+ unsigned long mask = BIT_MASK(nr);
+ unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr);
+ unsigned long old;
+ unsigned long tmp;
+
+ __asm__ __volatile__(
+ "1: l.lwa %0,0(%2) \n"
+ " l.or %1,%0,%3 \n"
+ " l.swa 0(%2),%1 \n"
+ " l.bnf 1b \n"
+ " l.nop \n"
+ : "=&r"(old), "=&r"(tmp)
+ : "r"(p), "r"(mask)
+ : "cc", "memory");
+
+ return (old & mask) != 0;
+}
+
+static inline int test_and_clear_bit(int nr, volatile unsigned long *addr)
+{
+ unsigned long mask = BIT_MASK(nr);
+ unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr);
+ unsigned long old;
+ unsigned long tmp;
+
+ __asm__ __volatile__(
+ "1: l.lwa %0,0(%2) \n"
+ " l.and %1,%0,%3 \n"
+ " l.swa 0(%2),%1 \n"
+ " l.bnf 1b \n"
+ " l.nop \n"
+ : "=&r"(old), "=&r"(tmp)
+ : "r"(p), "r"(~mask)
+ : "cc", "memory");
+
+ return (old & mask) != 0;
+}
+
+static inline int test_and_change_bit(int nr, volatile unsigned long *addr)
+{
+ unsigned long mask = BIT_MASK(nr);
+ unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr);
+ unsigned long old;
+ unsigned long tmp;
+
+ __asm__ __volatile__(
+ "1: l.lwa %0,0(%2) \n"
+ " l.xor %1,%0,%3 \n"
+ " l.swa 0(%2),%1 \n"
+ " l.bnf 1b \n"
+ " l.nop \n"
+ : "=&r"(old), "=&r"(tmp)
+ : "r"(p), "r"(mask)
+ : "cc", "memory");
+
+ return (old & mask) != 0;
+}
+
+#endif /* __ASM_OPENRISC_BITOPS_ATOMIC_H */
--
2.9.3
next prev parent reply other threads:[~2017-02-24 4:37 UTC|newest]
Thread overview: 46+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-02-24 4:32 [PATCH v4 00/24] OpenRISC patches for 4.11 Stafford Horne
2017-02-24 4:32 ` [PATCH v4 01/24] openrisc: use SPARSE_IRQ Stafford Horne
2017-02-24 4:32 ` [PATCH v4 02/24] openrisc: add cache way information to cpuinfo Stafford Horne
2017-02-24 4:32 ` [PATCH v4 03/24] openrisc: tlb miss handler optimizations Stafford Horne
2017-02-24 4:32 ` [PATCH v4 04/24] openrisc: head: use THREAD_SIZE instead of magic constant Stafford Horne
2017-02-24 4:32 ` [PATCH v4 05/24] openrisc: head: refactor out tlb flush into it's own function Stafford Horne
2017-02-24 9:57 ` Jonas Bonn
2017-02-24 10:54 ` Stefan Kristiansson
2017-02-24 12:48 ` Jonas Bonn
2017-02-24 13:54 ` Stefan Kristiansson
2017-02-24 19:20 ` Stafford Horne
2017-02-24 4:32 ` [PATCH v4 06/24] openrisc: add l.lwa/l.swa emulation Stafford Horne
2017-02-24 9:27 ` Jonas Bonn
2017-02-24 19:53 ` Stafford Horne
2017-02-24 4:32 ` Stafford Horne [this message]
2017-02-24 10:56 ` [PATCH v4 07/24] openrisc: add atomic bitops Peter Zijlstra
2017-02-24 19:16 ` Stafford Horne
2017-02-24 4:32 ` [PATCH v4 08/24] openrisc: add cmpxchg and xchg implementations Stafford Horne
2017-02-24 4:32 ` [PATCH v4 09/24] openrisc: add optimized atomic operations Stafford Horne
2017-02-24 4:32 ` [PATCH v4 10/24] openrisc: add futex_atomic_* implementations Stafford Horne
2017-02-24 4:32 ` [PATCH v4 11/24] openrisc: remove unnecessary stddef.h include Stafford Horne
2017-02-24 4:32 ` [PATCH v4 12/24] openrisc: Fix the bitmask for the unit present register Stafford Horne
2017-02-24 4:32 ` [PATCH v4 13/24] openrisc: Initial support for the idle state Stafford Horne
2017-02-24 4:32 ` [PATCH v4 14/24] openrisc: Add optimized memset Stafford Horne
2017-02-24 4:32 ` [PATCH v4 15/24] openrisc: Add optimized memcpy routine Stafford Horne
2017-02-24 4:32 ` [PATCH v4 16/24] openrisc: Add .gitignore Stafford Horne
2017-02-24 4:32 ` [PATCH v4 17/24] MAINTAINERS: Add the openrisc official repository Stafford Horne
2017-02-24 4:32 ` [PATCH v4 18/24] scripts/checkstack.pl: Add openrisc support Stafford Horne
2017-02-24 14:42 ` Tobias Klauser
2017-02-24 19:33 ` Stafford Horne
2017-02-24 4:32 ` [PATCH v4 19/24] openrisc: entry: Whitespace and comment cleanups Stafford Horne
2017-02-24 9:45 ` Jonas Bonn
2017-02-24 20:31 ` Stafford Horne
2017-02-24 4:32 ` [PATCH v4 20/24] openrisc: entry: Fix delay slot detection Stafford Horne
2017-02-24 9:32 ` Jonas Bonn
2017-02-24 20:13 ` Stafford Horne
2017-02-24 4:32 ` [PATCH v4 21/24] openrisc: head: Move init strings to rodata section Stafford Horne
2017-02-24 9:28 ` Jonas Bonn
2017-02-24 20:09 ` Stafford Horne
2017-02-24 4:32 ` [PATCH v4 22/24] arch/openrisc/lib/memcpy.c: use correct OR1200 option Stafford Horne
2017-02-24 9:24 ` Jonas Bonn
2017-02-24 19:44 ` Stafford Horne
2017-02-24 4:32 ` [PATCH v4 23/24] openrisc: Export ioremap symbols used by modules Stafford Horne
2017-02-24 4:32 ` [PATCH v4 24/24] openrisc: head: Init r0 to 0 on start Stafford Horne
2017-02-24 9:21 ` Jonas Bonn
2017-02-24 19:35 ` Stafford Horne
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