readl/writel and memory barriers

["Dan Maas" <dmaas@dcine.com>]

Are the PCI memory access functions like readl() and writel() supposed to
enforce ordering without explicit memory barriers?

I've heard inconsistent reports - Benjamin Herrenschmidt pointed out that on
PPC, the definitions of readl() and writel() include memory barriers. But
the code example on page 229 of Rubini and Corbet's "Linux Device Drivers"
2nd ed. suggests that an explicit wmb() is needed to preserve ordering of
writel()s.

In a quick survey of architectures that need explicit memory barriers to
enforce ordering of PCI accesses, it seems that alpha and PPC include memory
barriers inside readl() and writel(), whereas MIPS, sparc64, ia64, and s390
do not include them. (I'm not intimately familiar with these architectures
so forgive me if I got some wrong...). What is the official story here?

Regards,
Dan