From: "Dan Maas" <dmaas@dcine.com>
To: "Jesse Barnes" <jbarnes@sgi.com>, "David Mosberger" <davidm@hpl.hp.com>
Cc: <linux-kernel@vger.kernel.org>,
"Benjamin Herrenschmidt" <benh@kernel.crashing.org>,
"Ben Collins" <bcollins@debian.org>
Subject: Re: readl/writel and memory barriers
Date: Tue, 19 Feb 2002 15:11:45 -0500 [thread overview]
Message-ID: <0a5301c1b981$a921f820$1a01a8c0@allyourbase> (raw)
In-Reply-To: <092401c1b8e7$1d190660$1a01a8c0@allyourbase> <15474.34580.625864.963930@napali.hpl.hp.com> <20020219103506.A1511175@sgi.com>
Jesse Barnes wrote:
> To avoid the overhead of having I/O flushed on every
> memory barrier and readX/writeX operation, we've introduced
> mmiob() on ia64, which explicity orders I/O space accesses.
> Some ports have chosen to take the performance hit in every
> readX/writeX, memory barrier, and spinlock however
> (e.g. PPC64, MIPS).
I have a hunch that many drivers will break if you change the semantics of
readX/writeX from in-order to out-of-order - lots of drivers are only
developed & tested on x86, which completely hides the issue...
If you consider the performance cost of in-order readX/writeX to be
significant, then I would suggest adding another group of readX/writeX APIs
that explicitly allow out-of-order PCI access. (__raw_readX/__raw_writeX
seem to offer this already on some platforms...)
Regards,
Dan
next prev parent reply other threads:[~2002-02-19 20:11 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2002-02-19 1:45 Dan Maas
2002-02-19 9:31 ` Alan Cox
2002-02-19 17:10 ` David Mosberger
2002-02-19 18:35 ` Jesse Barnes
2002-02-19 20:11 ` Dan Maas [this message]
2002-02-19 20:23 ` Jesse Barnes
2002-02-19 22:05 ` Keith Owens
2002-02-19 22:17 ` Jesse Barnes
2002-02-21 0:29 ` Randy.Dunlap
2002-02-23 4:48 ` Daniel Phillips
2002-02-25 16:19 ` Randy.Dunlap
2002-02-19 19:33 ` David Mosberger
2002-02-19 19:42 ` Jesse Barnes
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