Re: readl/writel and memory barriers

[David Mosberger <davidm@hpl.hp.com>]

>>>>> On Mon, 18 Feb 2002 20:45:29 -0500, "Dan Maas" <dmaas@dcine.com> said:

  Dan> In a quick survey of architectures that need explicit memory
  Dan> barriers to enforce ordering of PCI accesses, it seems that
  Dan> alpha and PPC include memory barriers inside readl() and
  Dan> writel(), whereas MIPS, sparc64, ia64, and s390 do not include
  Dan> them. (I'm not intimately familiar with these architectures so
  Dan> forgive me if I got some wrong...). What is the official story
  Dan> here?

On ia64, the fact that readl()/writel() are accessing uncached space
ensures the CPU doesn't reorder the accesses.  Furthermore, the
accesses are performed through "volatile" pointers, which ensures that
the compiler doesn't reorder them (and, as a side-effect, such
pointers also generate ordered loads/stores, but this isn't strictly
needed, due to accessing uncached space).

	--david