Re: [PATCH v2 3/8] clk: qcom: common: Manage rpm, configure PLLs & AON clks in really probe

[Jagadeesh Kona <quic_jkona@quicinc.com>]

On 3/6/2025 6:15 PM, Konrad Dybcio wrote:
> On 6.03.2025 9:55 AM, Jagadeesh Kona wrote:
>> Add support for runtime power management, PLL configuration and enabling
>> critical clocks in qcom_cc_really_probe() to commonize the clock
>> controller probe.
>>
>> The runtime power management is not required for all clock controllers,
>> hence handle the rpm based on use_rpm flag in clock controller descriptor.
>> Also the power domains need to be kept enabled during pll configuration,
>> hence attach all required power domains prior to calling get_sync() on the
>> device.
>>
>> Signed-off-by: Jagadeesh Kona <quic_jkona@quicinc.com>
>> ---
> 
> [...]
> 
>> + * struct qcom_clk_cfg - To maintain list of clocks that needs to be
>> + *                       kept ON or misc clock register settings
> 
> I have some reservations about this name, particularly since 'clk_cfg'
> has already been used in the msmbus/interconnect space..
> 
> Perhaps qcom_clk_reg_settings?
> 

Sure, will update.

>> + * @offset: address offset for clock register
>> + * @mask: bit mask to indicate the bits to update
>> + */
>> +struct qcom_clk_cfg {
>> +	unsigned int offset;
>> +	unsigned int mask;
> 
> "u32"
> 
> also, to expand it, we probably want "field" and "val" to replace the
> calls to regmap_update_bits in some drivers
> 
> I think we may keep this /\ struct for things like:
> 
> /* Enable clock gating for MDP clocks */
> regmap_update_bits(regmap, DISP_CC_MISC_CMD, 0x10, 0x10);
> 
> while keeping a separate u32 array of branch clocks to call
> qcom_branch_set_clk_en() on - we would then use 3x less memory
> 
> 

Sure, will take care of these in next series.

>> +};
> 
>> +
>>  struct qcom_cc_desc {
>>  	const struct regmap_config *config;
>>  	struct clk_regmap **clks;
>> @@ -39,6 +50,11 @@ struct qcom_cc_desc {
>>  	const struct qcom_icc_hws_data *icc_hws;
>>  	size_t num_icc_hws;
>>  	unsigned int icc_first_node_id;
>> +	struct qcom_clk_cfg *clks_cfg;
>> +	size_t num_clks_cfg;
>> +	struct clk_alpha_pll **plls;
> 
> Some ancient or "non-standard" SoCs have non-alpha PLLs, please rename
> this to something like alpha_plls
> 

Sure, will update it.

Thanks,
Jagadeesh

> 
> Konrad