From: David Daney <ddaney.cavm@gmail.com>
To: linux-mips@linux-mips.org, ralf@linux-mips.org,
kvm@vger.kernel.org, Sanjay Lal <sanjayl@kymasys.com>
Cc: linux-kernel@vger.kernel.org, David Daney <david.daney@cavium.com>
Subject: [PATCH 13/31] mips/kvm: Add accessors for MIPS VZ registers.
Date: Fri, 7 Jun 2013 16:03:17 -0700 [thread overview]
Message-ID: <1370646215-6543-14-git-send-email-ddaney.cavm@gmail.com> (raw)
In-Reply-To: <1370646215-6543-1-git-send-email-ddaney.cavm@gmail.com>
From: David Daney <david.daney@cavium.com>
There are accessors for both the guest control registers as well as
guest CP0 context.
Signed-off-by: David Daney <david.daney@cavium.com>
---
arch/mips/include/asm/mipsregs.h | 260 +++++++++++++++++++++++++++++++++++++++
1 file changed, 260 insertions(+)
diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h
index 6f03c72..0addfec 100644
--- a/arch/mips/include/asm/mipsregs.h
+++ b/arch/mips/include/asm/mipsregs.h
@@ -50,10 +50,13 @@
#define CP0_WIRED $6
#define CP0_INFO $7
#define CP0_BADVADDR $8
+#define CP0_BADINSTR $8, 1
+#define CP0_BADINSTRP $8, 2
#define CP0_COUNT $9
#define CP0_ENTRYHI $10
#define CP0_COMPARE $11
#define CP0_STATUS $12
+#define CP0_GUESTCTL0 $12, 6
#define CP0_CAUSE $13
#define CP0_EPC $14
#define CP0_PRID $15
@@ -623,6 +626,10 @@
#define MIPS_FPIR_L (_ULCAST_(1) << 21)
#define MIPS_FPIR_F64 (_ULCAST_(1) << 22)
+/* Bits in the MIPS VZ GuestCtl0 Register */
+#define MIPS_GUESTCTL0B_GM 31
+#define MIPS_GUESTCTL0F_GM (_ULCAST_(1) << MIPS_GUESTCTL0B_GM)
+
#ifndef __ASSEMBLY__
/*
@@ -851,6 +858,144 @@ do { \
local_irq_restore(__flags); \
} while (0)
+/*
+ * Macros to access the VZ Guest system control coprocessor
+ */
+
+#define __read_32bit_gc0_register(source, sel) \
+ ({ int __res; \
+ __asm__ __volatile__( \
+ ".set mips64r2\n\t" \
+ ".set\tvirt\n\t" \
+ ".ifeq 0-" #sel "\n\t" \
+ "mfgc0\t%0, " #source ", 0\n\t" \
+ ".endif\n\t" \
+ ".ifeq 1-" #sel "\n\t" \
+ "mfgc0\t%0, " #source ", 1\n\t" \
+ ".endif\n\t" \
+ ".ifeq 2-" #sel "\n\t" \
+ "mfgc0\t%0, " #source ", 2\n\t" \
+ ".endif\n\t" \
+ ".ifeq 3-" #sel "\n\t" \
+ "mfgc0\t%0, " #source ", 3\n\t" \
+ ".endif\n\t" \
+ ".ifeq 4-" #sel "\n\t" \
+ "mfgc0\t%0, " #source ", 4\n\t" \
+ ".endif\n\t" \
+ ".ifeq 5-" #sel "\n\t" \
+ "mfgc0\t%0, " #source ", 5\n\t" \
+ ".endif\n\t" \
+ ".ifeq 6-" #sel "\n\t" \
+ "mfgc0\t%0, " #source ", 6\n\t" \
+ ".endif\n\t" \
+ ".ifeq 7-" #sel "\n\t" \
+ "mfgc0\t%0, " #source ", 7\n\t" \
+ ".endif\n\t" \
+ ".set\tmips0" \
+ : "=r" (__res)); \
+ __res; \
+})
+
+#define __read_64bit_gc0_register(source, sel) \
+ ({ unsigned long long __res; \
+ __asm__ __volatile__( \
+ ".set mips64r2\n\t" \
+ ".set\tvirt\n\t" \
+ ".ifeq 0-" #sel "\n\t" \
+ "dmfgc0\t%0, " #source ", 0\n\t" \
+ ".endif\n\t" \
+ ".ifeq 1-" #sel "\n\t" \
+ "dmfgc0\t%0, " #source ", 1\n\t" \
+ ".endif\n\t" \
+ ".ifeq 2-" #sel "\n\t" \
+ "dmfgc0\t%0, " #source ", 2\n\t" \
+ ".endif\n\t" \
+ ".ifeq 3-" #sel "\n\t" \
+ "dmfgc0\t%0, " #source ", 3\n\t" \
+ ".endif\n\t" \
+ ".ifeq 4-" #sel "\n\t" \
+ "dmfgc0\t%0, " #source ", 4\n\t" \
+ ".endif\n\t" \
+ ".ifeq 5-" #sel "\n\t" \
+ "dmfgc0\t%0, " #source ", 5\n\t" \
+ ".endif\n\t" \
+ ".ifeq 6-" #sel "\n\t" \
+ "dmfgc0\t%0, " #source ", 6\n\t" \
+ ".endif\n\t" \
+ ".ifeq 7-" #sel "\n\t" \
+ "dmfgc0\t%0, " #source ", 7\n\t" \
+ ".endif\n\t" \
+ ".set\tmips0" \
+ : "=r" (__res)); \
+ __res; \
+})
+
+#define __write_32bit_gc0_register(source, sel, value) \
+do { \
+ __asm__ __volatile__( \
+ ".set mips64r2\n\t" \
+ ".set\tvirt\n\t" \
+ ".ifeq 0-" #sel "\n\t" \
+ "mtgc0\t%z0, " #source ", 0\n\t" \
+ ".endif\n\t" \
+ ".ifeq 1-" #sel "\n\t" \
+ "mtgc0\t%z0, " #source ", 1\n\t" \
+ ".endif\n\t" \
+ ".ifeq 2-" #sel "\n\t" \
+ "mtgc0\t%z0, " #source ", 2\n\t" \
+ ".endif\n\t" \
+ ".ifeq 3-" #sel "\n\t" \
+ "mtgc0\t%z0, " #source ", 3\n\t" \
+ ".endif\n\t" \
+ ".ifeq 4-" #sel "\n\t" \
+ "mtgc0\t%z0, " #source ", 4\n\t" \
+ ".endif\n\t" \
+ ".ifeq 5-" #sel "\n\t" \
+ "mtgc0\t%z0, " #source ", 5\n\t" \
+ ".endif\n\t" \
+ ".ifeq 6-" #sel "\n\t" \
+ "mtgc0\t%z0, " #source ", 6\n\t" \
+ ".endif\n\t" \
+ ".ifeq 7-" #sel "\n\t" \
+ "mtgc0\t%z0, " #source ", 7\n\t" \
+ ".endif\n\t" \
+ ".set\tmips0" \
+ : : "Jr" ((unsigned int)(value))); \
+} while (0)
+
+#define __write_64bit_gc0_register(source, sel, value) \
+do { \
+ __asm__ __volatile__( \
+ ".set mips64r2\n\t" \
+ ".set\tvirt\n\t" \
+ ".ifeq 0-" #sel "\n\t" \
+ "dmtgc0\t%z0, " #source ", 0\n\t" \
+ ".endif\n\t" \
+ ".ifeq 1-" #sel "\n\t" \
+ "dmtgc0\t%z0, " #source ", 1\n\t" \
+ ".endif\n\t" \
+ ".ifeq 2-" #sel "\n\t" \
+ "dmtgc0\t%z0, " #source ", 2\n\t" \
+ ".endif\n\t" \
+ ".ifeq 3-" #sel "\n\t" \
+ "dmtgc0\t%z0, " #source ", 3\n\t" \
+ ".endif\n\t" \
+ ".ifeq 4-" #sel "\n\t" \
+ "dmtgc0\t%z0, " #source ", 4\n\t" \
+ ".endif\n\t" \
+ ".ifeq 5-" #sel "\n\t" \
+ "dmtgc0\t%z0, " #source ", 5\n\t" \
+ ".endif\n\t" \
+ ".ifeq 6-" #sel "\n\t" \
+ "dmtgc0\t%z0, " #source ", 6\n\t" \
+ ".endif\n\t" \
+ ".ifeq 7-" #sel "\n\t" \
+ "dmtgc0\t%z0, " #source ", 7\n\t" \
+ ".endif\n\t" \
+ ".set\tmips0" \
+ : : "Jr" (value)); \
+} while (0)
+
#define read_c0_index() __read_32bit_c0_register($0, 0)
#define write_c0_index(val) __write_32bit_c0_register($0, 0, val)
@@ -889,6 +1034,12 @@ do { \
#define read_c0_badvaddr() __read_ulong_c0_register($8, 0)
#define write_c0_badvaddr(val) __write_ulong_c0_register($8, 0, val)
+#define read_c0_badinstr() __read_32bit_c0_register($8, 1)
+#define write_c0_badinstr(val) __write_32bit_c0_register($8, 1, val)
+
+#define read_c0_badinstrp() __read_32bit_c0_register($8, 2)
+#define write_c0_badinstrp(val) __write_32bit_c0_register($8, 2, val)
+
#define read_c0_count() __read_32bit_c0_register($9, 0)
#define write_c0_count(val) __write_32bit_c0_register($9, 0, val)
@@ -1162,6 +1313,93 @@ do { \
#define read_c0_brcm_sleepcount() __read_32bit_c0_register($22, 7)
#define write_c0_brcm_sleepcount(val) __write_32bit_c0_register($22, 7, val)
+/* MIPS VZ */
+#define read_c0_guestctl0() __read_32bit_c0_register($12, 6)
+#define write_c0_guestctl0(val) __write_32bit_c0_register($12, 6, val)
+
+#define read_c0_guestctl1() __read_32bit_c0_register($10, 4)
+#define write_c0_guestctl1(val) __write_32bit_c0_register($10, 4, val)
+
+#define read_c0_guestctl2() __read_32bit_c0_register($10, 5)
+#define write_c0_guestctl2(val) __write_32bit_c0_register($10, 5, val)
+
+#define read_c0_guestctl3() __read_32bit_c0_register($10, 6)
+#define write_c0_guestctl3(val) __write_32bit_c0_register($10, 6, val)
+
+#define read_c0_gtoffset() __read_32bit_c0_register($12, 7)
+#define write_c0_gtoffset(val) __write_32bit_c0_register($12, 7, val)
+
+#define read_gc0_index() __read_32bit_gc0_register($0, 0)
+#define write_gc0_index(val) __write_32bit_gc0_register($0, 0, val)
+
+#define read_gc0_entrylo0() __read_64bit_gc0_register($2, 0)
+#define write_gc0_entrylo0(val) __write_64bit_gc0_register($2, 0, val)
+
+#define read_gc0_entrylo1() __read_64bit_gc0_register($3, 0)
+#define write_gc0_entrylo1(val) __write_64bit_gc0_register($3, 0, val)
+
+#define read_gc0_context() __read_64bit_gc0_register($4, 0)
+#define write_gc0_context(val) __write_64bit_gc0_register($4, 0, val)
+
+#define read_gc0_userlocal() __read_64bit_gc0_register($4, 2)
+#define write_gc0_userlocal(val) __write_64bit_gc0_register($4, 2, val)
+
+#define read_gc0_pagemask() __read_32bit_gc0_register($5, 0)
+#define write_gc0_pagemask(val) __write_32bit_gc0_register($5, 0, val)
+
+#define read_gc0_pagegrain() __read_32bit_gc0_register($5, 1)
+#define write_gc0_pagegrain(val) __write_32bit_gc0_register($5, 1, val)
+
+#define read_gc0_wired() __read_32bit_gc0_register($6, 0)
+#define write_gc0_wired(val) __write_32bit_gc0_register($6, 0, val)
+
+#define read_gc0_hwrena() __read_32bit_gc0_register($7, 0)
+#define write_gc0_hwrena(val) __write_32bit_gc0_register($7, 0, val)
+
+#define read_gc0_badvaddr() __read_64bit_gc0_register($8, 0)
+#define write_gc0_badvaddr(val) __write_64bit_gc0_register($8, 0, val)
+
+#define read_gc0_count() __read_32bit_gc0_register($9, 0)
+/* Not possible to write gc0_count. */
+
+#define read_gc0_entryhi() __read_64bit_gc0_register($10, 0)
+#define write_gc0_entryhi(val) __write_64bit_gc0_register($10, 0, val)
+
+#define read_gc0_compare() __read_32bit_gc0_register($11, 0)
+#define write_gc0_compare(val) __write_32bit_gc0_register($11, 0, val)
+
+#define read_gc0_status() __read_32bit_gc0_register($12, 0)
+#define write_gc0_status(val) __write_32bit_gc0_register($12, 0, val)
+
+#define read_gc0_cause() __read_32bit_gc0_register($13, 0)
+#define write_gc0_cause(val) __write_32bit_gc0_register($13, 0, val)
+
+#define read_gc0_ebase() __read_64bit_gc0_register($15, 1)
+#define write_gc0_ebase(val) __write_64bit_gc0_register($15, 1, val)
+
+#define read_gc0_config() __read_32bit_gc0_register($16, 0)
+#define read_gc0_config1() __read_32bit_gc0_register($16, 1)
+#define read_gc0_config2() __read_32bit_gc0_register($16, 2)
+#define read_gc0_config3() __read_32bit_gc0_register($16, 3)
+#define read_gc0_config4() __read_32bit_gc0_register($16, 4)
+#define read_gc0_config5() __read_32bit_gc0_register($16, 5)
+#define read_gc0_config6() __read_32bit_gc0_register($16, 6)
+#define read_gc0_config7() __read_32bit_gc0_register($16, 7)
+#define write_gc0_config(val) __write_32bit_gc0_register($16, 0, val)
+#define write_gc0_config1(val) __write_32bit_gc0_register($16, 1, val)
+#define write_gc0_config2(val) __write_32bit_gc0_register($16, 2, val)
+#define write_gc0_config3(val) __write_32bit_gc0_register($16, 3, val)
+#define write_gc0_config4(val) __write_32bit_gc0_register($16, 4, val)
+#define write_gc0_config5(val) __write_32bit_gc0_register($16, 5, val)
+#define write_gc0_config6(val) __write_32bit_gc0_register($16, 6, val)
+#define write_gc0_config7(val) __write_32bit_gc0_register($16, 7, val)
+
+#define read_gc0_xcontext() __read_64bit_gc0_register($20, 0)
+#define write_gc0_xcontext(val) __write_64bit_gc0_register($20, 0, val)
+
+#define read_gc0_kscratch(idx) __read_64bit_gc0_register($31, (idx))
+#define write_gc0_kscratch(idx, val) __write_64bit_gc0_register($31, (idx), val)
+
/*
* Macros to access the floating point coprocessor control registers
*/
@@ -1633,6 +1871,28 @@ static inline void tlb_write_random(void)
".set reorder");
}
+static inline void guest_tlb_write_indexed(void)
+{
+ __asm__ __volatile__(
+ ".set push\n\t"
+ ".set mips64r2\n\t"
+ ".set virt\n\t"
+ ".set noreorder\n\t"
+ "tlbgwi\n\t"
+ ".set pop");
+}
+
+static inline void guest_tlb_read(void)
+{
+ __asm__ __volatile__(
+ ".set push\n\t"
+ ".set mips64r2\n\t"
+ ".set virt\n\t"
+ ".set noreorder\n\t"
+ "tlbgr\n\t"
+ ".set pop");
+}
+
/*
* Manipulate bits in a c0 register.
*/
--
1.7.11.7
next prev parent reply other threads:[~2013-06-07 23:09 UTC|newest]
Thread overview: 81+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-06-07 23:03 [PATCH 00/31] KVM/MIPS: Implement hardware virtualization via the MIPS-VZ extensions David Daney
2013-06-07 23:03 ` [PATCH 01/31] MIPS: Move allocate_kscratch to cpu-probe.c and make it public David Daney
2013-06-14 11:41 ` Ralf Baechle
2013-06-14 13:11 ` Ralf Baechle
2013-06-07 23:03 ` [PATCH 02/31] MIPS: Save and restore K0/K1 when CONFIG_KVM_MIPSVZ David Daney
2013-06-07 23:03 ` [PATCH 03/31] mips/kvm: Fix 32-bitisms in kvm_locore.S David Daney
2013-06-14 13:09 ` Ralf Baechle
2013-06-14 13:21 ` Sergei Shtylyov
2013-06-07 23:03 ` [PATCH 04/31] mips/kvm: Add casts to avoid pointer width mismatch build failures David Daney
2013-06-14 13:14 ` Ralf Baechle
2013-06-07 23:03 ` [PATCH 05/31] mips/kvm: Use generic cache flushing functions David Daney
2013-06-14 13:17 ` Ralf Baechle
2013-06-07 23:03 ` [PATCH 06/31] mips/kvm: Rename kvm_vcpu_arch.pc to kvm_vcpu_arch.epc David Daney
2013-06-14 13:18 ` Ralf Baechle
2013-06-07 23:03 ` [PATCH 07/31] mips/kvm: Rename VCPU_registername to KVM_VCPU_ARCH_registername David Daney
2013-06-14 13:18 ` Ralf Baechle
2013-06-07 23:03 ` [PATCH 08/31] mips/kvm: Fix code formatting in arch/mips/kvm/kvm_locore.S David Daney
2013-06-14 13:21 ` Ralf Baechle
2013-06-07 23:03 ` [PATCH 09/31] mips/kvm: Factor trap-and-emulate support into a pluggable implementation David Daney
2013-06-14 13:22 ` Ralf Baechle
2013-06-07 23:03 ` [PATCH 10/31] mips/kvm: Implement ioctls to get and set FPU registers David Daney
2013-06-14 16:11 ` Ralf Baechle
2013-06-07 23:03 ` [PATCH 11/31] MIPS: Rearrange branch.c so it can be used by kvm code David Daney
2013-06-14 22:03 ` Ralf Baechle
2013-06-07 23:03 ` [PATCH 12/31] MIPS: Add instruction format information for WAIT, MTC0, MFC0, et al David Daney
2013-06-14 22:07 ` Ralf Baechle
2013-06-07 23:03 ` David Daney [this message]
2013-06-14 22:10 ` [PATCH 13/31] mips/kvm: Add accessors for MIPS VZ registers Ralf Baechle
2013-06-07 23:03 ` [PATCH 14/31] mips/kvm: Add thread_info flag to indicate operation in MIPS VZ Guest Mode David Daney
2013-06-14 22:10 ` Ralf Baechle
2013-06-07 23:03 ` [PATCH 15/31] mips/kvm: Exception handling to leave and reenter guest mode David Daney
2013-06-15 10:00 ` Ralf Baechle
2013-10-11 12:51 ` James Hogan
2013-06-07 23:03 ` [PATCH 16/31] mips/kvm: Add exception handler for MIPSVZ Guest exceptions David Daney
2013-06-15 10:23 ` Ralf Baechle
2013-06-07 23:03 ` [PATCH 17/31] MIPS: Quit exposing Kconfig symbols in uapi headers David Daney
2013-06-14 11:12 ` Ralf Baechle
2013-06-15 17:13 ` Paolo Bonzini
2013-06-07 23:03 ` [PATCH 18/31] mips/kvm: Add pt_regs slots for BadInstr and BadInstrP David Daney
2013-06-15 10:25 ` Ralf Baechle
2013-06-07 23:03 ` [PATCH 19/31] mips/kvm: Add host definitions for MIPS VZ based host David Daney
2013-06-16 8:49 ` Ralf Baechle
2013-06-07 23:03 ` [PATCH 20/31] mips/kvm: Hook into TLB fault handlers David Daney
2013-06-07 23:34 ` Sergei Shtylyov
2013-06-08 0:15 ` David Daney
2013-06-16 8:51 ` Ralf Baechle
2013-06-07 23:03 ` [PATCH 21/31] mips/kvm: Allow set_except_vector() to be used from MIPSVZ code David Daney
2013-06-16 11:22 ` Ralf Baechle
2013-06-07 23:03 ` [PATCH 22/31] mips/kvm: Split get_new_mmu_context into two parts David Daney
2013-06-16 11:26 ` Ralf Baechle
2013-06-07 23:03 ` [PATCH 23/31] mips/kvm: Hook into CP unusable exception handler David Daney
2013-06-16 11:28 ` Ralf Baechle
2013-06-07 23:03 ` [PATCH 24/31] mips/kvm: Add thread_struct fields used by MIPSVZ hosts David Daney
2013-06-16 11:29 ` Ralf Baechle
2013-06-07 23:03 ` [PATCH 25/31] mips/kvm: Add some asm-offsets constants used by MIPSVZ David Daney
2013-06-16 11:31 ` Ralf Baechle
2013-08-06 17:23 ` David Daney
2013-06-07 23:03 ` [PATCH 26/31] mips/kvm: Split up Kconfig and Makefile definitions in preperation for MIPSVZ David Daney
2013-06-16 11:33 ` Ralf Baechle
2013-06-07 23:03 ` [PATCH 27/31] mips/kvm: Gate the use of kvm_local_flush_tlb_all() by KVM_MIPSTE David Daney
2013-06-16 11:42 ` Ralf Baechle
2013-06-07 23:03 ` [PATCH 28/31] mips/kvm: Only use KVM_COALESCED_MMIO_PAGE_OFFSET with KVM_MIPSTE David Daney
2013-06-16 12:03 ` Ralf Baechle
2013-06-07 23:03 ` [PATCH 29/31] mips/kvm: Add MIPSVZ support David Daney
2013-06-16 11:47 ` Ralf Baechle
2013-06-07 23:03 ` [PATCH 30/31] mips/kvm: Enable MIPSVZ in Kconfig/Makefile David Daney
2013-06-16 11:44 ` Ralf Baechle
2013-06-07 23:03 ` [PATCH 31/31] mips/kvm: Allow for upto 8 KVM vcpus per vm David Daney
2013-06-16 11:37 ` Ralf Baechle
2013-06-07 23:15 ` [PATCH 00/31] KVM/MIPS: Implement hardware virtualization via the MIPS-VZ extensions David Daney
2013-06-09 7:31 ` Gleb Natapov
2013-06-09 23:23 ` David Daney
2013-06-09 23:40 ` Maciej W. Rozycki
2013-06-10 11:16 ` Ralf Baechle
2013-06-10 6:18 ` Gleb Natapov
2013-06-10 16:37 ` Sanjay Lal
2013-06-16 11:59 ` Ralf Baechle
2013-06-10 16:43 ` Sanjay Lal
2013-06-10 17:14 ` David Daney
2013-06-14 11:12 ` Ralf Baechle
2013-06-19 9:06 ` Ralf Baechle
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